1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2022 Intel Corporation.
3
4 #include <linux/acpi.h>
5 #include <linux/clk.h>
6 #include <linux/delay.h>
7 #include <linux/i2c.h>
8 #include <linux/module.h>
9 #include <linux/pm_runtime.h>
10 #include <linux/regulator/consumer.h>
11 #include <media/v4l2-ctrls.h>
12 #include <media/v4l2-device.h>
13 #include <media/v4l2-fwnode.h>
14
15 #define OV08D10_SCLK 144000000ULL
16 #define OV08D10_XVCLK_19_2 19200000
17 #define OV08D10_ROWCLK 36000
18 #define OV08D10_DATA_LANES 2
19 #define OV08D10_RGB_DEPTH 10
20
21 #define OV08D10_REG_PAGE 0xfd
22 #define OV08D10_REG_GLOBAL_EFFECTIVE 0x01
23 #define OV08D10_REG_CHIP_ID_0 0x00
24 #define OV08D10_REG_CHIP_ID_1 0x01
25 #define OV08D10_ID_MASK GENMASK(15, 0)
26 #define OV08D10_CHIP_ID 0x5608
27
28 #define OV08D10_REG_MODE_SELECT 0xa0
29 #define OV08D10_MODE_STANDBY 0x00
30 #define OV08D10_MODE_STREAMING 0x01
31
32 /* vertical-timings from sensor */
33 #define OV08D10_REG_VTS_H 0x05
34 #define OV08D10_REG_VTS_L 0x06
35 #define OV08D10_VTS_MAX 0x7fff
36
37 /* Exposure controls from sensor */
38 #define OV08D10_REG_EXPOSURE_H 0x02
39 #define OV08D10_REG_EXPOSURE_M 0x03
40 #define OV08D10_REG_EXPOSURE_L 0x04
41 #define OV08D10_EXPOSURE_MIN 6
42 #define OV08D10_EXPOSURE_MAX_MARGIN 6
43 #define OV08D10_EXPOSURE_STEP 1
44
45 /* Analog gain controls from sensor */
46 #define OV08D10_REG_ANALOG_GAIN 0x24
47 #define OV08D10_ANAL_GAIN_MIN 128
48 #define OV08D10_ANAL_GAIN_MAX 2047
49 #define OV08D10_ANAL_GAIN_STEP 1
50
51 /* Digital gain controls from sensor */
52 #define OV08D10_REG_MWB_DGAIN_C 0x21
53 #define OV08D10_REG_MWB_DGAIN_F 0x22
54 #define OV08D10_DGTL_GAIN_MIN 0
55 #define OV08D10_DGTL_GAIN_MAX 4095
56 #define OV08D10_DGTL_GAIN_STEP 1
57 #define OV08D10_DGTL_GAIN_DEFAULT 1024
58
59 /* Test Pattern Control */
60 #define OV08D10_REG_TEST_PATTERN 0x12
61 #define OV08D10_TEST_PATTERN_ENABLE 0x01
62 #define OV08D10_TEST_PATTERN_DISABLE 0x00
63
64 /* Flip Mirror Controls from sensor */
65 #define OV08D10_REG_FLIP_OPT 0x32
66 #define OV08D10_REG_FLIP_MASK 0x3
67
68 #define to_ov08d10(_sd) container_of(_sd, struct ov08d10, sd)
69
70 struct ov08d10_reg {
71 u8 address;
72 u8 val;
73 };
74
75 struct ov08d10_reg_list {
76 u32 num_of_regs;
77 const struct ov08d10_reg *regs;
78 };
79
80 struct ov08d10_link_freq_config {
81 const struct ov08d10_reg_list reg_list;
82 };
83
84 struct ov08d10_mode {
85 /* Frame width in pixels */
86 u32 width;
87
88 /* Frame height in pixels */
89 u32 height;
90
91 /* Horizontal timining size */
92 u32 hts;
93
94 /* Default vertical timining size */
95 u32 vts_def;
96
97 /* Min vertical timining size */
98 u32 vts_min;
99
100 /* Link frequency needed for this resolution */
101 u32 link_freq_index;
102
103 /* Sensor register settings for this resolution */
104 const struct ov08d10_reg_list reg_list;
105
106 /* Number of data lanes */
107 u8 data_lanes;
108 };
109
110 /* 3280x2460, 3264x2448 need 720Mbps/lane, 2 lanes */
111 static const struct ov08d10_reg mipi_data_rate_720mbps[] = {
112 {0xfd, 0x00},
113 {0x11, 0x2a},
114 {0x14, 0x43},
115 {0x1a, 0x04},
116 {0x1b, 0xe1},
117 {0x1e, 0x13},
118 {0xb7, 0x02}
119 };
120
121 /* 1632x1224 needs 360Mbps/lane, 2 lanes */
122 static const struct ov08d10_reg mipi_data_rate_360mbps[] = {
123 {0xfd, 0x00},
124 {0x1a, 0x04},
125 {0x1b, 0xe1},
126 {0x1d, 0x00},
127 {0x1c, 0x19},
128 {0x11, 0x2a},
129 {0x14, 0x54},
130 {0x1e, 0x13},
131 {0xb7, 0x02}
132 };
133
134 static const struct ov08d10_reg lane_2_mode_3280x2460[] = {
135 /* 3280x2460 resolution */
136 {0xfd, 0x01},
137 {0x12, 0x00},
138 {0x03, 0x12},
139 {0x04, 0x58},
140 {0x07, 0x05},
141 {0x21, 0x02},
142 {0x24, 0x30},
143 {0x33, 0x03},
144 {0x01, 0x03},
145 {0x19, 0x10},
146 {0x42, 0x55},
147 {0x43, 0x00},
148 {0x47, 0x07},
149 {0x48, 0x08},
150 {0xb2, 0x7f},
151 {0xb3, 0x7b},
152 {0xbd, 0x08},
153 {0xd2, 0x57},
154 {0xd3, 0x10},
155 {0xd4, 0x08},
156 {0xd5, 0x08},
157 {0xd6, 0x06},
158 {0xb1, 0x00},
159 {0xb4, 0x00},
160 {0xb7, 0x0a},
161 {0xbc, 0x44},
162 {0xbf, 0x48},
163 {0xc1, 0x10},
164 {0xc3, 0x24},
165 {0xc8, 0x03},
166 {0xc9, 0xf8},
167 {0xe1, 0x33},
168 {0xe2, 0xbb},
169 {0x51, 0x0c},
170 {0x52, 0x0a},
171 {0x57, 0x8c},
172 {0x59, 0x09},
173 {0x5a, 0x08},
174 {0x5e, 0x10},
175 {0x60, 0x02},
176 {0x6d, 0x5c},
177 {0x76, 0x16},
178 {0x7c, 0x11},
179 {0x90, 0x28},
180 {0x91, 0x16},
181 {0x92, 0x1c},
182 {0x93, 0x24},
183 {0x95, 0x48},
184 {0x9c, 0x06},
185 {0xca, 0x0c},
186 {0xce, 0x0d},
187 {0xfd, 0x01},
188 {0xc0, 0x00},
189 {0xdd, 0x18},
190 {0xde, 0x19},
191 {0xdf, 0x32},
192 {0xe0, 0x70},
193 {0xfd, 0x01},
194 {0xc2, 0x05},
195 {0xd7, 0x88},
196 {0xd8, 0x77},
197 {0xd9, 0x00},
198 {0xfd, 0x07},
199 {0x00, 0xf8},
200 {0x01, 0x2b},
201 {0x05, 0x40},
202 {0x08, 0x06},
203 {0x09, 0x11},
204 {0x28, 0x6f},
205 {0x2a, 0x20},
206 {0x2b, 0x05},
207 {0x5e, 0x10},
208 {0x52, 0x00},
209 {0x53, 0x7c},
210 {0x54, 0x00},
211 {0x55, 0x7c},
212 {0x56, 0x00},
213 {0x57, 0x7c},
214 {0x58, 0x00},
215 {0x59, 0x7c},
216 {0xfd, 0x02},
217 {0x9a, 0x30},
218 {0xa8, 0x02},
219 {0xfd, 0x02},
220 {0xa1, 0x01},
221 {0xa2, 0x09},
222 {0xa3, 0x9c},
223 {0xa5, 0x00},
224 {0xa6, 0x0c},
225 {0xa7, 0xd0},
226 {0xfd, 0x00},
227 {0x24, 0x01},
228 {0xc0, 0x16},
229 {0xc1, 0x08},
230 {0xc2, 0x30},
231 {0x8e, 0x0c},
232 {0x8f, 0xd0},
233 {0x90, 0x09},
234 {0x91, 0x9c},
235 {0xfd, 0x05},
236 {0x04, 0x40},
237 {0x07, 0x00},
238 {0x0d, 0x01},
239 {0x0f, 0x01},
240 {0x10, 0x00},
241 {0x11, 0x00},
242 {0x12, 0x0c},
243 {0x13, 0xcf},
244 {0x14, 0x00},
245 {0x15, 0x00},
246 {0xfd, 0x00},
247 {0x20, 0x0f},
248 {0xe7, 0x03},
249 {0xe7, 0x00}
250 };
251
252 static const struct ov08d10_reg lane_2_mode_3264x2448[] = {
253 /* 3264x2448 resolution */
254 {0xfd, 0x01},
255 {0x12, 0x00},
256 {0x03, 0x12},
257 {0x04, 0x58},
258 {0x07, 0x05},
259 {0x21, 0x02},
260 {0x24, 0x30},
261 {0x33, 0x03},
262 {0x01, 0x03},
263 {0x19, 0x10},
264 {0x42, 0x55},
265 {0x43, 0x00},
266 {0x47, 0x07},
267 {0x48, 0x08},
268 {0xb2, 0x7f},
269 {0xb3, 0x7b},
270 {0xbd, 0x08},
271 {0xd2, 0x57},
272 {0xd3, 0x10},
273 {0xd4, 0x08},
274 {0xd5, 0x08},
275 {0xd6, 0x06},
276 {0xb1, 0x00},
277 {0xb4, 0x00},
278 {0xb7, 0x0a},
279 {0xbc, 0x44},
280 {0xbf, 0x48},
281 {0xc1, 0x10},
282 {0xc3, 0x24},
283 {0xc8, 0x03},
284 {0xc9, 0xf8},
285 {0xe1, 0x33},
286 {0xe2, 0xbb},
287 {0x51, 0x0c},
288 {0x52, 0x0a},
289 {0x57, 0x8c},
290 {0x59, 0x09},
291 {0x5a, 0x08},
292 {0x5e, 0x10},
293 {0x60, 0x02},
294 {0x6d, 0x5c},
295 {0x76, 0x16},
296 {0x7c, 0x11},
297 {0x90, 0x28},
298 {0x91, 0x16},
299 {0x92, 0x1c},
300 {0x93, 0x24},
301 {0x95, 0x48},
302 {0x9c, 0x06},
303 {0xca, 0x0c},
304 {0xce, 0x0d},
305 {0xfd, 0x01},
306 {0xc0, 0x00},
307 {0xdd, 0x18},
308 {0xde, 0x19},
309 {0xdf, 0x32},
310 {0xe0, 0x70},
311 {0xfd, 0x01},
312 {0xc2, 0x05},
313 {0xd7, 0x88},
314 {0xd8, 0x77},
315 {0xd9, 0x00},
316 {0xfd, 0x07},
317 {0x00, 0xf8},
318 {0x01, 0x2b},
319 {0x05, 0x40},
320 {0x08, 0x06},
321 {0x09, 0x11},
322 {0x28, 0x6f},
323 {0x2a, 0x20},
324 {0x2b, 0x05},
325 {0x5e, 0x10},
326 {0x52, 0x00},
327 {0x53, 0x7c},
328 {0x54, 0x00},
329 {0x55, 0x7c},
330 {0x56, 0x00},
331 {0x57, 0x7c},
332 {0x58, 0x00},
333 {0x59, 0x7c},
334 {0xfd, 0x02},
335 {0x9a, 0x30},
336 {0xa8, 0x02},
337 {0xfd, 0x02},
338 {0xa1, 0x09},
339 {0xa2, 0x09},
340 {0xa3, 0x90},
341 {0xa5, 0x08},
342 {0xa6, 0x0c},
343 {0xa7, 0xc0},
344 {0xfd, 0x00},
345 {0x24, 0x01},
346 {0xc0, 0x16},
347 {0xc1, 0x08},
348 {0xc2, 0x30},
349 {0x8e, 0x0c},
350 {0x8f, 0xc0},
351 {0x90, 0x09},
352 {0x91, 0x90},
353 {0xfd, 0x05},
354 {0x04, 0x40},
355 {0x07, 0x00},
356 {0x0d, 0x01},
357 {0x0f, 0x01},
358 {0x10, 0x00},
359 {0x11, 0x00},
360 {0x12, 0x0c},
361 {0x13, 0xcf},
362 {0x14, 0x00},
363 {0x15, 0x00},
364 {0xfd, 0x00},
365 {0x20, 0x0f},
366 {0xe7, 0x03},
367 {0xe7, 0x00}
368 };
369
370 static const struct ov08d10_reg lane_2_mode_1632x1224[] = {
371 /* 1640x1232 resolution */
372 {0xfd, 0x01},
373 {0x1a, 0x0a},
374 {0x1b, 0x08},
375 {0x2a, 0x01},
376 {0x2b, 0x9a},
377 {0xfd, 0x01},
378 {0x12, 0x00},
379 {0x03, 0x05},
380 {0x04, 0xe2},
381 {0x07, 0x05},
382 {0x21, 0x02},
383 {0x24, 0x30},
384 {0x33, 0x03},
385 {0x31, 0x06},
386 {0x33, 0x03},
387 {0x01, 0x03},
388 {0x19, 0x10},
389 {0x42, 0x55},
390 {0x43, 0x00},
391 {0x47, 0x07},
392 {0x48, 0x08},
393 {0xb2, 0x7f},
394 {0xb3, 0x7b},
395 {0xbd, 0x08},
396 {0xd2, 0x57},
397 {0xd3, 0x10},
398 {0xd4, 0x08},
399 {0xd5, 0x08},
400 {0xd6, 0x06},
401 {0xb1, 0x00},
402 {0xb4, 0x00},
403 {0xb7, 0x0a},
404 {0xbc, 0x44},
405 {0xbf, 0x48},
406 {0xc1, 0x10},
407 {0xc3, 0x24},
408 {0xc8, 0x03},
409 {0xc9, 0xf8},
410 {0xe1, 0x33},
411 {0xe2, 0xbb},
412 {0x51, 0x0c},
413 {0x52, 0x0a},
414 {0x57, 0x8c},
415 {0x59, 0x09},
416 {0x5a, 0x08},
417 {0x5e, 0x10},
418 {0x60, 0x02},
419 {0x6d, 0x5c},
420 {0x76, 0x16},
421 {0x7c, 0x1a},
422 {0x90, 0x28},
423 {0x91, 0x16},
424 {0x92, 0x1c},
425 {0x93, 0x24},
426 {0x95, 0x48},
427 {0x9c, 0x06},
428 {0xca, 0x0c},
429 {0xce, 0x0d},
430 {0xfd, 0x01},
431 {0xc0, 0x00},
432 {0xdd, 0x18},
433 {0xde, 0x19},
434 {0xdf, 0x32},
435 {0xe0, 0x70},
436 {0xfd, 0x01},
437 {0xc2, 0x05},
438 {0xd7, 0x88},
439 {0xd8, 0x77},
440 {0xd9, 0x00},
441 {0xfd, 0x07},
442 {0x00, 0xf8},
443 {0x01, 0x2b},
444 {0x05, 0x40},
445 {0x08, 0x03},
446 {0x09, 0x08},
447 {0x28, 0x6f},
448 {0x2a, 0x20},
449 {0x2b, 0x05},
450 {0x2c, 0x01},
451 {0x50, 0x02},
452 {0x51, 0x03},
453 {0x5e, 0x00},
454 {0x52, 0x00},
455 {0x53, 0x7c},
456 {0x54, 0x00},
457 {0x55, 0x7c},
458 {0x56, 0x00},
459 {0x57, 0x7c},
460 {0x58, 0x00},
461 {0x59, 0x7c},
462 {0xfd, 0x02},
463 {0x9a, 0x30},
464 {0xa8, 0x02},
465 {0xfd, 0x02},
466 {0xa9, 0x04},
467 {0xaa, 0xd0},
468 {0xab, 0x06},
469 {0xac, 0x68},
470 {0xa1, 0x09},
471 {0xa2, 0x04},
472 {0xa3, 0xc8},
473 {0xa5, 0x04},
474 {0xa6, 0x06},
475 {0xa7, 0x60},
476 {0xfd, 0x05},
477 {0x06, 0x80},
478 {0x18, 0x06},
479 {0x19, 0x68},
480 {0xfd, 0x00},
481 {0x24, 0x01},
482 {0xc0, 0x16},
483 {0xc1, 0x08},
484 {0xc2, 0x30},
485 {0x8e, 0x06},
486 {0x8f, 0x60},
487 {0x90, 0x04},
488 {0x91, 0xc8},
489 {0x93, 0x0e},
490 {0x94, 0x77},
491 {0x95, 0x77},
492 {0x96, 0x10},
493 {0x98, 0x88},
494 {0x9c, 0x1a},
495 {0xfd, 0x05},
496 {0x04, 0x40},
497 {0x07, 0x99},
498 {0x0d, 0x03},
499 {0x0f, 0x03},
500 {0x10, 0x00},
501 {0x11, 0x00},
502 {0x12, 0x0c},
503 {0x13, 0xcf},
504 {0x14, 0x00},
505 {0x15, 0x00},
506 {0xfd, 0x00},
507 {0x20, 0x0f},
508 {0xe7, 0x03},
509 {0xe7, 0x00},
510 };
511
512 static const char * const ov08d10_test_pattern_menu[] = {
513 "Disabled",
514 "Standard Color Bar",
515 };
516
517 struct ov08d10 {
518 struct device *dev;
519 struct clk *clk;
520
521 struct v4l2_subdev sd;
522 struct media_pad pad;
523 struct v4l2_ctrl_handler ctrl_handler;
524
525 /* V4L2 Controls */
526 struct v4l2_ctrl *link_freq;
527 struct v4l2_ctrl *pixel_rate;
528 struct v4l2_ctrl *vblank;
529 struct v4l2_ctrl *hblank;
530 struct v4l2_ctrl *vflip;
531 struct v4l2_ctrl *hflip;
532 struct v4l2_ctrl *exposure;
533
534 /* Current mode */
535 const struct ov08d10_mode *cur_mode;
536
537 /* To serialize asynchronus callbacks */
538 struct mutex mutex;
539
540 /* lanes index */
541 u8 nlanes;
542
543 const struct ov08d10_lane_cfg *priv_lane;
544 u8 modes_size;
545 };
546
547 struct ov08d10_lane_cfg {
548 const s64 link_freq_menu[2];
549 const struct ov08d10_link_freq_config link_freq_configs[2];
550 const struct ov08d10_mode sp_modes[3];
551 };
552
553 static const struct ov08d10_lane_cfg lane_cfg_2 = {
554 {
555 720000000,
556 360000000,
557 },
558 {{
559 .reg_list = {
560 .num_of_regs =
561 ARRAY_SIZE(mipi_data_rate_720mbps),
562 .regs = mipi_data_rate_720mbps,
563 }
564 },
565 {
566 .reg_list = {
567 .num_of_regs =
568 ARRAY_SIZE(mipi_data_rate_360mbps),
569 .regs = mipi_data_rate_360mbps,
570 }
571 }},
572 {{
573 .width = 3280,
574 .height = 2460,
575 .hts = 1840,
576 .vts_def = 2504,
577 .vts_min = 2504,
578 .reg_list = {
579 .num_of_regs = ARRAY_SIZE(lane_2_mode_3280x2460),
580 .regs = lane_2_mode_3280x2460,
581 },
582 .link_freq_index = 0,
583 .data_lanes = 2,
584 },
585 {
586 .width = 3264,
587 .height = 2448,
588 .hts = 1840,
589 .vts_def = 2504,
590 .vts_min = 2504,
591 .reg_list = {
592 .num_of_regs = ARRAY_SIZE(lane_2_mode_3264x2448),
593 .regs = lane_2_mode_3264x2448,
594 },
595 .link_freq_index = 0,
596 .data_lanes = 2,
597 },
598 {
599 .width = 1632,
600 .height = 1224,
601 .hts = 1912,
602 .vts_def = 3736,
603 .vts_min = 3736,
604 .reg_list = {
605 .num_of_regs = ARRAY_SIZE(lane_2_mode_1632x1224),
606 .regs = lane_2_mode_1632x1224,
607 },
608 .link_freq_index = 1,
609 .data_lanes = 2,
610 }}
611 };
612
ov08d10_get_format_code(struct ov08d10 * ov08d10)613 static u32 ov08d10_get_format_code(struct ov08d10 *ov08d10)
614 {
615 static const u32 codes[2][2] = {
616 { MEDIA_BUS_FMT_SGRBG10_1X10, MEDIA_BUS_FMT_SRGGB10_1X10},
617 { MEDIA_BUS_FMT_SBGGR10_1X10, MEDIA_BUS_FMT_SGBRG10_1X10},
618 };
619
620 return codes[ov08d10->vflip->val][ov08d10->hflip->val];
621 }
622
ov08d10_modes_num(const struct ov08d10 * ov08d10)623 static unsigned int ov08d10_modes_num(const struct ov08d10 *ov08d10)
624 {
625 unsigned int i, count = 0;
626
627 for (i = 0; i < ARRAY_SIZE(ov08d10->priv_lane->sp_modes); i++) {
628 if (ov08d10->priv_lane->sp_modes[i].width == 0)
629 break;
630 count++;
631 }
632
633 return count;
634 }
635
to_rate(const s64 * link_freq_menu,u32 f_index,u8 nlanes)636 static u64 to_rate(const s64 *link_freq_menu,
637 u32 f_index, u8 nlanes)
638 {
639 u64 pixel_rate = link_freq_menu[f_index] * 2 * nlanes;
640
641 do_div(pixel_rate, OV08D10_RGB_DEPTH);
642
643 return pixel_rate;
644 }
645
to_pixels_per_line(const s64 * link_freq_menu,u32 hts,u32 f_index,u8 nlanes)646 static u64 to_pixels_per_line(const s64 *link_freq_menu, u32 hts,
647 u32 f_index, u8 nlanes)
648 {
649 u64 ppl = hts * to_rate(link_freq_menu, f_index, nlanes);
650
651 do_div(ppl, OV08D10_SCLK);
652
653 return ppl;
654 }
655
ov08d10_write_reg_list(struct ov08d10 * ov08d10,const struct ov08d10_reg_list * r_list)656 static int ov08d10_write_reg_list(struct ov08d10 *ov08d10,
657 const struct ov08d10_reg_list *r_list)
658 {
659 struct i2c_client *client = v4l2_get_subdevdata(&ov08d10->sd);
660 unsigned int i;
661 int ret;
662
663 for (i = 0; i < r_list->num_of_regs; i++) {
664 ret = i2c_smbus_write_byte_data(client, r_list->regs[i].address,
665 r_list->regs[i].val);
666 if (ret) {
667 dev_err_ratelimited(ov08d10->dev,
668 "failed to write reg 0x%2.2x. error = %d",
669 r_list->regs[i].address, ret);
670 return ret;
671 }
672 }
673
674 return 0;
675 }
676
ov08d10_update_analog_gain(struct ov08d10 * ov08d10,u32 a_gain)677 static int ov08d10_update_analog_gain(struct ov08d10 *ov08d10, u32 a_gain)
678 {
679 struct i2c_client *client = v4l2_get_subdevdata(&ov08d10->sd);
680 u8 val;
681 int ret;
682
683 val = ((a_gain >> 3) & 0xFF);
684 /* CIS control registers */
685 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_PAGE, 0x01);
686 if (ret < 0)
687 return ret;
688
689 /* update AGAIN */
690 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_ANALOG_GAIN, val);
691 if (ret < 0)
692 return ret;
693
694 return i2c_smbus_write_byte_data(client,
695 OV08D10_REG_GLOBAL_EFFECTIVE, 0x01);
696 }
697
ov08d10_update_digital_gain(struct ov08d10 * ov08d10,u32 d_gain)698 static int ov08d10_update_digital_gain(struct ov08d10 *ov08d10, u32 d_gain)
699 {
700 struct i2c_client *client = v4l2_get_subdevdata(&ov08d10->sd);
701 u8 val;
702 int ret;
703
704 d_gain = (d_gain >> 1);
705 /* CIS control registers */
706 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_PAGE, 0x01);
707 if (ret < 0)
708 return ret;
709
710 val = ((d_gain >> 8) & 0x3F);
711 /* update DGAIN */
712 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_MWB_DGAIN_C, val);
713 if (ret < 0)
714 return ret;
715
716 val = d_gain & 0xFF;
717 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_MWB_DGAIN_F, val);
718 if (ret < 0)
719 return ret;
720
721 return i2c_smbus_write_byte_data(client,
722 OV08D10_REG_GLOBAL_EFFECTIVE, 0x01);
723 }
724
ov08d10_set_exposure(struct ov08d10 * ov08d10,u32 exposure)725 static int ov08d10_set_exposure(struct ov08d10 *ov08d10, u32 exposure)
726 {
727 struct i2c_client *client = v4l2_get_subdevdata(&ov08d10->sd);
728 u8 val;
729 u8 hts_h, hts_l;
730 u32 hts, cur_vts, exp_cal;
731 int ret;
732
733 cur_vts = ov08d10->cur_mode->vts_def;
734 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_PAGE, 0x01);
735 if (ret < 0)
736 return ret;
737
738 hts_h = i2c_smbus_read_byte_data(client, 0x37);
739 hts_l = i2c_smbus_read_byte_data(client, 0x38);
740 hts = ((hts_h << 8) | (hts_l));
741 exp_cal = 66 * OV08D10_ROWCLK / hts;
742 exposure = exposure * exp_cal / (cur_vts - OV08D10_EXPOSURE_MAX_MARGIN);
743 /* CIS control registers */
744 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_PAGE, 0x01);
745 if (ret < 0)
746 return ret;
747
748 /* update exposure */
749 val = ((exposure >> 16) & 0xFF);
750 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_EXPOSURE_H, val);
751 if (ret < 0)
752 return ret;
753
754 val = ((exposure >> 8) & 0xFF);
755 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_EXPOSURE_M, val);
756 if (ret < 0)
757 return ret;
758
759 val = exposure & 0xFF;
760 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_EXPOSURE_L, val);
761 if (ret < 0)
762 return ret;
763
764 return i2c_smbus_write_byte_data(client,
765 OV08D10_REG_GLOBAL_EFFECTIVE, 0x01);
766 }
767
ov08d10_set_vblank(struct ov08d10 * ov08d10,u32 vblank)768 static int ov08d10_set_vblank(struct ov08d10 *ov08d10, u32 vblank)
769 {
770 struct i2c_client *client = v4l2_get_subdevdata(&ov08d10->sd);
771 u8 val;
772 int ret;
773
774 /* CIS control registers */
775 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_PAGE, 0x01);
776 if (ret < 0)
777 return ret;
778
779 val = ((vblank >> 8) & 0xFF);
780 /* update vblank */
781 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_VTS_H, val);
782 if (ret < 0)
783 return ret;
784
785 val = vblank & 0xFF;
786 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_VTS_L, val);
787 if (ret < 0)
788 return ret;
789
790 return i2c_smbus_write_byte_data(client,
791 OV08D10_REG_GLOBAL_EFFECTIVE, 0x01);
792 }
793
ov08d10_test_pattern(struct ov08d10 * ov08d10,u32 pattern)794 static int ov08d10_test_pattern(struct ov08d10 *ov08d10, u32 pattern)
795 {
796 struct i2c_client *client = v4l2_get_subdevdata(&ov08d10->sd);
797 u8 val;
798 int ret;
799
800 if (pattern)
801 val = OV08D10_TEST_PATTERN_ENABLE;
802 else
803 val = OV08D10_TEST_PATTERN_DISABLE;
804
805 /* CIS control registers */
806 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_PAGE, 0x01);
807 if (ret < 0)
808 return ret;
809
810 ret = i2c_smbus_write_byte_data(client,
811 OV08D10_REG_TEST_PATTERN, val);
812 if (ret < 0)
813 return ret;
814
815 return i2c_smbus_write_byte_data(client,
816 OV08D10_REG_GLOBAL_EFFECTIVE, 0x01);
817 }
818
ov08d10_set_ctrl_flip(struct ov08d10 * ov08d10,u32 ctrl_val)819 static int ov08d10_set_ctrl_flip(struct ov08d10 *ov08d10, u32 ctrl_val)
820 {
821 struct i2c_client *client = v4l2_get_subdevdata(&ov08d10->sd);
822 u8 val;
823 int ret;
824
825 /* System control registers */
826 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_PAGE, 0x01);
827 if (ret < 0)
828 return ret;
829
830 ret = i2c_smbus_read_byte_data(client, OV08D10_REG_FLIP_OPT);
831 if (ret < 0)
832 return ret;
833
834 val = ret | (ctrl_val & OV08D10_REG_FLIP_MASK);
835
836 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_PAGE, 0x01);
837 if (ret < 0)
838 return ret;
839
840 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_FLIP_OPT, val);
841
842 if (ret < 0)
843 return ret;
844
845 return i2c_smbus_write_byte_data(client,
846 OV08D10_REG_GLOBAL_EFFECTIVE, 0x01);
847 }
848
ov08d10_set_ctrl(struct v4l2_ctrl * ctrl)849 static int ov08d10_set_ctrl(struct v4l2_ctrl *ctrl)
850 {
851 struct ov08d10 *ov08d10 = container_of(ctrl->handler,
852 struct ov08d10, ctrl_handler);
853 s64 exposure_max;
854 int ret;
855
856 /* Propagate change of current control to all related controls */
857 if (ctrl->id == V4L2_CID_VBLANK) {
858 /* Update max exposure while meeting expected vblanking */
859 exposure_max = ov08d10->cur_mode->height + ctrl->val -
860 OV08D10_EXPOSURE_MAX_MARGIN;
861 __v4l2_ctrl_modify_range(ov08d10->exposure,
862 ov08d10->exposure->minimum,
863 exposure_max, ov08d10->exposure->step,
864 exposure_max);
865 }
866
867 /* V4L2 controls values will be applied only when power is already up */
868 if (!pm_runtime_get_if_in_use(ov08d10->dev))
869 return 0;
870
871 switch (ctrl->id) {
872 case V4L2_CID_ANALOGUE_GAIN:
873 ret = ov08d10_update_analog_gain(ov08d10, ctrl->val);
874 break;
875
876 case V4L2_CID_DIGITAL_GAIN:
877 ret = ov08d10_update_digital_gain(ov08d10, ctrl->val);
878 break;
879
880 case V4L2_CID_EXPOSURE:
881 ret = ov08d10_set_exposure(ov08d10, ctrl->val);
882 break;
883
884 case V4L2_CID_VBLANK:
885 ret = ov08d10_set_vblank(ov08d10, ctrl->val);
886 break;
887
888 case V4L2_CID_TEST_PATTERN:
889 ret = ov08d10_test_pattern(ov08d10, ctrl->val);
890 break;
891
892 case V4L2_CID_HFLIP:
893 case V4L2_CID_VFLIP:
894 ret = ov08d10_set_ctrl_flip(ov08d10,
895 ov08d10->hflip->val |
896 ov08d10->vflip->val << 1);
897 break;
898
899 default:
900 ret = -EINVAL;
901 break;
902 }
903
904 pm_runtime_put(ov08d10->dev);
905
906 return ret;
907 }
908
909 static const struct v4l2_ctrl_ops ov08d10_ctrl_ops = {
910 .s_ctrl = ov08d10_set_ctrl,
911 };
912
ov08d10_init_controls(struct ov08d10 * ov08d10)913 static int ov08d10_init_controls(struct ov08d10 *ov08d10)
914 {
915 struct v4l2_ctrl_handler *ctrl_hdlr;
916 u8 link_freq_size;
917 s64 exposure_max;
918 s64 vblank_def;
919 s64 vblank_min;
920 s64 h_blank;
921 s64 pixel_rate_max;
922 const struct ov08d10_mode *mode;
923 int ret;
924
925 ctrl_hdlr = &ov08d10->ctrl_handler;
926 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8);
927 if (ret)
928 return ret;
929
930 ctrl_hdlr->lock = &ov08d10->mutex;
931 link_freq_size = ARRAY_SIZE(ov08d10->priv_lane->link_freq_menu);
932 ov08d10->link_freq =
933 v4l2_ctrl_new_int_menu(ctrl_hdlr, &ov08d10_ctrl_ops,
934 V4L2_CID_LINK_FREQ,
935 link_freq_size - 1,
936 0,
937 ov08d10->priv_lane->link_freq_menu);
938 if (ov08d10->link_freq)
939 ov08d10->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
940
941 pixel_rate_max = to_rate(ov08d10->priv_lane->link_freq_menu, 0,
942 ov08d10->cur_mode->data_lanes);
943 ov08d10->pixel_rate =
944 v4l2_ctrl_new_std(ctrl_hdlr, &ov08d10_ctrl_ops,
945 V4L2_CID_PIXEL_RATE, 0, pixel_rate_max, 1,
946 pixel_rate_max);
947
948 mode = ov08d10->cur_mode;
949 vblank_def = mode->vts_def - mode->height;
950 vblank_min = mode->vts_min - mode->height;
951 ov08d10->vblank =
952 v4l2_ctrl_new_std(ctrl_hdlr, &ov08d10_ctrl_ops,
953 V4L2_CID_VBLANK, vblank_min,
954 OV08D10_VTS_MAX - mode->height, 1,
955 vblank_def);
956
957 h_blank = to_pixels_per_line(ov08d10->priv_lane->link_freq_menu,
958 mode->hts, mode->link_freq_index,
959 mode->data_lanes) -
960 mode->width;
961 ov08d10->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov08d10_ctrl_ops,
962 V4L2_CID_HBLANK, h_blank, h_blank,
963 1, h_blank);
964 if (ov08d10->hblank)
965 ov08d10->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
966
967 v4l2_ctrl_new_std(ctrl_hdlr, &ov08d10_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
968 OV08D10_ANAL_GAIN_MIN, OV08D10_ANAL_GAIN_MAX,
969 OV08D10_ANAL_GAIN_STEP, OV08D10_ANAL_GAIN_MIN);
970
971 v4l2_ctrl_new_std(ctrl_hdlr, &ov08d10_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
972 OV08D10_DGTL_GAIN_MIN, OV08D10_DGTL_GAIN_MAX,
973 OV08D10_DGTL_GAIN_STEP, OV08D10_DGTL_GAIN_DEFAULT);
974
975 exposure_max = mode->vts_def - OV08D10_EXPOSURE_MAX_MARGIN;
976 ov08d10->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov08d10_ctrl_ops,
977 V4L2_CID_EXPOSURE,
978 OV08D10_EXPOSURE_MIN,
979 exposure_max,
980 OV08D10_EXPOSURE_STEP,
981 exposure_max);
982
983 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov08d10_ctrl_ops,
984 V4L2_CID_TEST_PATTERN,
985 ARRAY_SIZE(ov08d10_test_pattern_menu) - 1,
986 0, 0, ov08d10_test_pattern_menu);
987
988 ov08d10->hflip = v4l2_ctrl_new_std(ctrl_hdlr, &ov08d10_ctrl_ops,
989 V4L2_CID_HFLIP, 0, 1, 1, 0);
990 if (ov08d10->hflip)
991 ov08d10->hflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;
992 ov08d10->vflip = v4l2_ctrl_new_std(ctrl_hdlr, &ov08d10_ctrl_ops,
993 V4L2_CID_VFLIP, 0, 1, 1, 0);
994 if (ov08d10->vflip)
995 ov08d10->vflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;
996
997 if (ctrl_hdlr->error)
998 return ctrl_hdlr->error;
999
1000 ov08d10->sd.ctrl_handler = ctrl_hdlr;
1001
1002 return 0;
1003 }
1004
ov08d10_update_pad_format(struct ov08d10 * ov08d10,const struct ov08d10_mode * mode,struct v4l2_mbus_framefmt * fmt)1005 static void ov08d10_update_pad_format(struct ov08d10 *ov08d10,
1006 const struct ov08d10_mode *mode,
1007 struct v4l2_mbus_framefmt *fmt)
1008 {
1009 fmt->width = mode->width;
1010 fmt->height = mode->height;
1011 fmt->code = ov08d10_get_format_code(ov08d10);
1012 fmt->field = V4L2_FIELD_NONE;
1013 }
1014
ov08d10_start_streaming(struct ov08d10 * ov08d10)1015 static int ov08d10_start_streaming(struct ov08d10 *ov08d10)
1016 {
1017 struct i2c_client *client = v4l2_get_subdevdata(&ov08d10->sd);
1018 const struct ov08d10_reg_list *reg_list;
1019 int link_freq_index, ret;
1020
1021 link_freq_index = ov08d10->cur_mode->link_freq_index;
1022 reg_list =
1023 &ov08d10->priv_lane->link_freq_configs[link_freq_index].reg_list;
1024
1025 /* soft reset */
1026 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_PAGE, 0x00);
1027 if (ret < 0) {
1028 dev_err(ov08d10->dev, "failed to reset sensor");
1029 return ret;
1030 }
1031 ret = i2c_smbus_write_byte_data(client, 0x20, 0x0e);
1032 if (ret < 0) {
1033 dev_err(ov08d10->dev, "failed to reset sensor");
1034 return ret;
1035 }
1036 usleep_range(3000, 4000);
1037 ret = i2c_smbus_write_byte_data(client, 0x20, 0x0b);
1038 if (ret < 0) {
1039 dev_err(ov08d10->dev, "failed to reset sensor");
1040 return ret;
1041 }
1042
1043 /* update sensor setting */
1044 ret = ov08d10_write_reg_list(ov08d10, reg_list);
1045 if (ret) {
1046 dev_err(ov08d10->dev, "failed to set plls");
1047 return ret;
1048 }
1049
1050 reg_list = &ov08d10->cur_mode->reg_list;
1051 ret = ov08d10_write_reg_list(ov08d10, reg_list);
1052 if (ret) {
1053 dev_err(ov08d10->dev, "failed to set mode");
1054 return ret;
1055 }
1056
1057 ret = __v4l2_ctrl_handler_setup(ov08d10->sd.ctrl_handler);
1058 if (ret)
1059 return ret;
1060
1061 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_PAGE, 0x00);
1062 if (ret < 0)
1063 return ret;
1064
1065 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_MODE_SELECT,
1066 OV08D10_MODE_STREAMING);
1067 if (ret < 0)
1068 return ret;
1069
1070 return i2c_smbus_write_byte_data(client, OV08D10_REG_PAGE, 0x01);
1071 }
1072
ov08d10_stop_streaming(struct ov08d10 * ov08d10)1073 static void ov08d10_stop_streaming(struct ov08d10 *ov08d10)
1074 {
1075 struct i2c_client *client = v4l2_get_subdevdata(&ov08d10->sd);
1076 int ret;
1077
1078 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_PAGE, 0x00);
1079 if (ret < 0) {
1080 dev_err(ov08d10->dev, "failed to stop streaming");
1081 return;
1082 }
1083 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_MODE_SELECT,
1084 OV08D10_MODE_STANDBY);
1085 if (ret < 0) {
1086 dev_err(ov08d10->dev, "failed to stop streaming");
1087 return;
1088 }
1089
1090 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_PAGE, 0x01);
1091 if (ret < 0) {
1092 dev_err(ov08d10->dev, "failed to stop streaming");
1093 return;
1094 }
1095 }
1096
ov08d10_set_stream(struct v4l2_subdev * sd,int enable)1097 static int ov08d10_set_stream(struct v4l2_subdev *sd, int enable)
1098 {
1099 struct ov08d10 *ov08d10 = to_ov08d10(sd);
1100 int ret = 0;
1101
1102 mutex_lock(&ov08d10->mutex);
1103 if (enable) {
1104 ret = pm_runtime_resume_and_get(ov08d10->dev);
1105 if (ret < 0) {
1106 mutex_unlock(&ov08d10->mutex);
1107 return ret;
1108 }
1109
1110 ret = ov08d10_start_streaming(ov08d10);
1111 if (ret) {
1112 enable = 0;
1113 ov08d10_stop_streaming(ov08d10);
1114 pm_runtime_put(ov08d10->dev);
1115 }
1116 } else {
1117 ov08d10_stop_streaming(ov08d10);
1118 pm_runtime_put(ov08d10->dev);
1119 }
1120
1121 /* vflip and hflip cannot change during streaming */
1122 __v4l2_ctrl_grab(ov08d10->vflip, enable);
1123 __v4l2_ctrl_grab(ov08d10->hflip, enable);
1124
1125 mutex_unlock(&ov08d10->mutex);
1126
1127 return ret;
1128 }
1129
ov08d10_set_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)1130 static int ov08d10_set_format(struct v4l2_subdev *sd,
1131 struct v4l2_subdev_state *sd_state,
1132 struct v4l2_subdev_format *fmt)
1133 {
1134 struct ov08d10 *ov08d10 = to_ov08d10(sd);
1135 const struct ov08d10_mode *mode;
1136 s32 vblank_def, h_blank;
1137 s64 pixel_rate;
1138
1139 mode = v4l2_find_nearest_size(ov08d10->priv_lane->sp_modes,
1140 ov08d10->modes_size,
1141 width, height, fmt->format.width,
1142 fmt->format.height);
1143
1144 mutex_lock(&ov08d10->mutex);
1145 ov08d10_update_pad_format(ov08d10, mode, &fmt->format);
1146 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1147 *v4l2_subdev_state_get_format(sd_state, fmt->pad) =
1148 fmt->format;
1149 } else {
1150 ov08d10->cur_mode = mode;
1151 __v4l2_ctrl_s_ctrl(ov08d10->link_freq, mode->link_freq_index);
1152 pixel_rate = to_rate(ov08d10->priv_lane->link_freq_menu,
1153 mode->link_freq_index,
1154 ov08d10->cur_mode->data_lanes);
1155 __v4l2_ctrl_s_ctrl_int64(ov08d10->pixel_rate, pixel_rate);
1156
1157 /* Update limits and set FPS to default */
1158 vblank_def = mode->vts_def - mode->height;
1159 __v4l2_ctrl_modify_range(ov08d10->vblank,
1160 mode->vts_min - mode->height,
1161 OV08D10_VTS_MAX - mode->height, 1,
1162 vblank_def);
1163 __v4l2_ctrl_s_ctrl(ov08d10->vblank, vblank_def);
1164 h_blank = to_pixels_per_line(ov08d10->priv_lane->link_freq_menu,
1165 mode->hts,
1166 mode->link_freq_index,
1167 ov08d10->cur_mode->data_lanes)
1168 - mode->width;
1169 __v4l2_ctrl_modify_range(ov08d10->hblank, h_blank, h_blank, 1,
1170 h_blank);
1171 }
1172
1173 mutex_unlock(&ov08d10->mutex);
1174
1175 return 0;
1176 }
1177
ov08d10_get_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)1178 static int ov08d10_get_format(struct v4l2_subdev *sd,
1179 struct v4l2_subdev_state *sd_state,
1180 struct v4l2_subdev_format *fmt)
1181 {
1182 struct ov08d10 *ov08d10 = to_ov08d10(sd);
1183
1184 mutex_lock(&ov08d10->mutex);
1185 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
1186 fmt->format = *v4l2_subdev_state_get_format(sd_state,
1187 fmt->pad);
1188 else
1189 ov08d10_update_pad_format(ov08d10, ov08d10->cur_mode,
1190 &fmt->format);
1191
1192 mutex_unlock(&ov08d10->mutex);
1193
1194 return 0;
1195 }
1196
ov08d10_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)1197 static int ov08d10_enum_mbus_code(struct v4l2_subdev *sd,
1198 struct v4l2_subdev_state *sd_state,
1199 struct v4l2_subdev_mbus_code_enum *code)
1200 {
1201 struct ov08d10 *ov08d10 = to_ov08d10(sd);
1202
1203 if (code->index > 0)
1204 return -EINVAL;
1205
1206 mutex_lock(&ov08d10->mutex);
1207 code->code = ov08d10_get_format_code(ov08d10);
1208 mutex_unlock(&ov08d10->mutex);
1209
1210 return 0;
1211 }
1212
ov08d10_enum_frame_size(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_size_enum * fse)1213 static int ov08d10_enum_frame_size(struct v4l2_subdev *sd,
1214 struct v4l2_subdev_state *sd_state,
1215 struct v4l2_subdev_frame_size_enum *fse)
1216 {
1217 struct ov08d10 *ov08d10 = to_ov08d10(sd);
1218
1219 if (fse->index >= ov08d10->modes_size)
1220 return -EINVAL;
1221
1222 mutex_lock(&ov08d10->mutex);
1223 if (fse->code != ov08d10_get_format_code(ov08d10)) {
1224 mutex_unlock(&ov08d10->mutex);
1225 return -EINVAL;
1226 }
1227 mutex_unlock(&ov08d10->mutex);
1228
1229 fse->min_width = ov08d10->priv_lane->sp_modes[fse->index].width;
1230 fse->max_width = fse->min_width;
1231 fse->min_height = ov08d10->priv_lane->sp_modes[fse->index].height;
1232 fse->max_height = fse->min_height;
1233
1234 return 0;
1235 }
1236
ov08d10_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1237 static int ov08d10_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1238 {
1239 struct ov08d10 *ov08d10 = to_ov08d10(sd);
1240
1241 mutex_lock(&ov08d10->mutex);
1242 ov08d10_update_pad_format(ov08d10, &ov08d10->priv_lane->sp_modes[0],
1243 v4l2_subdev_state_get_format(fh->state, 0));
1244 mutex_unlock(&ov08d10->mutex);
1245
1246 return 0;
1247 }
1248
1249 static const struct v4l2_subdev_video_ops ov08d10_video_ops = {
1250 .s_stream = ov08d10_set_stream,
1251 };
1252
1253 static const struct v4l2_subdev_pad_ops ov08d10_pad_ops = {
1254 .set_fmt = ov08d10_set_format,
1255 .get_fmt = ov08d10_get_format,
1256 .enum_mbus_code = ov08d10_enum_mbus_code,
1257 .enum_frame_size = ov08d10_enum_frame_size,
1258 };
1259
1260 static const struct v4l2_subdev_ops ov08d10_subdev_ops = {
1261 .video = &ov08d10_video_ops,
1262 .pad = &ov08d10_pad_ops,
1263 };
1264
1265 static const struct v4l2_subdev_internal_ops ov08d10_internal_ops = {
1266 .open = ov08d10_open,
1267 };
1268
ov08d10_identify_module(struct ov08d10 * ov08d10)1269 static int ov08d10_identify_module(struct ov08d10 *ov08d10)
1270 {
1271 struct i2c_client *client = v4l2_get_subdevdata(&ov08d10->sd);
1272 u32 val;
1273 u16 chip_id;
1274 int ret;
1275
1276 /* System control registers */
1277 ret = i2c_smbus_write_byte_data(client, OV08D10_REG_PAGE, 0x00);
1278 if (ret < 0)
1279 return ret;
1280
1281 /* Validate the chip ID */
1282 ret = i2c_smbus_read_byte_data(client, OV08D10_REG_CHIP_ID_0);
1283 if (ret < 0)
1284 return ret;
1285
1286 val = ret << 8;
1287
1288 ret = i2c_smbus_read_byte_data(client, OV08D10_REG_CHIP_ID_1);
1289 if (ret < 0)
1290 return ret;
1291
1292 chip_id = val | ret;
1293
1294 if ((chip_id & OV08D10_ID_MASK) != OV08D10_CHIP_ID) {
1295 dev_err(ov08d10->dev, "unexpected sensor id(0x%04x)\n",
1296 chip_id);
1297 return -EINVAL;
1298 }
1299
1300 return 0;
1301 }
1302
ov08d10_get_hwcfg(struct ov08d10 * ov08d10)1303 static int ov08d10_get_hwcfg(struct ov08d10 *ov08d10)
1304 {
1305 struct device *dev = ov08d10->dev;
1306 struct fwnode_handle *ep;
1307 struct fwnode_handle *fwnode = dev_fwnode(dev);
1308 struct v4l2_fwnode_endpoint bus_cfg = {
1309 .bus_type = V4L2_MBUS_CSI2_DPHY
1310 };
1311 unsigned int i, j;
1312 int ret;
1313
1314 if (!fwnode)
1315 return -ENXIO;
1316
1317 ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
1318 if (!ep)
1319 return -ENXIO;
1320
1321 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
1322 fwnode_handle_put(ep);
1323 if (ret)
1324 return ret;
1325
1326 /* Get number of data lanes */
1327 if (bus_cfg.bus.mipi_csi2.num_data_lanes != 2) {
1328 dev_err(dev, "number of CSI2 data lanes %d is not supported",
1329 bus_cfg.bus.mipi_csi2.num_data_lanes);
1330 ret = -EINVAL;
1331 goto check_hwcfg_error;
1332 }
1333
1334 dev_dbg(dev, "Using %u data lanes\n", ov08d10->cur_mode->data_lanes);
1335
1336 ov08d10->priv_lane = &lane_cfg_2;
1337 ov08d10->modes_size = ov08d10_modes_num(ov08d10);
1338
1339 if (!bus_cfg.nr_of_link_frequencies) {
1340 dev_err(dev, "no link frequencies defined");
1341 ret = -EINVAL;
1342 goto check_hwcfg_error;
1343 }
1344
1345 for (i = 0; i < ARRAY_SIZE(ov08d10->priv_lane->link_freq_menu); i++) {
1346 for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) {
1347 if (ov08d10->priv_lane->link_freq_menu[i] ==
1348 bus_cfg.link_frequencies[j])
1349 break;
1350 }
1351
1352 if (j == bus_cfg.nr_of_link_frequencies) {
1353 dev_err(dev, "no link frequency %lld supported",
1354 ov08d10->priv_lane->link_freq_menu[i]);
1355 ret = -EINVAL;
1356 goto check_hwcfg_error;
1357 }
1358 }
1359
1360 check_hwcfg_error:
1361 v4l2_fwnode_endpoint_free(&bus_cfg);
1362
1363 return ret;
1364 }
1365
ov08d10_remove(struct i2c_client * client)1366 static void ov08d10_remove(struct i2c_client *client)
1367 {
1368 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1369 struct ov08d10 *ov08d10 = to_ov08d10(sd);
1370
1371 v4l2_async_unregister_subdev(sd);
1372 media_entity_cleanup(&sd->entity);
1373 v4l2_ctrl_handler_free(sd->ctrl_handler);
1374 pm_runtime_disable(ov08d10->dev);
1375 mutex_destroy(&ov08d10->mutex);
1376 }
1377
ov08d10_probe(struct i2c_client * client)1378 static int ov08d10_probe(struct i2c_client *client)
1379 {
1380 struct ov08d10 *ov08d10;
1381 unsigned long freq;
1382 int ret;
1383
1384 ov08d10 = devm_kzalloc(&client->dev, sizeof(*ov08d10), GFP_KERNEL);
1385 if (!ov08d10)
1386 return -ENOMEM;
1387
1388 ov08d10->dev = &client->dev;
1389
1390 ov08d10->clk = devm_v4l2_sensor_clk_get(ov08d10->dev, NULL);
1391 if (IS_ERR(ov08d10->clk))
1392 return dev_err_probe(ov08d10->dev, PTR_ERR(ov08d10->clk),
1393 "failed to get clock\n");
1394
1395 freq = clk_get_rate(ov08d10->clk);
1396 if (freq != OV08D10_XVCLK_19_2)
1397 dev_warn(ov08d10->dev,
1398 "external clock rate %lu is not supported\n", freq);
1399
1400 ret = ov08d10_get_hwcfg(ov08d10);
1401 if (ret) {
1402 dev_err(ov08d10->dev, "failed to get HW configuration: %d",
1403 ret);
1404 return ret;
1405 }
1406
1407 v4l2_i2c_subdev_init(&ov08d10->sd, client, &ov08d10_subdev_ops);
1408
1409 ret = ov08d10_identify_module(ov08d10);
1410 if (ret) {
1411 dev_err(ov08d10->dev, "failed to find sensor: %d", ret);
1412 return ret;
1413 }
1414
1415 mutex_init(&ov08d10->mutex);
1416 ov08d10->cur_mode = &ov08d10->priv_lane->sp_modes[0];
1417 ret = ov08d10_init_controls(ov08d10);
1418 if (ret) {
1419 dev_err(ov08d10->dev, "failed to init controls: %d", ret);
1420 goto probe_error_v4l2_ctrl_handler_free;
1421 }
1422
1423 ov08d10->sd.internal_ops = &ov08d10_internal_ops;
1424 ov08d10->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1425 ov08d10->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1426 ov08d10->pad.flags = MEDIA_PAD_FL_SOURCE;
1427 ret = media_entity_pads_init(&ov08d10->sd.entity, 1, &ov08d10->pad);
1428 if (ret) {
1429 dev_err(ov08d10->dev, "failed to init entity pads: %d", ret);
1430 goto probe_error_v4l2_ctrl_handler_free;
1431 }
1432
1433 ret = v4l2_async_register_subdev_sensor(&ov08d10->sd);
1434 if (ret < 0) {
1435 dev_err(ov08d10->dev, "failed to register V4L2 subdev: %d",
1436 ret);
1437 goto probe_error_media_entity_cleanup;
1438 }
1439
1440 /*
1441 * Device is already turned on by i2c-core with ACPI domain PM.
1442 * Enable runtime PM and turn off the device.
1443 */
1444 pm_runtime_set_active(ov08d10->dev);
1445 pm_runtime_enable(ov08d10->dev);
1446 pm_runtime_idle(ov08d10->dev);
1447
1448 return 0;
1449
1450 probe_error_media_entity_cleanup:
1451 media_entity_cleanup(&ov08d10->sd.entity);
1452
1453 probe_error_v4l2_ctrl_handler_free:
1454 v4l2_ctrl_handler_free(ov08d10->sd.ctrl_handler);
1455 mutex_destroy(&ov08d10->mutex);
1456
1457 return ret;
1458 }
1459
1460 #ifdef CONFIG_ACPI
1461 static const struct acpi_device_id ov08d10_acpi_ids[] = {
1462 { "OVTI08D1" },
1463 { /* sentinel */ }
1464 };
1465
1466 MODULE_DEVICE_TABLE(acpi, ov08d10_acpi_ids);
1467 #endif
1468
1469 static struct i2c_driver ov08d10_i2c_driver = {
1470 .driver = {
1471 .name = "ov08d10",
1472 .acpi_match_table = ACPI_PTR(ov08d10_acpi_ids),
1473 },
1474 .probe = ov08d10_probe,
1475 .remove = ov08d10_remove,
1476 };
1477
1478 module_i2c_driver(ov08d10_i2c_driver);
1479
1480 MODULE_AUTHOR("Su, Jimmy <jimmy.su@intel.com>");
1481 MODULE_DESCRIPTION("OmniVision ov08d10 sensor driver");
1482 MODULE_LICENSE("GPL v2");
1483