1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2023 Intel Corporation.
3
4 #include <linux/acpi.h>
5 #include <linux/clk.h>
6 #include <linux/delay.h>
7 #include <linux/gpio/consumer.h>
8 #include <linux/i2c.h>
9 #include <linux/module.h>
10 #include <linux/pm_runtime.h>
11 #include <linux/regmap.h>
12 #include <media/v4l2-cci.h>
13 #include <media/v4l2-ctrls.h>
14 #include <media/v4l2-device.h>
15 #include <media/v4l2-fwnode.h>
16
17 #define OV02E10_LINK_FREQ_360MHZ 360000000ULL
18 #define OV02E10_SCLK 36000000LL
19 #define OV02E10_MCLK 19200000
20 #define OV02E10_DATA_LANES 2
21 #define OV02E10_RGB_DEPTH 10
22
23 #define OV02E10_REG_PAGE_FLAG CCI_REG8(0xfd)
24 #define OV02E10_PAGE_0 0x0
25 #define OV02E10_PAGE_1 0x1
26 #define OV02E10_PAGE_2 0x2
27 #define OV02E10_PAGE_3 0x3
28 #define OV02E10_PAGE_5 0x4
29 #define OV02E10_PAGE_7 0x5
30 #define OV02E10_PAGE_8 0x6
31 #define OV02E10_PAGE_9 0xF
32 #define OV02E10_PAGE_D 0x8
33 #define OV02E10_PAGE_E 0x9
34 #define OV02E10_PAGE_F 0xA
35
36 #define OV02E10_REG_CHIP_ID CCI_REG32(0x00)
37 #define OV02E10_CHIP_ID 0x45025610
38
39 /* Horizontal and vertical flip */
40 #define OV02E10_REG_ORIENTATION CCI_REG8(0x32)
41
42 /* vertical-timings from sensor */
43 #define OV02E10_REG_VTS CCI_REG16(0x35)
44 #define OV02E10_VTS_DEF 2244
45 #define OV02E10_VTS_MIN 2244
46 #define OV02E10_VTS_MAX 0x7fff
47
48 /* horizontal-timings from sensor */
49 #define OV02E10_REG_HTS CCI_REG16(0x37)
50
51 /* Exposure controls from sensor */
52 #define OV02E10_REG_EXPOSURE CCI_REG16(0x03)
53 #define OV02E10_EXPOSURE_MIN 1
54 #define OV02E10_EXPOSURE_MAX_MARGIN 2
55 #define OV02E10_EXPOSURE_STEP 1
56
57 /* Analog gain controls from sensor */
58 #define OV02E10_REG_ANALOG_GAIN CCI_REG8(0x24)
59 #define OV02E10_ANAL_GAIN_MIN 0x10
60 #define OV02E10_ANAL_GAIN_MAX 0xf8
61 #define OV02E10_ANAL_GAIN_STEP 1
62
63 /* Digital gain controls from sensor */
64 #define OV02E10_REG_DIGITAL_GAIN CCI_REG16(0x21)
65 #define OV02E10_DGTL_GAIN_MIN 256
66 #define OV02E10_DGTL_GAIN_MAX 1020
67 #define OV02E10_DGTL_GAIN_STEP 1
68 #define OV02E10_DGTL_GAIN_DEFAULT 256
69
70 /* Register update control */
71 #define OV02E10_REG_COMMAND_UPDATE CCI_REG8(0xE7)
72 #define OV02E10_COMMAND_UPDATE 0x00
73 #define OV02E10_COMMAND_HOLD 0x01
74
75 /* Test Pattern Control */
76 #define OV02E10_REG_TEST_PATTERN CCI_REG8(0x12)
77 #define OV02E10_TEST_PATTERN_ENABLE BIT(0)
78 #define OV02E10_TEST_PATTERN_BAR_SHIFT 1
79
80 struct reg_sequence_list {
81 u32 num_regs;
82 const struct reg_sequence *regs;
83 };
84
85 struct ov02e10_mode {
86 /* Frame width in pixels */
87 u32 width;
88
89 /* Frame height in pixels */
90 u32 height;
91
92 /* Horizontal timining size */
93 u32 hts;
94
95 /* Default vertical timing */
96 u32 vts_def;
97
98 /* Min vertical timining size */
99 u32 vts_min;
100
101 /* Sensor register settings for this resolution */
102 const struct reg_sequence_list reg_list;
103 };
104
105 static const struct reg_sequence mode_1928x1088_30fps_2lane[] = {
106 { 0xfd, 0x00 },
107 { 0x20, 0x00 },
108 { 0x20, 0x0b },
109 { 0x21, 0x02 },
110 { 0x10, 0x23 },
111 { 0xc5, 0x04 },
112 { 0x21, 0x00 },
113 { 0x14, 0x96 },
114 { 0x17, 0x01 },
115 { 0xfd, 0x01 },
116 { 0x03, 0x00 },
117 { 0x04, 0x04 },
118 { 0x05, 0x04 },
119 { 0x06, 0x62 },
120 { 0x07, 0x01 },
121 { 0x22, 0x80 },
122 { 0x24, 0xff },
123 { 0x40, 0xc6 },
124 { 0x41, 0x18 },
125 { 0x45, 0x3f },
126 { 0x48, 0x0c },
127 { 0x4c, 0x08 },
128 { 0x51, 0x12 },
129 { 0x52, 0x10 },
130 { 0x57, 0x98 },
131 { 0x59, 0x06 },
132 { 0x5a, 0x04 },
133 { 0x5c, 0x38 },
134 { 0x5e, 0x10 },
135 { 0x67, 0x11 },
136 { 0x7b, 0x04 },
137 { 0x81, 0x12 },
138 { 0x90, 0x51 },
139 { 0x91, 0x09 },
140 { 0x92, 0x21 },
141 { 0x93, 0x28 },
142 { 0x95, 0x54 },
143 { 0x9d, 0x20 },
144 { 0x9e, 0x04 },
145 { 0xb1, 0x9a },
146 { 0xb2, 0x86 },
147 { 0xb6, 0x3f },
148 { 0xb9, 0x30 },
149 { 0xc1, 0x01 },
150 { 0xc5, 0xa0 },
151 { 0xc6, 0x73 },
152 { 0xc7, 0x04 },
153 { 0xc8, 0x25 },
154 { 0xc9, 0x05 },
155 { 0xca, 0x28 },
156 { 0xcb, 0x00 },
157 { 0xcf, 0x16 },
158 { 0xd2, 0xd0 },
159 { 0xd7, 0x3f },
160 { 0xd8, 0x40 },
161 { 0xd9, 0x40 },
162 { 0xda, 0x44 },
163 { 0xdb, 0x3d },
164 { 0xdc, 0x3d },
165 { 0xdd, 0x3d },
166 { 0xde, 0x3d },
167 { 0xdf, 0xf0 },
168 { 0xea, 0x0f },
169 { 0xeb, 0x04 },
170 { 0xec, 0x29 },
171 { 0xee, 0x47 },
172 { 0xfd, 0x01 },
173 { 0x31, 0x01 },
174 { 0x27, 0x00 },
175 { 0x2f, 0x41 },
176 { 0xfd, 0x02 },
177 { 0xa1, 0x01 },
178 { 0xfd, 0x02 },
179 { 0x9a, 0x03 },
180 { 0xfd, 0x03 },
181 { 0x9d, 0x0f },
182 { 0xfd, 0x07 },
183 { 0x42, 0x00 },
184 { 0x43, 0xad },
185 { 0x44, 0x00 },
186 { 0x45, 0xa8 },
187 { 0x46, 0x00 },
188 { 0x47, 0xa8 },
189 { 0x48, 0x00 },
190 { 0x49, 0xad },
191 { 0xfd, 0x00 },
192 { 0xc4, 0x01 },
193 { 0xfd, 0x01 },
194 { 0x33, 0x03 },
195 { 0xfd, 0x00 },
196 { 0x20, 0x1f },
197 };
198
199 static const char *const ov02e10_test_pattern_menu[] = {
200 "Disabled",
201 "Color Bar",
202 };
203
204 static const s64 link_freq_menu_items[] = {
205 OV02E10_LINK_FREQ_360MHZ,
206 };
207
208 static const struct ov02e10_mode supported_modes[] = {
209 {
210 .width = 1928,
211 .height = 1088,
212 .hts = 534,
213 .vts_def = 2244,
214 .vts_min = 2244,
215 .reg_list = {
216 .num_regs = ARRAY_SIZE(mode_1928x1088_30fps_2lane),
217 .regs = mode_1928x1088_30fps_2lane,
218 },
219 },
220 };
221
222 static const char * const ov02e10_supply_names[] = {
223 "dovdd", /* Digital I/O power */
224 "avdd", /* Analog power */
225 "dvdd", /* Digital core power */
226 };
227
228 struct ov02e10 {
229 struct device *dev;
230
231 struct regmap *regmap;
232 struct v4l2_subdev sd;
233 struct media_pad pad;
234 struct v4l2_ctrl_handler ctrl_handler;
235
236 /* V4L2 Controls */
237 struct v4l2_ctrl *link_freq;
238 struct v4l2_ctrl *pixel_rate;
239 struct v4l2_ctrl *vblank;
240 struct v4l2_ctrl *hblank;
241 struct v4l2_ctrl *exposure;
242 struct v4l2_ctrl *vflip;
243 struct v4l2_ctrl *hflip;
244
245 struct clk *img_clk;
246 struct regulator_bulk_data supplies[ARRAY_SIZE(ov02e10_supply_names)];
247 struct gpio_desc *reset;
248
249 /* Current mode */
250 const struct ov02e10_mode *cur_mode;
251
252 /* MIPI lanes info */
253 u32 link_freq_index;
254 u8 mipi_lanes;
255 };
256
to_ov02e10(struct v4l2_subdev * subdev)257 static inline struct ov02e10 *to_ov02e10(struct v4l2_subdev *subdev)
258 {
259 return container_of(subdev, struct ov02e10, sd);
260 }
261
to_pixel_rate(u32 f_index)262 static u64 to_pixel_rate(u32 f_index)
263 {
264 u64 pixel_rate = link_freq_menu_items[f_index] * 2 * OV02E10_DATA_LANES;
265
266 do_div(pixel_rate, OV02E10_RGB_DEPTH);
267
268 return pixel_rate;
269 }
270
to_pixels_per_line(u32 hts,u32 f_index)271 static u64 to_pixels_per_line(u32 hts, u32 f_index)
272 {
273 u64 ppl = hts * to_pixel_rate(f_index);
274
275 do_div(ppl, OV02E10_SCLK);
276
277 return ppl;
278 }
279
ov02e10_test_pattern(struct ov02e10 * ov02e10,u32 pattern,int * pret)280 static void ov02e10_test_pattern(struct ov02e10 *ov02e10, u32 pattern, int *pret)
281 {
282 if (pattern)
283 pattern = pattern << OV02E10_TEST_PATTERN_BAR_SHIFT |
284 OV02E10_TEST_PATTERN_ENABLE;
285
286 cci_write(ov02e10->regmap, OV02E10_REG_TEST_PATTERN, pattern, pret);
287 }
288
ov02e10_set_ctrl(struct v4l2_ctrl * ctrl)289 static int ov02e10_set_ctrl(struct v4l2_ctrl *ctrl)
290 {
291 struct ov02e10 *ov02e10 = container_of(ctrl->handler,
292 struct ov02e10, ctrl_handler);
293 s64 exposure_max;
294 int ret;
295
296 /* Propagate change of current control to all related controls */
297 if (ctrl->id == V4L2_CID_VBLANK) {
298 /* Update max exposure while meeting expected vblanking */
299 exposure_max = ov02e10->cur_mode->height + ctrl->val -
300 OV02E10_EXPOSURE_MAX_MARGIN;
301 ret = __v4l2_ctrl_modify_range(ov02e10->exposure,
302 ov02e10->exposure->minimum,
303 exposure_max,
304 ov02e10->exposure->step,
305 exposure_max);
306 if (ret)
307 return ret;
308 }
309
310 /* V4L2 controls values will be applied only when power is already up */
311 if (!pm_runtime_get_if_in_use(ov02e10->dev))
312 return 0;
313
314 ret = cci_write(ov02e10->regmap, OV02E10_REG_COMMAND_UPDATE,
315 OV02E10_COMMAND_HOLD, NULL);
316
317 switch (ctrl->id) {
318 case V4L2_CID_ANALOGUE_GAIN:
319 cci_write(ov02e10->regmap, OV02E10_REG_PAGE_FLAG,
320 OV02E10_PAGE_1, &ret);
321 cci_write(ov02e10->regmap, OV02E10_REG_ANALOG_GAIN,
322 ctrl->val, &ret);
323 break;
324
325 case V4L2_CID_DIGITAL_GAIN:
326 cci_write(ov02e10->regmap, OV02E10_REG_PAGE_FLAG,
327 OV02E10_PAGE_1, &ret);
328 cci_write(ov02e10->regmap, OV02E10_REG_DIGITAL_GAIN,
329 ctrl->val, &ret);
330 break;
331
332 case V4L2_CID_EXPOSURE:
333 cci_write(ov02e10->regmap, OV02E10_REG_PAGE_FLAG,
334 OV02E10_PAGE_1, &ret);
335 cci_write(ov02e10->regmap, OV02E10_REG_EXPOSURE,
336 ctrl->val, &ret);
337 break;
338
339 case V4L2_CID_HFLIP:
340 case V4L2_CID_VFLIP:
341 cci_write(ov02e10->regmap, OV02E10_REG_PAGE_FLAG,
342 OV02E10_PAGE_1, &ret);
343 cci_write(ov02e10->regmap, OV02E10_REG_ORIENTATION,
344 ov02e10->hflip->val | ov02e10->vflip->val << 1, &ret);
345 break;
346 case V4L2_CID_VBLANK:
347 cci_write(ov02e10->regmap, OV02E10_REG_PAGE_FLAG,
348 OV02E10_PAGE_1, &ret);
349 cci_write(ov02e10->regmap, OV02E10_REG_VTS,
350 ov02e10->cur_mode->height + ctrl->val, &ret);
351 break;
352
353 case V4L2_CID_TEST_PATTERN:
354 cci_write(ov02e10->regmap, OV02E10_REG_PAGE_FLAG,
355 OV02E10_PAGE_1, &ret);
356 ov02e10_test_pattern(ov02e10, ctrl->val, &ret);
357 break;
358
359 default:
360 ret = -EINVAL;
361 break;
362 }
363
364 cci_write(ov02e10->regmap, OV02E10_REG_COMMAND_UPDATE,
365 OV02E10_COMMAND_UPDATE, &ret);
366
367 pm_runtime_put(ov02e10->dev);
368
369 return ret;
370 }
371
372 static const struct v4l2_ctrl_ops ov02e10_ctrl_ops = {
373 .s_ctrl = ov02e10_set_ctrl,
374 };
375
ov02e10_init_controls(struct ov02e10 * ov02e10)376 static int ov02e10_init_controls(struct ov02e10 *ov02e10)
377 {
378 struct v4l2_ctrl_handler *ctrl_hdlr = &ov02e10->ctrl_handler;
379 const struct ov02e10_mode *mode = ov02e10->cur_mode;
380 u32 vblank_min, vblank_max, vblank_def;
381 struct v4l2_fwnode_device_properties props;
382 s64 exposure_max, h_blank, pixel_rate;
383 int ret;
384
385 v4l2_ctrl_handler_init(ctrl_hdlr, 12);
386
387 ov02e10->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr,
388 &ov02e10_ctrl_ops,
389 V4L2_CID_LINK_FREQ,
390 ov02e10->link_freq_index,
391 0, link_freq_menu_items);
392 if (ov02e10->link_freq)
393 ov02e10->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
394
395 pixel_rate = to_pixel_rate(ov02e10->link_freq_index);
396 ov02e10->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov02e10_ctrl_ops,
397 V4L2_CID_PIXEL_RATE, 0,
398 pixel_rate, 1, pixel_rate);
399
400 vblank_min = mode->vts_min - mode->height;
401 vblank_max = OV02E10_VTS_MAX - mode->height;
402 vblank_def = mode->vts_def - mode->height;
403 ov02e10->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov02e10_ctrl_ops,
404 V4L2_CID_VBLANK, vblank_min,
405 vblank_max, 1, vblank_def);
406
407 h_blank = mode->hts - mode->width;
408 ov02e10->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov02e10_ctrl_ops,
409 V4L2_CID_HBLANK, h_blank, h_blank,
410 1, h_blank);
411 if (ov02e10->hblank)
412 ov02e10->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
413
414 v4l2_ctrl_new_std(ctrl_hdlr, &ov02e10_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
415 OV02E10_ANAL_GAIN_MIN, OV02E10_ANAL_GAIN_MAX,
416 OV02E10_ANAL_GAIN_STEP, OV02E10_ANAL_GAIN_MIN);
417
418 v4l2_ctrl_new_std(ctrl_hdlr, &ov02e10_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
419 OV02E10_DGTL_GAIN_MIN, OV02E10_DGTL_GAIN_MAX,
420 OV02E10_DGTL_GAIN_STEP, OV02E10_DGTL_GAIN_DEFAULT);
421
422 exposure_max = mode->vts_def - OV02E10_EXPOSURE_MAX_MARGIN;
423 ov02e10->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov02e10_ctrl_ops,
424 V4L2_CID_EXPOSURE,
425 OV02E10_EXPOSURE_MIN,
426 exposure_max,
427 OV02E10_EXPOSURE_STEP,
428 exposure_max);
429
430 ov02e10->hflip = v4l2_ctrl_new_std(ctrl_hdlr, &ov02e10_ctrl_ops,
431 V4L2_CID_HFLIP, 0, 1, 1, 0);
432 if (ov02e10->hflip)
433 ov02e10->hflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;
434
435 ov02e10->vflip = v4l2_ctrl_new_std(ctrl_hdlr, &ov02e10_ctrl_ops,
436 V4L2_CID_VFLIP, 0, 1, 1, 0);
437 if (ov02e10->vflip)
438 ov02e10->vflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;
439
440 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov02e10_ctrl_ops,
441 V4L2_CID_TEST_PATTERN,
442 ARRAY_SIZE(ov02e10_test_pattern_menu) - 1,
443 0, 0, ov02e10_test_pattern_menu);
444
445 ret = v4l2_fwnode_device_parse(ov02e10->dev, &props);
446 if (ret)
447 return ret;
448
449 v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &ov02e10_ctrl_ops, &props);
450
451 if (ctrl_hdlr->error)
452 return ctrl_hdlr->error;
453
454 ov02e10->sd.ctrl_handler = ctrl_hdlr;
455
456 return 0;
457 }
458
ov02e10_update_pad_format(const struct ov02e10_mode * mode,struct v4l2_mbus_framefmt * fmt)459 static void ov02e10_update_pad_format(const struct ov02e10_mode *mode,
460 struct v4l2_mbus_framefmt *fmt)
461 {
462 fmt->width = mode->width;
463 fmt->height = mode->height;
464 fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
465 fmt->field = V4L2_FIELD_NONE;
466 }
467
ov02e10_set_stream_mode(struct ov02e10 * ov02e10,u8 val)468 static int ov02e10_set_stream_mode(struct ov02e10 *ov02e10, u8 val)
469 {
470 int ret = 0;
471
472 cci_write(ov02e10->regmap, OV02E10_REG_PAGE_FLAG, OV02E10_PAGE_0, &ret);
473 cci_write(ov02e10->regmap, CCI_REG8(0xa0), val, &ret);
474 cci_write(ov02e10->regmap, OV02E10_REG_PAGE_FLAG, OV02E10_PAGE_1, &ret);
475 cci_write(ov02e10->regmap, CCI_REG8(0x01), 0x02, &ret);
476
477 return ret;
478 }
479
ov02e10_enable_streams(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,u32 pad,u64 streams_mask)480 static int ov02e10_enable_streams(struct v4l2_subdev *sd,
481 struct v4l2_subdev_state *state,
482 u32 pad, u64 streams_mask)
483 {
484 struct ov02e10 *ov02e10 = to_ov02e10(sd);
485 const struct reg_sequence_list *reg_list;
486 int ret;
487
488 ret = pm_runtime_resume_and_get(ov02e10->dev);
489 if (ret)
490 return ret;
491
492 reg_list = &ov02e10->cur_mode->reg_list;
493 ret = regmap_multi_reg_write(ov02e10->regmap, reg_list->regs,
494 reg_list->num_regs);
495 if (ret) {
496 dev_err(ov02e10->dev, "failed to set mode\n");
497 goto out;
498 }
499
500 ret = __v4l2_ctrl_handler_setup(ov02e10->sd.ctrl_handler);
501 if (ret)
502 goto out;
503
504 ret = ov02e10_set_stream_mode(ov02e10, 1);
505
506 out:
507 if (ret)
508 pm_runtime_put(ov02e10->dev);
509
510 return ret;
511 }
512
ov02e10_disable_streams(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,u32 pad,u64 streams_mask)513 static int ov02e10_disable_streams(struct v4l2_subdev *sd,
514 struct v4l2_subdev_state *state,
515 u32 pad, u64 streams_mask)
516 {
517 struct ov02e10 *ov02e10 = to_ov02e10(sd);
518
519 ov02e10_set_stream_mode(ov02e10, 0);
520 pm_runtime_put(ov02e10->dev);
521
522 return 0;
523 }
524
ov02e10_get_pm_resources(struct device * dev)525 static int ov02e10_get_pm_resources(struct device *dev)
526 {
527 struct v4l2_subdev *sd = dev_get_drvdata(dev);
528 struct ov02e10 *ov02e10 = to_ov02e10(sd);
529 int i;
530
531 ov02e10->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
532 if (IS_ERR(ov02e10->reset))
533 return dev_err_probe(dev, PTR_ERR(ov02e10->reset),
534 "failed to get reset gpio\n");
535
536 for (i = 0; i < ARRAY_SIZE(ov02e10_supply_names); i++)
537 ov02e10->supplies[i].supply = ov02e10_supply_names[i];
538
539 return devm_regulator_bulk_get(dev, ARRAY_SIZE(ov02e10_supply_names),
540 ov02e10->supplies);
541 }
542
ov02e10_power_off(struct device * dev)543 static int ov02e10_power_off(struct device *dev)
544 {
545 struct v4l2_subdev *sd = dev_get_drvdata(dev);
546 struct ov02e10 *ov02e10 = to_ov02e10(sd);
547
548 if (ov02e10->reset)
549 gpiod_set_value_cansleep(ov02e10->reset, 1);
550
551 regulator_bulk_disable(ARRAY_SIZE(ov02e10_supply_names),
552 ov02e10->supplies);
553
554 clk_disable_unprepare(ov02e10->img_clk);
555
556 return 0;
557 }
558
ov02e10_power_on(struct device * dev)559 static int ov02e10_power_on(struct device *dev)
560 {
561 struct v4l2_subdev *sd = dev_get_drvdata(dev);
562 struct ov02e10 *ov02e10 = to_ov02e10(sd);
563 int ret;
564
565 ret = clk_prepare_enable(ov02e10->img_clk);
566 if (ret < 0) {
567 dev_err(dev, "failed to enable imaging clock: %d\n", ret);
568 return ret;
569 }
570
571 ret = regulator_bulk_enable(ARRAY_SIZE(ov02e10_supply_names),
572 ov02e10->supplies);
573 if (ret < 0) {
574 dev_err(dev, "failed to enable regulators\n");
575 goto disable_clk;
576 }
577
578 if (ov02e10->reset) {
579 usleep_range(5000, 5100);
580 gpiod_set_value_cansleep(ov02e10->reset, 0);
581 usleep_range(8000, 8100);
582 }
583
584 return 0;
585
586 disable_clk:
587 clk_disable_unprepare(ov02e10->img_clk);
588
589 return ret;
590 }
591
ov02e10_set_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)592 static int ov02e10_set_format(struct v4l2_subdev *sd,
593 struct v4l2_subdev_state *sd_state,
594 struct v4l2_subdev_format *fmt)
595 {
596 struct ov02e10 *ov02e10 = to_ov02e10(sd);
597 const struct ov02e10_mode *mode;
598 s32 vblank_def, h_blank;
599 int ret = 0;
600
601 mode = v4l2_find_nearest_size(supported_modes,
602 ARRAY_SIZE(supported_modes),
603 width, height, fmt->format.width,
604 fmt->format.height);
605
606 ov02e10_update_pad_format(mode, &fmt->format);
607
608 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
609 *v4l2_subdev_state_get_format(sd_state, fmt->pad) = fmt->format;
610 } else {
611 ov02e10->cur_mode = mode;
612 ret = __v4l2_ctrl_s_ctrl(ov02e10->link_freq,
613 ov02e10->link_freq_index);
614 if (ret)
615 return ret;
616
617 ret = __v4l2_ctrl_s_ctrl_int64(ov02e10->pixel_rate,
618 to_pixel_rate(ov02e10->link_freq_index));
619 if (ret)
620 return ret;
621
622 /* Update limits and set FPS to default */
623 vblank_def = mode->vts_def - mode->height;
624 ret = __v4l2_ctrl_modify_range(ov02e10->vblank,
625 mode->vts_min - mode->height,
626 OV02E10_VTS_MAX - mode->height,
627 1, vblank_def);
628 if (ret)
629 return ret;
630
631 ret = __v4l2_ctrl_s_ctrl(ov02e10->vblank, vblank_def);
632 if (ret)
633 return ret;
634
635 h_blank = to_pixels_per_line(mode->hts, ov02e10->link_freq_index);
636 h_blank -= mode->width;
637 ret = __v4l2_ctrl_modify_range(ov02e10->hblank, h_blank,
638 h_blank, 1, h_blank);
639 }
640
641 return ret;
642 }
643
ov02e10_get_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)644 static int ov02e10_get_format(struct v4l2_subdev *sd,
645 struct v4l2_subdev_state *sd_state,
646 struct v4l2_subdev_format *fmt)
647 {
648 struct ov02e10 *ov02e10 = to_ov02e10(sd);
649
650 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
651 fmt->format = *v4l2_subdev_state_get_format(sd_state, fmt->pad);
652 else
653 ov02e10_update_pad_format(ov02e10->cur_mode, &fmt->format);
654
655 return 0;
656 }
657
ov02e10_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)658 static int ov02e10_enum_mbus_code(struct v4l2_subdev *sd,
659 struct v4l2_subdev_state *sd_state,
660 struct v4l2_subdev_mbus_code_enum *code)
661 {
662 if (code->index > 0)
663 return -EINVAL;
664
665 code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
666
667 return 0;
668 }
669
ov02e10_enum_frame_size(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_size_enum * fse)670 static int ov02e10_enum_frame_size(struct v4l2_subdev *sd,
671 struct v4l2_subdev_state *sd_state,
672 struct v4l2_subdev_frame_size_enum *fse)
673 {
674 if (fse->index >= ARRAY_SIZE(supported_modes))
675 return -EINVAL;
676
677 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
678 return -EINVAL;
679
680 fse->min_width = supported_modes[fse->index].width;
681 fse->max_width = fse->min_width;
682 fse->min_height = supported_modes[fse->index].height;
683 fse->max_height = fse->min_height;
684
685 return 0;
686 }
687
ov02e10_init_state(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state)688 static int ov02e10_init_state(struct v4l2_subdev *sd,
689 struct v4l2_subdev_state *sd_state)
690 {
691 ov02e10_update_pad_format(&supported_modes[0],
692 v4l2_subdev_state_get_format(sd_state, 0));
693
694 return 0;
695 }
696
697 static const struct v4l2_subdev_video_ops ov02e10_video_ops = {
698 .s_stream = v4l2_subdev_s_stream_helper,
699 };
700
701 static const struct v4l2_subdev_pad_ops ov02e10_pad_ops = {
702 .set_fmt = ov02e10_set_format,
703 .get_fmt = ov02e10_get_format,
704 .enum_mbus_code = ov02e10_enum_mbus_code,
705 .enum_frame_size = ov02e10_enum_frame_size,
706 .enable_streams = ov02e10_enable_streams,
707 .disable_streams = ov02e10_disable_streams,
708 };
709
710 static const struct v4l2_subdev_ops ov02e10_subdev_ops = {
711 .video = &ov02e10_video_ops,
712 .pad = &ov02e10_pad_ops,
713 };
714
715 static const struct media_entity_operations ov02e10_subdev_entity_ops = {
716 .link_validate = v4l2_subdev_link_validate,
717 };
718
719 static const struct v4l2_subdev_internal_ops ov02e10_internal_ops = {
720 .init_state = ov02e10_init_state,
721 };
722
ov02e10_identify_module(struct ov02e10 * ov02e10)723 static int ov02e10_identify_module(struct ov02e10 *ov02e10)
724 {
725 int ret;
726 u64 val;
727
728 ret = cci_write(ov02e10->regmap, OV02E10_REG_PAGE_FLAG,
729 OV02E10_PAGE_0, NULL);
730 cci_read(ov02e10->regmap, OV02E10_REG_CHIP_ID, &val, &ret);
731 if (ret)
732 return ret;
733
734 if (val != OV02E10_CHIP_ID) {
735 dev_err(ov02e10->dev, "chip id mismatch: %x!=%x\n",
736 OV02E10_CHIP_ID, (u32)val);
737 return -ENXIO;
738 }
739
740 return 0;
741 }
742
ov02e10_check_hwcfg(struct ov02e10 * ov02e10)743 static int ov02e10_check_hwcfg(struct ov02e10 *ov02e10)
744 {
745 struct v4l2_fwnode_endpoint bus_cfg = {
746 .bus_type = V4L2_MBUS_CSI2_DPHY
747 };
748 struct device *dev = ov02e10->dev;
749 struct fwnode_handle *ep;
750 struct fwnode_handle *fwnode = dev_fwnode(dev);
751 unsigned long link_freq_bitmap;
752 int ret;
753
754 ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
755 if (!ep)
756 return dev_err_probe(dev, -EPROBE_DEFER,
757 "waiting for fwnode graph endpoint\n");
758
759 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
760 fwnode_handle_put(ep);
761 if (ret)
762 return dev_err_probe(dev, ret, "parsing endpoint failed\n");
763
764 if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV02E10_DATA_LANES) {
765 dev_err(dev, "number of CSI2 data lanes %d is not supported\n",
766 bus_cfg.bus.mipi_csi2.num_data_lanes);
767 ret = -EINVAL;
768 goto out_err;
769 }
770
771 if (!bus_cfg.nr_of_link_frequencies) {
772 dev_err(dev, "no link frequencies defined\n");
773 ret = -EINVAL;
774 goto out_err;
775 }
776
777 ret = v4l2_link_freq_to_bitmap(dev, bus_cfg.link_frequencies,
778 bus_cfg.nr_of_link_frequencies,
779 link_freq_menu_items,
780 ARRAY_SIZE(link_freq_menu_items),
781 &link_freq_bitmap);
782 if (ret)
783 goto out_err;
784
785 /* v4l2_link_freq_to_bitmap() guarantees at least 1 bit is set */
786 ov02e10->link_freq_index = ffs(link_freq_bitmap) - 1;
787 ov02e10->mipi_lanes = bus_cfg.bus.mipi_csi2.num_data_lanes;
788
789 out_err:
790 v4l2_fwnode_endpoint_free(&bus_cfg);
791
792 return ret;
793 }
794
ov02e10_remove(struct i2c_client * client)795 static void ov02e10_remove(struct i2c_client *client)
796 {
797 struct v4l2_subdev *sd = i2c_get_clientdata(client);
798 struct ov02e10 *ov02e10 = to_ov02e10(sd);
799
800 v4l2_async_unregister_subdev(sd);
801 v4l2_subdev_cleanup(sd);
802 media_entity_cleanup(&sd->entity);
803 v4l2_ctrl_handler_free(sd->ctrl_handler);
804 pm_runtime_disable(ov02e10->dev);
805
806 if (!pm_runtime_status_suspended(ov02e10->dev)) {
807 ov02e10_power_off(ov02e10->dev);
808 pm_runtime_set_suspended(ov02e10->dev);
809 }
810 }
811
ov02e10_probe(struct i2c_client * client)812 static int ov02e10_probe(struct i2c_client *client)
813 {
814 struct ov02e10 *ov02e10;
815 unsigned long freq;
816 int ret;
817
818 ov02e10 = devm_kzalloc(&client->dev, sizeof(*ov02e10), GFP_KERNEL);
819 if (!ov02e10)
820 return -ENOMEM;
821
822 ov02e10->dev = &client->dev;
823
824 ov02e10->img_clk = devm_v4l2_sensor_clk_get(ov02e10->dev, NULL);
825 if (IS_ERR(ov02e10->img_clk))
826 return dev_err_probe(ov02e10->dev, PTR_ERR(ov02e10->img_clk),
827 "failed to get imaging clock\n");
828
829 freq = clk_get_rate(ov02e10->img_clk);
830 if (freq != OV02E10_MCLK)
831 return dev_err_probe(ov02e10->dev, -EINVAL,
832 "external clock %lu is not supported",
833 freq);
834
835 v4l2_i2c_subdev_init(&ov02e10->sd, client, &ov02e10_subdev_ops);
836
837 /* Check HW config */
838 ret = ov02e10_check_hwcfg(ov02e10);
839 if (ret)
840 return ret;
841
842 /* Initialize subdev */
843 ov02e10->regmap = devm_cci_regmap_init_i2c(client, 8);
844 if (IS_ERR(ov02e10->regmap))
845 return PTR_ERR(ov02e10->regmap);
846
847 ret = ov02e10_get_pm_resources(ov02e10->dev);
848 if (ret)
849 return ret;
850
851 ret = ov02e10_power_on(ov02e10->dev);
852 if (ret) {
853 dev_err_probe(ov02e10->dev, ret, "failed to power on\n");
854 return ret;
855 }
856
857 /* Check module identity */
858 ret = ov02e10_identify_module(ov02e10);
859 if (ret) {
860 dev_err(ov02e10->dev, "failed to find sensor: %d\n", ret);
861 goto probe_error_power_off;
862 }
863
864 ov02e10->cur_mode = &supported_modes[0];
865 ret = ov02e10_init_controls(ov02e10);
866 if (ret) {
867 dev_err(ov02e10->dev, "failed to init controls: %d\n", ret);
868 goto probe_error_v4l2_ctrl_handler_free;
869 }
870
871 /* Initialize subdev */
872 ov02e10->sd.internal_ops = &ov02e10_internal_ops;
873 ov02e10->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
874 ov02e10->sd.entity.ops = &ov02e10_subdev_entity_ops;
875 ov02e10->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
876
877 /* Initialize source pad */
878 ov02e10->pad.flags = MEDIA_PAD_FL_SOURCE;
879 ret = media_entity_pads_init(&ov02e10->sd.entity, 1, &ov02e10->pad);
880 if (ret) {
881 dev_err(ov02e10->dev, "failed to init entity pads: %d", ret);
882 goto probe_error_v4l2_ctrl_handler_free;
883 }
884
885 ov02e10->sd.state_lock = ov02e10->ctrl_handler.lock;
886 ret = v4l2_subdev_init_finalize(&ov02e10->sd);
887 if (ret < 0) {
888 dev_err(ov02e10->dev, "failed to init subdev: %d", ret);
889 goto probe_error_media_entity_cleanup;
890 }
891
892 pm_runtime_set_active(ov02e10->dev);
893 pm_runtime_enable(ov02e10->dev);
894
895 ret = v4l2_async_register_subdev_sensor(&ov02e10->sd);
896 if (ret < 0) {
897 dev_err(ov02e10->dev, "failed to register V4L2 subdev: %d",
898 ret);
899 goto probe_error_v4l2_subdev_cleanup;
900 }
901
902 pm_runtime_idle(ov02e10->dev);
903 return 0;
904
905 probe_error_v4l2_subdev_cleanup:
906 pm_runtime_disable(ov02e10->dev);
907 pm_runtime_set_suspended(ov02e10->dev);
908 v4l2_subdev_cleanup(&ov02e10->sd);
909
910 probe_error_media_entity_cleanup:
911 media_entity_cleanup(&ov02e10->sd.entity);
912
913 probe_error_v4l2_ctrl_handler_free:
914 v4l2_ctrl_handler_free(ov02e10->sd.ctrl_handler);
915
916 probe_error_power_off:
917 ov02e10_power_off(ov02e10->dev);
918
919 return ret;
920 }
921
922 static DEFINE_RUNTIME_DEV_PM_OPS(ov02e10_pm_ops, ov02e10_power_off,
923 ov02e10_power_on, NULL);
924
925 static const struct acpi_device_id ov02e10_acpi_ids[] = {
926 { "OVTI02E1" },
927 { /* sentinel */ }
928 };
929
930 MODULE_DEVICE_TABLE(acpi, ov02e10_acpi_ids);
931
932 static const struct of_device_id ov02e10_of_match[] = {
933 { .compatible = "ovti,ov02e10" },
934 { /* sentinel */ }
935 };
936 MODULE_DEVICE_TABLE(of, ov02e10_of_match);
937
938 static struct i2c_driver ov02e10_i2c_driver = {
939 .driver = {
940 .name = "ov02e10",
941 .pm = pm_sleep_ptr(&ov02e10_pm_ops),
942 .acpi_match_table = ov02e10_acpi_ids,
943 .of_match_table = ov02e10_of_match,
944 },
945 .probe = ov02e10_probe,
946 .remove = ov02e10_remove,
947 };
948
949 module_i2c_driver(ov02e10_i2c_driver);
950
951 MODULE_AUTHOR("Jingjing Xiong");
952 MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
953 MODULE_AUTHOR("Alan Stern <stern@rowland.harvard.edu>");
954 MODULE_AUTHOR("Bryan O'Donoghue <bryan.odonoghue@linaro.org>");
955 MODULE_DESCRIPTION("OmniVision OV02E10 sensor driver");
956 MODULE_LICENSE("GPL");
957