1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2023 Intel Corporation.
3
4 #include <linux/acpi.h>
5 #include <linux/clk.h>
6 #include <linux/delay.h>
7 #include <linux/gpio/consumer.h>
8 #include <linux/i2c.h>
9 #include <linux/module.h>
10 #include <linux/pm_runtime.h>
11 #include <linux/regmap.h>
12 #include <media/v4l2-cci.h>
13 #include <media/v4l2-ctrls.h>
14 #include <media/v4l2-device.h>
15 #include <media/v4l2-fwnode.h>
16
17 #define OV02E10_LINK_FREQ_360MHZ 360000000ULL
18 #define OV02E10_SCLK 36000000LL
19 #define OV02E10_MCLK 19200000
20 #define OV02E10_DATA_LANES 2
21 #define OV02E10_RGB_DEPTH 10
22
23 #define OV02E10_REG_PAGE_FLAG CCI_REG8(0xfd)
24 #define OV02E10_PAGE_0 0x0
25 #define OV02E10_PAGE_1 0x1
26 #define OV02E10_PAGE_2 0x2
27 #define OV02E10_PAGE_3 0x3
28 #define OV02E10_PAGE_5 0x4
29 #define OV02E10_PAGE_7 0x5
30 #define OV02E10_PAGE_8 0x6
31 #define OV02E10_PAGE_9 0xF
32 #define OV02E10_PAGE_D 0x8
33 #define OV02E10_PAGE_E 0x9
34 #define OV02E10_PAGE_F 0xA
35
36 #define OV02E10_REG_CHIP_ID CCI_REG32(0x00)
37 #define OV02E10_CHIP_ID 0x45025610
38
39 /* Horizontal and vertical flip */
40 #define OV02E10_REG_ORIENTATION CCI_REG8(0x32)
41
42 /* vertical-timings from sensor */
43 #define OV02E10_REG_VTS CCI_REG16(0x35)
44 #define OV02E10_VTS_DEF 2244
45 #define OV02E10_VTS_MIN 2244
46 #define OV02E10_VTS_MAX 0x7fff
47
48 /* horizontal-timings from sensor */
49 #define OV02E10_REG_HTS CCI_REG16(0x37)
50
51 /* Exposure controls from sensor */
52 #define OV02E10_REG_EXPOSURE CCI_REG16(0x03)
53 #define OV02E10_EXPOSURE_MIN 1
54 #define OV02E10_EXPOSURE_MAX_MARGIN 2
55 #define OV02E10_EXPOSURE_STEP 1
56
57 /* Analog gain controls from sensor */
58 #define OV02E10_REG_ANALOG_GAIN CCI_REG8(0x24)
59 #define OV02E10_ANAL_GAIN_MIN 0x10
60 #define OV02E10_ANAL_GAIN_MAX 0xf8
61 #define OV02E10_ANAL_GAIN_STEP 1
62
63 /* Digital gain controls from sensor */
64 #define OV02E10_REG_DIGITAL_GAIN CCI_REG16(0x21)
65 #define OV02E10_DGTL_GAIN_MIN 256
66 #define OV02E10_DGTL_GAIN_MAX 1020
67 #define OV02E10_DGTL_GAIN_STEP 1
68 #define OV02E10_DGTL_GAIN_DEFAULT 256
69
70 /* Register update control */
71 #define OV02E10_REG_COMMAND_UPDATE CCI_REG8(0xE7)
72 #define OV02E10_COMMAND_UPDATE 0x00
73 #define OV02E10_COMMAND_HOLD 0x01
74
75 /* Test Pattern Control */
76 #define OV02E10_REG_TEST_PATTERN CCI_REG8(0x12)
77 #define OV02E10_TEST_PATTERN_ENABLE BIT(0)
78 #define OV02E10_TEST_PATTERN_BAR_SHIFT 1
79
80 struct reg_sequence_list {
81 u32 num_regs;
82 const struct reg_sequence *regs;
83 };
84
85 struct ov02e10_mode {
86 /* Frame width in pixels */
87 u32 width;
88
89 /* Frame height in pixels */
90 u32 height;
91
92 /* Horizontal timining size */
93 u32 hts;
94
95 /* Default vertical timing */
96 u32 vts_def;
97
98 /* Min vertical timining size */
99 u32 vts_min;
100
101 /* Sensor register settings for this resolution */
102 const struct reg_sequence_list reg_list;
103 };
104
105 static const struct reg_sequence mode_1928x1088_30fps_2lane[] = {
106 { 0xfd, 0x00 },
107 { 0x20, 0x00 },
108 { 0x20, 0x0b },
109 { 0x21, 0x02 },
110 { 0x10, 0x23 },
111 { 0xc5, 0x04 },
112 { 0x21, 0x00 },
113 { 0x14, 0x96 },
114 { 0x17, 0x01 },
115 { 0xfd, 0x01 },
116 { 0x03, 0x00 },
117 { 0x04, 0x04 },
118 { 0x05, 0x04 },
119 { 0x06, 0x62 },
120 { 0x07, 0x01 },
121 { 0x22, 0x80 },
122 { 0x24, 0xff },
123 { 0x40, 0xc6 },
124 { 0x41, 0x18 },
125 { 0x45, 0x3f },
126 { 0x48, 0x0c },
127 { 0x4c, 0x08 },
128 { 0x51, 0x12 },
129 { 0x52, 0x10 },
130 { 0x57, 0x98 },
131 { 0x59, 0x06 },
132 { 0x5a, 0x04 },
133 { 0x5c, 0x38 },
134 { 0x5e, 0x10 },
135 { 0x67, 0x11 },
136 { 0x7b, 0x04 },
137 { 0x81, 0x12 },
138 { 0x90, 0x51 },
139 { 0x91, 0x09 },
140 { 0x92, 0x21 },
141 { 0x93, 0x28 },
142 { 0x95, 0x54 },
143 { 0x9d, 0x20 },
144 { 0x9e, 0x04 },
145 { 0xb1, 0x9a },
146 { 0xb2, 0x86 },
147 { 0xb6, 0x3f },
148 { 0xb9, 0x30 },
149 { 0xc1, 0x01 },
150 { 0xc5, 0xa0 },
151 { 0xc6, 0x73 },
152 { 0xc7, 0x04 },
153 { 0xc8, 0x25 },
154 { 0xc9, 0x05 },
155 { 0xca, 0x28 },
156 { 0xcb, 0x00 },
157 { 0xcf, 0x16 },
158 { 0xd2, 0xd0 },
159 { 0xd7, 0x3f },
160 { 0xd8, 0x40 },
161 { 0xd9, 0x40 },
162 { 0xda, 0x44 },
163 { 0xdb, 0x3d },
164 { 0xdc, 0x3d },
165 { 0xdd, 0x3d },
166 { 0xde, 0x3d },
167 { 0xdf, 0xf0 },
168 { 0xea, 0x0f },
169 { 0xeb, 0x04 },
170 { 0xec, 0x29 },
171 { 0xee, 0x47 },
172 { 0xfd, 0x01 },
173 { 0x31, 0x01 },
174 { 0x27, 0x00 },
175 { 0x2f, 0x41 },
176 { 0xfd, 0x02 },
177 { 0xa1, 0x01 },
178 { 0xfd, 0x02 },
179 { 0x9a, 0x03 },
180 { 0xfd, 0x03 },
181 { 0x9d, 0x0f },
182 { 0xfd, 0x07 },
183 { 0x42, 0x00 },
184 { 0x43, 0xad },
185 { 0x44, 0x00 },
186 { 0x45, 0xa8 },
187 { 0x46, 0x00 },
188 { 0x47, 0xa8 },
189 { 0x48, 0x00 },
190 { 0x49, 0xad },
191 { 0xfd, 0x00 },
192 { 0xc4, 0x01 },
193 { 0xfd, 0x01 },
194 { 0x33, 0x03 },
195 { 0xfd, 0x00 },
196 { 0x20, 0x1f },
197 };
198
199 static const char *const ov02e10_test_pattern_menu[] = {
200 "Disabled",
201 "Color Bar",
202 };
203
204 static const s64 link_freq_menu_items[] = {
205 OV02E10_LINK_FREQ_360MHZ,
206 };
207
208 static const struct ov02e10_mode supported_modes[] = {
209 {
210 .width = 1928,
211 .height = 1088,
212 .hts = 534,
213 .vts_def = 2244,
214 .vts_min = 2244,
215 .reg_list = {
216 .num_regs = ARRAY_SIZE(mode_1928x1088_30fps_2lane),
217 .regs = mode_1928x1088_30fps_2lane,
218 },
219 },
220 };
221
222 static const char * const ov02e10_supply_names[] = {
223 "dovdd", /* Digital I/O power */
224 "avdd", /* Analog power */
225 "dvdd", /* Digital core power */
226 };
227
228 struct ov02e10 {
229 struct regmap *regmap;
230 struct v4l2_subdev sd;
231 struct media_pad pad;
232 struct v4l2_ctrl_handler ctrl_handler;
233
234 /* V4L2 Controls */
235 struct v4l2_ctrl *link_freq;
236 struct v4l2_ctrl *pixel_rate;
237 struct v4l2_ctrl *vblank;
238 struct v4l2_ctrl *hblank;
239 struct v4l2_ctrl *exposure;
240 struct v4l2_ctrl *vflip;
241 struct v4l2_ctrl *hflip;
242
243 struct clk *img_clk;
244 struct regulator_bulk_data supplies[ARRAY_SIZE(ov02e10_supply_names)];
245 struct gpio_desc *reset;
246
247 /* Current mode */
248 const struct ov02e10_mode *cur_mode;
249
250 /* MIPI lanes info */
251 u32 link_freq_index;
252 u8 mipi_lanes;
253 };
254
to_ov02e10(struct v4l2_subdev * subdev)255 static inline struct ov02e10 *to_ov02e10(struct v4l2_subdev *subdev)
256 {
257 return container_of(subdev, struct ov02e10, sd);
258 }
259
to_pixel_rate(u32 f_index)260 static u64 to_pixel_rate(u32 f_index)
261 {
262 u64 pixel_rate = link_freq_menu_items[f_index] * 2 * OV02E10_DATA_LANES;
263
264 do_div(pixel_rate, OV02E10_RGB_DEPTH);
265
266 return pixel_rate;
267 }
268
to_pixels_per_line(u32 hts,u32 f_index)269 static u64 to_pixels_per_line(u32 hts, u32 f_index)
270 {
271 u64 ppl = hts * to_pixel_rate(f_index);
272
273 do_div(ppl, OV02E10_SCLK);
274
275 return ppl;
276 }
277
ov02e10_test_pattern(struct ov02e10 * ov02e10,u32 pattern,int * pret)278 static void ov02e10_test_pattern(struct ov02e10 *ov02e10, u32 pattern, int *pret)
279 {
280 if (pattern)
281 pattern = pattern << OV02E10_TEST_PATTERN_BAR_SHIFT |
282 OV02E10_TEST_PATTERN_ENABLE;
283
284 cci_write(ov02e10->regmap, OV02E10_REG_TEST_PATTERN, pattern, pret);
285 }
286
ov02e10_set_ctrl(struct v4l2_ctrl * ctrl)287 static int ov02e10_set_ctrl(struct v4l2_ctrl *ctrl)
288 {
289 struct ov02e10 *ov02e10 = container_of(ctrl->handler,
290 struct ov02e10, ctrl_handler);
291 struct i2c_client *client = v4l2_get_subdevdata(&ov02e10->sd);
292 s64 exposure_max;
293 int ret;
294
295 /* Propagate change of current control to all related controls */
296 if (ctrl->id == V4L2_CID_VBLANK) {
297 /* Update max exposure while meeting expected vblanking */
298 exposure_max = ov02e10->cur_mode->height + ctrl->val -
299 OV02E10_EXPOSURE_MAX_MARGIN;
300 ret = __v4l2_ctrl_modify_range(ov02e10->exposure,
301 ov02e10->exposure->minimum,
302 exposure_max,
303 ov02e10->exposure->step,
304 exposure_max);
305 if (ret)
306 return ret;
307 }
308
309 /* V4L2 controls values will be applied only when power is already up */
310 if (!pm_runtime_get_if_in_use(&client->dev))
311 return 0;
312
313 ret = cci_write(ov02e10->regmap, OV02E10_REG_COMMAND_UPDATE,
314 OV02E10_COMMAND_HOLD, NULL);
315
316 switch (ctrl->id) {
317 case V4L2_CID_ANALOGUE_GAIN:
318 cci_write(ov02e10->regmap, OV02E10_REG_PAGE_FLAG,
319 OV02E10_PAGE_1, &ret);
320 cci_write(ov02e10->regmap, OV02E10_REG_ANALOG_GAIN,
321 ctrl->val, &ret);
322 break;
323
324 case V4L2_CID_DIGITAL_GAIN:
325 cci_write(ov02e10->regmap, OV02E10_REG_PAGE_FLAG,
326 OV02E10_PAGE_1, &ret);
327 cci_write(ov02e10->regmap, OV02E10_REG_DIGITAL_GAIN,
328 ctrl->val, &ret);
329 break;
330
331 case V4L2_CID_EXPOSURE:
332 cci_write(ov02e10->regmap, OV02E10_REG_PAGE_FLAG,
333 OV02E10_PAGE_1, &ret);
334 cci_write(ov02e10->regmap, OV02E10_REG_EXPOSURE,
335 ctrl->val, &ret);
336 break;
337
338 case V4L2_CID_HFLIP:
339 case V4L2_CID_VFLIP:
340 cci_write(ov02e10->regmap, OV02E10_REG_PAGE_FLAG,
341 OV02E10_PAGE_1, &ret);
342 cci_write(ov02e10->regmap, OV02E10_REG_ORIENTATION,
343 ov02e10->hflip->val | ov02e10->vflip->val << 1, &ret);
344 break;
345 case V4L2_CID_VBLANK:
346 cci_write(ov02e10->regmap, OV02E10_REG_PAGE_FLAG,
347 OV02E10_PAGE_1, &ret);
348 cci_write(ov02e10->regmap, OV02E10_REG_VTS,
349 ov02e10->cur_mode->height + ctrl->val, &ret);
350 break;
351
352 case V4L2_CID_TEST_PATTERN:
353 cci_write(ov02e10->regmap, OV02E10_REG_PAGE_FLAG,
354 OV02E10_PAGE_1, &ret);
355 ov02e10_test_pattern(ov02e10, ctrl->val, &ret);
356 break;
357
358 default:
359 ret = -EINVAL;
360 break;
361 }
362
363 cci_write(ov02e10->regmap, OV02E10_REG_COMMAND_UPDATE,
364 OV02E10_COMMAND_UPDATE, &ret);
365
366 pm_runtime_put(&client->dev);
367
368 return ret;
369 }
370
371 static const struct v4l2_ctrl_ops ov02e10_ctrl_ops = {
372 .s_ctrl = ov02e10_set_ctrl,
373 };
374
ov02e10_init_controls(struct ov02e10 * ov02e10)375 static int ov02e10_init_controls(struct ov02e10 *ov02e10)
376 {
377 struct i2c_client *client = v4l2_get_subdevdata(&ov02e10->sd);
378 struct v4l2_ctrl_handler *ctrl_hdlr = &ov02e10->ctrl_handler;
379 const struct ov02e10_mode *mode = ov02e10->cur_mode;
380 u32 vblank_min, vblank_max, vblank_def;
381 struct v4l2_fwnode_device_properties props;
382 s64 exposure_max, h_blank, pixel_rate;
383 int ret;
384
385 v4l2_ctrl_handler_init(ctrl_hdlr, 12);
386
387 ov02e10->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr,
388 &ov02e10_ctrl_ops,
389 V4L2_CID_LINK_FREQ,
390 ov02e10->link_freq_index,
391 0, link_freq_menu_items);
392 if (ov02e10->link_freq)
393 ov02e10->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
394
395 pixel_rate = to_pixel_rate(ov02e10->link_freq_index);
396 ov02e10->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov02e10_ctrl_ops,
397 V4L2_CID_PIXEL_RATE, 0,
398 pixel_rate, 1, pixel_rate);
399
400 vblank_min = mode->vts_min - mode->height;
401 vblank_max = OV02E10_VTS_MAX - mode->height;
402 vblank_def = mode->vts_def - mode->height;
403 ov02e10->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov02e10_ctrl_ops,
404 V4L2_CID_VBLANK, vblank_min,
405 vblank_max, 1, vblank_def);
406
407 h_blank = mode->hts - mode->width;
408 ov02e10->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov02e10_ctrl_ops,
409 V4L2_CID_HBLANK, h_blank, h_blank,
410 1, h_blank);
411 if (ov02e10->hblank)
412 ov02e10->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
413
414 v4l2_ctrl_new_std(ctrl_hdlr, &ov02e10_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
415 OV02E10_ANAL_GAIN_MIN, OV02E10_ANAL_GAIN_MAX,
416 OV02E10_ANAL_GAIN_STEP, OV02E10_ANAL_GAIN_MIN);
417
418 v4l2_ctrl_new_std(ctrl_hdlr, &ov02e10_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
419 OV02E10_DGTL_GAIN_MIN, OV02E10_DGTL_GAIN_MAX,
420 OV02E10_DGTL_GAIN_STEP, OV02E10_DGTL_GAIN_DEFAULT);
421
422 exposure_max = mode->vts_def - OV02E10_EXPOSURE_MAX_MARGIN;
423 ov02e10->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov02e10_ctrl_ops,
424 V4L2_CID_EXPOSURE,
425 OV02E10_EXPOSURE_MIN,
426 exposure_max,
427 OV02E10_EXPOSURE_STEP,
428 exposure_max);
429
430 ov02e10->hflip = v4l2_ctrl_new_std(ctrl_hdlr, &ov02e10_ctrl_ops,
431 V4L2_CID_HFLIP, 0, 1, 1, 0);
432 if (ov02e10->hflip)
433 ov02e10->hflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;
434
435 ov02e10->vflip = v4l2_ctrl_new_std(ctrl_hdlr, &ov02e10_ctrl_ops,
436 V4L2_CID_VFLIP, 0, 1, 1, 0);
437 if (ov02e10->vflip)
438 ov02e10->vflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;
439
440 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov02e10_ctrl_ops,
441 V4L2_CID_TEST_PATTERN,
442 ARRAY_SIZE(ov02e10_test_pattern_menu) - 1,
443 0, 0, ov02e10_test_pattern_menu);
444
445 ret = v4l2_fwnode_device_parse(&client->dev, &props);
446 if (ret)
447 return ret;
448
449 v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &ov02e10_ctrl_ops, &props);
450
451 if (ctrl_hdlr->error)
452 return ctrl_hdlr->error;
453
454 ov02e10->sd.ctrl_handler = ctrl_hdlr;
455
456 return 0;
457 }
458
ov02e10_update_pad_format(const struct ov02e10_mode * mode,struct v4l2_mbus_framefmt * fmt)459 static void ov02e10_update_pad_format(const struct ov02e10_mode *mode,
460 struct v4l2_mbus_framefmt *fmt)
461 {
462 fmt->width = mode->width;
463 fmt->height = mode->height;
464 fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
465 fmt->field = V4L2_FIELD_NONE;
466 }
467
ov02e10_set_stream_mode(struct ov02e10 * ov02e10,u8 val)468 static int ov02e10_set_stream_mode(struct ov02e10 *ov02e10, u8 val)
469 {
470 int ret = 0;
471
472 cci_write(ov02e10->regmap, OV02E10_REG_PAGE_FLAG, OV02E10_PAGE_0, &ret);
473 cci_write(ov02e10->regmap, CCI_REG8(0xa0), val, &ret);
474 cci_write(ov02e10->regmap, OV02E10_REG_PAGE_FLAG, OV02E10_PAGE_1, &ret);
475 cci_write(ov02e10->regmap, CCI_REG8(0x01), 0x02, &ret);
476
477 return ret;
478 }
479
ov02e10_enable_streams(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,u32 pad,u64 streams_mask)480 static int ov02e10_enable_streams(struct v4l2_subdev *sd,
481 struct v4l2_subdev_state *state,
482 u32 pad, u64 streams_mask)
483 {
484 struct i2c_client *client = v4l2_get_subdevdata(sd);
485 struct ov02e10 *ov02e10 = to_ov02e10(sd);
486 const struct reg_sequence_list *reg_list;
487 int ret;
488
489 ret = pm_runtime_resume_and_get(&client->dev);
490 if (ret)
491 return ret;
492
493 reg_list = &ov02e10->cur_mode->reg_list;
494 ret = regmap_multi_reg_write(ov02e10->regmap, reg_list->regs,
495 reg_list->num_regs);
496 if (ret) {
497 dev_err(&client->dev, "failed to set mode\n");
498 goto out;
499 }
500
501 ret = __v4l2_ctrl_handler_setup(ov02e10->sd.ctrl_handler);
502 if (ret)
503 goto out;
504
505 ret = ov02e10_set_stream_mode(ov02e10, 1);
506
507 out:
508 if (ret)
509 pm_runtime_put(&client->dev);
510
511 return ret;
512 }
513
ov02e10_disable_streams(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,u32 pad,u64 streams_mask)514 static int ov02e10_disable_streams(struct v4l2_subdev *sd,
515 struct v4l2_subdev_state *state,
516 u32 pad, u64 streams_mask)
517 {
518 struct i2c_client *client = v4l2_get_subdevdata(sd);
519 struct ov02e10 *ov02e10 = to_ov02e10(sd);
520
521 ov02e10_set_stream_mode(ov02e10, 0);
522 pm_runtime_put(&client->dev);
523
524 return 0;
525 }
526
ov02e10_get_pm_resources(struct device * dev)527 static int ov02e10_get_pm_resources(struct device *dev)
528 {
529 struct v4l2_subdev *sd = dev_get_drvdata(dev);
530 struct ov02e10 *ov02e10 = to_ov02e10(sd);
531 int i;
532
533 ov02e10->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
534 if (IS_ERR(ov02e10->reset))
535 return dev_err_probe(dev, PTR_ERR(ov02e10->reset),
536 "failed to get reset gpio\n");
537
538 for (i = 0; i < ARRAY_SIZE(ov02e10_supply_names); i++)
539 ov02e10->supplies[i].supply = ov02e10_supply_names[i];
540
541 return devm_regulator_bulk_get(dev, ARRAY_SIZE(ov02e10_supply_names),
542 ov02e10->supplies);
543 }
544
ov02e10_power_off(struct device * dev)545 static int ov02e10_power_off(struct device *dev)
546 {
547 struct v4l2_subdev *sd = dev_get_drvdata(dev);
548 struct ov02e10 *ov02e10 = to_ov02e10(sd);
549
550 if (ov02e10->reset)
551 gpiod_set_value_cansleep(ov02e10->reset, 1);
552
553 regulator_bulk_disable(ARRAY_SIZE(ov02e10_supply_names),
554 ov02e10->supplies);
555
556 clk_disable_unprepare(ov02e10->img_clk);
557
558 return 0;
559 }
560
ov02e10_power_on(struct device * dev)561 static int ov02e10_power_on(struct device *dev)
562 {
563 struct v4l2_subdev *sd = dev_get_drvdata(dev);
564 struct ov02e10 *ov02e10 = to_ov02e10(sd);
565 int ret;
566
567 ret = clk_prepare_enable(ov02e10->img_clk);
568 if (ret < 0) {
569 dev_err(dev, "failed to enable imaging clock: %d\n", ret);
570 return ret;
571 }
572
573 ret = regulator_bulk_enable(ARRAY_SIZE(ov02e10_supply_names),
574 ov02e10->supplies);
575 if (ret < 0) {
576 dev_err(dev, "failed to enable regulators\n");
577 goto disable_clk;
578 }
579
580 if (ov02e10->reset) {
581 usleep_range(5000, 5100);
582 gpiod_set_value_cansleep(ov02e10->reset, 0);
583 usleep_range(8000, 8100);
584 }
585
586 return 0;
587
588 disable_clk:
589 clk_disable_unprepare(ov02e10->img_clk);
590
591 return ret;
592 }
593
ov02e10_set_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)594 static int ov02e10_set_format(struct v4l2_subdev *sd,
595 struct v4l2_subdev_state *sd_state,
596 struct v4l2_subdev_format *fmt)
597 {
598 struct ov02e10 *ov02e10 = to_ov02e10(sd);
599 const struct ov02e10_mode *mode;
600 s32 vblank_def, h_blank;
601 int ret = 0;
602
603 mode = v4l2_find_nearest_size(supported_modes,
604 ARRAY_SIZE(supported_modes),
605 width, height, fmt->format.width,
606 fmt->format.height);
607
608 ov02e10_update_pad_format(mode, &fmt->format);
609
610 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
611 *v4l2_subdev_state_get_format(sd_state, fmt->pad) = fmt->format;
612 } else {
613 ov02e10->cur_mode = mode;
614 ret = __v4l2_ctrl_s_ctrl(ov02e10->link_freq,
615 ov02e10->link_freq_index);
616 if (ret)
617 return ret;
618
619 ret = __v4l2_ctrl_s_ctrl_int64(ov02e10->pixel_rate,
620 to_pixel_rate(ov02e10->link_freq_index));
621 if (ret)
622 return ret;
623
624 /* Update limits and set FPS to default */
625 vblank_def = mode->vts_def - mode->height;
626 ret = __v4l2_ctrl_modify_range(ov02e10->vblank,
627 mode->vts_min - mode->height,
628 OV02E10_VTS_MAX - mode->height,
629 1, vblank_def);
630 if (ret)
631 return ret;
632
633 ret = __v4l2_ctrl_s_ctrl(ov02e10->vblank, vblank_def);
634 if (ret)
635 return ret;
636
637 h_blank = to_pixels_per_line(mode->hts, ov02e10->link_freq_index);
638 h_blank -= mode->width;
639 ret = __v4l2_ctrl_modify_range(ov02e10->hblank, h_blank,
640 h_blank, 1, h_blank);
641 }
642
643 return ret;
644 }
645
ov02e10_get_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)646 static int ov02e10_get_format(struct v4l2_subdev *sd,
647 struct v4l2_subdev_state *sd_state,
648 struct v4l2_subdev_format *fmt)
649 {
650 struct ov02e10 *ov02e10 = to_ov02e10(sd);
651
652 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
653 fmt->format = *v4l2_subdev_state_get_format(sd_state, fmt->pad);
654 else
655 ov02e10_update_pad_format(ov02e10->cur_mode, &fmt->format);
656
657 return 0;
658 }
659
ov02e10_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)660 static int ov02e10_enum_mbus_code(struct v4l2_subdev *sd,
661 struct v4l2_subdev_state *sd_state,
662 struct v4l2_subdev_mbus_code_enum *code)
663 {
664 if (code->index > 0)
665 return -EINVAL;
666
667 code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
668
669 return 0;
670 }
671
ov02e10_enum_frame_size(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_size_enum * fse)672 static int ov02e10_enum_frame_size(struct v4l2_subdev *sd,
673 struct v4l2_subdev_state *sd_state,
674 struct v4l2_subdev_frame_size_enum *fse)
675 {
676 if (fse->index >= ARRAY_SIZE(supported_modes))
677 return -EINVAL;
678
679 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
680 return -EINVAL;
681
682 fse->min_width = supported_modes[fse->index].width;
683 fse->max_width = fse->min_width;
684 fse->min_height = supported_modes[fse->index].height;
685 fse->max_height = fse->min_height;
686
687 return 0;
688 }
689
ov02e10_init_state(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state)690 static int ov02e10_init_state(struct v4l2_subdev *sd,
691 struct v4l2_subdev_state *sd_state)
692 {
693 ov02e10_update_pad_format(&supported_modes[0],
694 v4l2_subdev_state_get_format(sd_state, 0));
695
696 return 0;
697 }
698
699 static const struct v4l2_subdev_video_ops ov02e10_video_ops = {
700 .s_stream = v4l2_subdev_s_stream_helper,
701 };
702
703 static const struct v4l2_subdev_pad_ops ov02e10_pad_ops = {
704 .set_fmt = ov02e10_set_format,
705 .get_fmt = ov02e10_get_format,
706 .enum_mbus_code = ov02e10_enum_mbus_code,
707 .enum_frame_size = ov02e10_enum_frame_size,
708 .enable_streams = ov02e10_enable_streams,
709 .disable_streams = ov02e10_disable_streams,
710 };
711
712 static const struct v4l2_subdev_ops ov02e10_subdev_ops = {
713 .video = &ov02e10_video_ops,
714 .pad = &ov02e10_pad_ops,
715 };
716
717 static const struct media_entity_operations ov02e10_subdev_entity_ops = {
718 .link_validate = v4l2_subdev_link_validate,
719 };
720
721 static const struct v4l2_subdev_internal_ops ov02e10_internal_ops = {
722 .init_state = ov02e10_init_state,
723 };
724
ov02e10_identify_module(struct ov02e10 * ov02e10)725 static int ov02e10_identify_module(struct ov02e10 *ov02e10)
726 {
727 struct i2c_client *client = v4l2_get_subdevdata(&ov02e10->sd);
728 int ret;
729 u64 val;
730
731 ret = cci_write(ov02e10->regmap, OV02E10_REG_PAGE_FLAG,
732 OV02E10_PAGE_0, NULL);
733 cci_read(ov02e10->regmap, OV02E10_REG_CHIP_ID, &val, &ret);
734 if (ret)
735 return ret;
736
737 if (val != OV02E10_CHIP_ID) {
738 dev_err(&client->dev, "chip id mismatch: %x!=%x\n",
739 OV02E10_CHIP_ID, (u32)val);
740 return -ENXIO;
741 }
742
743 return 0;
744 }
745
ov02e10_check_hwcfg(struct device * dev,struct ov02e10 * ov02e10)746 static int ov02e10_check_hwcfg(struct device *dev, struct ov02e10 *ov02e10)
747 {
748 struct v4l2_fwnode_endpoint bus_cfg = {
749 .bus_type = V4L2_MBUS_CSI2_DPHY
750 };
751 struct fwnode_handle *ep;
752 struct fwnode_handle *fwnode = dev_fwnode(dev);
753 unsigned long link_freq_bitmap;
754 u32 ext_clk;
755 int ret;
756
757 ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
758 if (!ep)
759 return dev_err_probe(dev, -EPROBE_DEFER,
760 "waiting for fwnode graph endpoint\n");
761
762 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
763 fwnode_handle_put(ep);
764 if (ret)
765 return dev_err_probe(dev, ret, "parsing endpoint failed\n");
766
767 ov02e10->img_clk = devm_clk_get_optional(dev, NULL);
768 if (IS_ERR(ov02e10->img_clk)) {
769 ret = dev_err_probe(dev, PTR_ERR(ov02e10->img_clk),
770 "failed to get imaging clock\n");
771 goto out_err;
772 }
773
774 if (ov02e10->img_clk) {
775 ext_clk = clk_get_rate(ov02e10->img_clk);
776 } else {
777 ret = fwnode_property_read_u32(dev_fwnode(dev), "clock-frequency",
778 &ext_clk);
779 if (ret) {
780 dev_err(dev, "can't get clock frequency\n");
781 goto out_err;
782 }
783 }
784
785 if (ext_clk != OV02E10_MCLK) {
786 dev_err(dev, "external clock %d is not supported\n",
787 ext_clk);
788 ret = -EINVAL;
789 goto out_err;
790 }
791
792 if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV02E10_DATA_LANES) {
793 dev_err(dev, "number of CSI2 data lanes %d is not supported\n",
794 bus_cfg.bus.mipi_csi2.num_data_lanes);
795 ret = -EINVAL;
796 goto out_err;
797 }
798
799 if (!bus_cfg.nr_of_link_frequencies) {
800 dev_err(dev, "no link frequencies defined\n");
801 ret = -EINVAL;
802 goto out_err;
803 }
804
805 ret = v4l2_link_freq_to_bitmap(dev, bus_cfg.link_frequencies,
806 bus_cfg.nr_of_link_frequencies,
807 link_freq_menu_items,
808 ARRAY_SIZE(link_freq_menu_items),
809 &link_freq_bitmap);
810 if (ret)
811 goto out_err;
812
813 /* v4l2_link_freq_to_bitmap() guarantees at least 1 bit is set */
814 ov02e10->link_freq_index = ffs(link_freq_bitmap) - 1;
815 ov02e10->mipi_lanes = bus_cfg.bus.mipi_csi2.num_data_lanes;
816
817 out_err:
818 v4l2_fwnode_endpoint_free(&bus_cfg);
819
820 return ret;
821 }
822
ov02e10_remove(struct i2c_client * client)823 static void ov02e10_remove(struct i2c_client *client)
824 {
825 struct v4l2_subdev *sd = i2c_get_clientdata(client);
826
827 v4l2_async_unregister_subdev(sd);
828 v4l2_subdev_cleanup(sd);
829 media_entity_cleanup(&sd->entity);
830 v4l2_ctrl_handler_free(sd->ctrl_handler);
831 pm_runtime_disable(&client->dev);
832
833 if (!pm_runtime_status_suspended(&client->dev)) {
834 ov02e10_power_off(&client->dev);
835 pm_runtime_set_suspended(&client->dev);
836 }
837 }
838
ov02e10_probe(struct i2c_client * client)839 static int ov02e10_probe(struct i2c_client *client)
840 {
841 struct ov02e10 *ov02e10;
842 int ret;
843
844 ov02e10 = devm_kzalloc(&client->dev, sizeof(*ov02e10), GFP_KERNEL);
845 if (!ov02e10)
846 return -ENOMEM;
847
848 v4l2_i2c_subdev_init(&ov02e10->sd, client, &ov02e10_subdev_ops);
849
850 /* Check HW config */
851 ret = ov02e10_check_hwcfg(&client->dev, ov02e10);
852 if (ret)
853 return ret;
854
855 /* Initialize subdev */
856 ov02e10->regmap = devm_cci_regmap_init_i2c(client, 8);
857 if (IS_ERR(ov02e10->regmap))
858 return PTR_ERR(ov02e10->regmap);
859
860 ret = ov02e10_get_pm_resources(&client->dev);
861 if (ret)
862 return ret;
863
864 ret = ov02e10_power_on(&client->dev);
865 if (ret) {
866 dev_err_probe(&client->dev, ret, "failed to power on\n");
867 return ret;
868 }
869
870 /* Check module identity */
871 ret = ov02e10_identify_module(ov02e10);
872 if (ret) {
873 dev_err(&client->dev, "failed to find sensor: %d\n", ret);
874 goto probe_error_power_off;
875 }
876
877 ov02e10->cur_mode = &supported_modes[0];
878 ret = ov02e10_init_controls(ov02e10);
879 if (ret) {
880 dev_err(&client->dev, "failed to init controls: %d\n", ret);
881 goto probe_error_v4l2_ctrl_handler_free;
882 }
883
884 /* Initialize subdev */
885 ov02e10->sd.internal_ops = &ov02e10_internal_ops;
886 ov02e10->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
887 ov02e10->sd.entity.ops = &ov02e10_subdev_entity_ops;
888 ov02e10->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
889
890 /* Initialize source pad */
891 ov02e10->pad.flags = MEDIA_PAD_FL_SOURCE;
892 ret = media_entity_pads_init(&ov02e10->sd.entity, 1, &ov02e10->pad);
893 if (ret) {
894 dev_err(&client->dev, "failed to init entity pads: %d", ret);
895 goto probe_error_v4l2_ctrl_handler_free;
896 }
897
898 ov02e10->sd.state_lock = ov02e10->ctrl_handler.lock;
899 ret = v4l2_subdev_init_finalize(&ov02e10->sd);
900 if (ret < 0) {
901 dev_err(&client->dev, "failed to init subdev: %d", ret);
902 goto probe_error_media_entity_cleanup;
903 }
904
905 pm_runtime_set_active(&client->dev);
906 pm_runtime_enable(&client->dev);
907
908 ret = v4l2_async_register_subdev_sensor(&ov02e10->sd);
909 if (ret < 0) {
910 dev_err(&client->dev, "failed to register V4L2 subdev: %d",
911 ret);
912 goto probe_error_v4l2_subdev_cleanup;
913 }
914
915 pm_runtime_idle(&client->dev);
916 return 0;
917
918 probe_error_v4l2_subdev_cleanup:
919 pm_runtime_disable(&client->dev);
920 pm_runtime_set_suspended(&client->dev);
921 v4l2_subdev_cleanup(&ov02e10->sd);
922
923 probe_error_media_entity_cleanup:
924 media_entity_cleanup(&ov02e10->sd.entity);
925
926 probe_error_v4l2_ctrl_handler_free:
927 v4l2_ctrl_handler_free(ov02e10->sd.ctrl_handler);
928
929 probe_error_power_off:
930 ov02e10_power_off(&client->dev);
931
932 return ret;
933 }
934
935 static DEFINE_RUNTIME_DEV_PM_OPS(ov02e10_pm_ops, ov02e10_power_off,
936 ov02e10_power_on, NULL);
937
938 static const struct acpi_device_id ov02e10_acpi_ids[] = {
939 { "OVTI02E1" },
940 { /* sentinel */ }
941 };
942
943 MODULE_DEVICE_TABLE(acpi, ov02e10_acpi_ids);
944
945 static const struct of_device_id ov02e10_of_match[] = {
946 { .compatible = "ovti,ov02e10" },
947 { /* sentinel */ }
948 };
949 MODULE_DEVICE_TABLE(of, ov02e10_of_match);
950
951 static struct i2c_driver ov02e10_i2c_driver = {
952 .driver = {
953 .name = "ov02e10",
954 .pm = pm_sleep_ptr(&ov02e10_pm_ops),
955 .acpi_match_table = ov02e10_acpi_ids,
956 .of_match_table = ov02e10_of_match,
957 },
958 .probe = ov02e10_probe,
959 .remove = ov02e10_remove,
960 };
961
962 module_i2c_driver(ov02e10_i2c_driver);
963
964 MODULE_AUTHOR("Jingjing Xiong <jingjing.xiong@intel.com>");
965 MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
966 MODULE_AUTHOR("Alan Stern <stern@rowland.harvard.edu>");
967 MODULE_AUTHOR("Bryan O'Donoghue <bryan.odonoghue@linaro.org>");
968 MODULE_DESCRIPTION("OmniVision OV02E10 sensor driver");
969 MODULE_LICENSE("GPL");
970