1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2022 Intel Corporation.
3
4 #include <linux/acpi.h>
5 #include <linux/clk.h>
6 #include <linux/delay.h>
7 #include <linux/gpio/consumer.h>
8 #include <linux/i2c.h>
9 #include <linux/module.h>
10 #include <linux/pm_runtime.h>
11 #include <linux/regmap.h>
12 #include <linux/version.h>
13 #include <media/v4l2-cci.h>
14 #include <media/v4l2-ctrls.h>
15 #include <media/v4l2-device.h>
16 #include <media/v4l2-fwnode.h>
17
18 #define OV02C10_LINK_FREQ_400MHZ 400000000ULL
19 #define OV02C10_MCLK 19200000
20 #define OV02C10_RGB_DEPTH 10
21
22 #define OV02C10_REG_CHIP_ID CCI_REG16(0x300a)
23 #define OV02C10_CHIP_ID 0x5602
24
25 #define OV02C10_REG_STREAM_CONTROL CCI_REG8(0x0100)
26
27 #define OV02C10_REG_HTS CCI_REG16(0x380c)
28
29 /* vertical-timings from sensor */
30 #define OV02C10_REG_VTS CCI_REG16(0x380e)
31 #define OV02C10_VTS_MAX 0xffff
32
33 /* Exposure controls from sensor */
34 #define OV02C10_REG_EXPOSURE CCI_REG16(0x3501)
35 #define OV02C10_EXPOSURE_MIN 4
36 #define OV02C10_EXPOSURE_MAX_MARGIN 8
37 #define OV02C10_EXPOSURE_STEP 1
38
39 /* Analog gain controls from sensor */
40 #define OV02C10_REG_ANALOG_GAIN CCI_REG16(0x3508)
41 #define OV02C10_ANAL_GAIN_MIN 0x10
42 #define OV02C10_ANAL_GAIN_MAX 0xf8
43 #define OV02C10_ANAL_GAIN_STEP 1
44 #define OV02C10_ANAL_GAIN_DEFAULT 0x10
45
46 /* Digital gain controls from sensor */
47 #define OV02C10_REG_DIGITAL_GAIN CCI_REG24(0x350a)
48 #define OV02C10_DGTL_GAIN_MIN 0x0400
49 #define OV02C10_DGTL_GAIN_MAX 0x3fff
50 #define OV02C10_DGTL_GAIN_STEP 1
51 #define OV02C10_DGTL_GAIN_DEFAULT 0x0400
52
53 /* Rotate */
54 #define OV02C10_ROTATE_CONTROL CCI_REG8(0x3820)
55 #define OV02C10_ISP_X_WIN_CONTROL CCI_REG16(0x3810)
56 #define OV02C10_ISP_Y_WIN_CONTROL CCI_REG16(0x3812)
57 #define OV02C10_CONFIG_ROTATE 0x18
58
59 /* Test Pattern Control */
60 #define OV02C10_REG_TEST_PATTERN CCI_REG8(0x4503)
61 #define OV02C10_TEST_PATTERN_ENABLE BIT(7)
62
63 struct ov02c10_mode {
64 /* Frame width in pixels */
65 u32 width;
66
67 /* Frame height in pixels */
68 u32 height;
69
70 /* Horizontal timining size */
71 u32 hts;
72
73 /* Min vertical timining size */
74 u32 vts_min;
75
76 /* Sensor register settings for this resolution */
77 const struct reg_sequence *reg_sequence;
78 const int sequence_length;
79 /* Sensor register settings for 1 or 2 lane config */
80 const struct reg_sequence *lane_settings[2];
81 const int lane_settings_length[2];
82 };
83
84 static const struct reg_sequence sensor_1928x1092_30fps_setting[] = {
85 {0x0301, 0x08},
86 {0x0303, 0x06},
87 {0x0304, 0x01},
88 {0x0305, 0xe0},
89 {0x0313, 0x40},
90 {0x031c, 0x4f},
91 {0x3020, 0x97},
92 {0x3022, 0x01},
93 {0x3026, 0xb4},
94 {0x303b, 0x00},
95 {0x303c, 0x4f},
96 {0x303d, 0xe6},
97 {0x303e, 0x00},
98 {0x303f, 0x03},
99 {0x3021, 0x23},
100 {0x3501, 0x04},
101 {0x3502, 0x6c},
102 {0x3504, 0x0c},
103 {0x3507, 0x00},
104 {0x3508, 0x08},
105 {0x3509, 0x00},
106 {0x350a, 0x01},
107 {0x350b, 0x00},
108 {0x350c, 0x41},
109 {0x3600, 0x84},
110 {0x3603, 0x08},
111 {0x3610, 0x57},
112 {0x3611, 0x1b},
113 {0x3613, 0x78},
114 {0x3623, 0x00},
115 {0x3632, 0xa0},
116 {0x3642, 0xe8},
117 {0x364c, 0x70},
118 {0x365f, 0x0f},
119 {0x3708, 0x30},
120 {0x3714, 0x24},
121 {0x3725, 0x02},
122 {0x3737, 0x08},
123 {0x3739, 0x28},
124 {0x3749, 0x32},
125 {0x374a, 0x32},
126 {0x374b, 0x32},
127 {0x374c, 0x32},
128 {0x374d, 0x81},
129 {0x374e, 0x81},
130 {0x374f, 0x81},
131 {0x3752, 0x36},
132 {0x3753, 0x36},
133 {0x3754, 0x36},
134 {0x3761, 0x00},
135 {0x376c, 0x81},
136 {0x3774, 0x18},
137 {0x3776, 0x08},
138 {0x377c, 0x81},
139 {0x377d, 0x81},
140 {0x377e, 0x81},
141 {0x37a0, 0x44},
142 {0x37a6, 0x44},
143 {0x37aa, 0x0d},
144 {0x37ae, 0x00},
145 {0x37cb, 0x03},
146 {0x37cc, 0x01},
147 {0x37d8, 0x02},
148 {0x37d9, 0x10},
149 {0x37e1, 0x10},
150 {0x37e2, 0x18},
151 {0x37e3, 0x08},
152 {0x37e4, 0x08},
153 {0x37e5, 0x02},
154 {0x37e6, 0x08},
155
156 /* 1928x1092 */
157 {0x3800, 0x00},
158 {0x3801, 0x00},
159 {0x3802, 0x00},
160 {0x3803, 0x00},
161 {0x3804, 0x07},
162 {0x3805, 0x8f},
163 {0x3806, 0x04},
164 {0x3807, 0x47},
165 {0x3808, 0x07},
166 {0x3809, 0x88},
167 {0x380a, 0x04},
168 {0x380b, 0x44},
169 {0x3810, 0x00},
170 {0x3811, 0x02},
171 {0x3812, 0x00},
172 {0x3813, 0x02},
173 {0x3814, 0x01},
174 {0x3815, 0x01},
175 {0x3816, 0x01},
176 {0x3817, 0x01},
177
178 {0x3820, 0xb0},
179 {0x3821, 0x00},
180 {0x3822, 0x80},
181 {0x3823, 0x08},
182 {0x3824, 0x00},
183 {0x3825, 0x20},
184 {0x3826, 0x00},
185 {0x3827, 0x08},
186 {0x382a, 0x00},
187 {0x382b, 0x08},
188 {0x382d, 0x00},
189 {0x382e, 0x00},
190 {0x382f, 0x23},
191 {0x3834, 0x00},
192 {0x3839, 0x00},
193 {0x383a, 0xd1},
194 {0x383e, 0x03},
195 {0x393d, 0x29},
196 {0x393f, 0x6e},
197 {0x394b, 0x06},
198 {0x394c, 0x06},
199 {0x394d, 0x08},
200 {0x394f, 0x01},
201 {0x3950, 0x01},
202 {0x3951, 0x01},
203 {0x3952, 0x01},
204 {0x3953, 0x01},
205 {0x3954, 0x01},
206 {0x3955, 0x01},
207 {0x3956, 0x01},
208 {0x3957, 0x0e},
209 {0x3958, 0x08},
210 {0x3959, 0x08},
211 {0x395a, 0x08},
212 {0x395b, 0x13},
213 {0x395c, 0x09},
214 {0x395d, 0x05},
215 {0x395e, 0x02},
216 {0x395f, 0x00},
217 {0x395f, 0x00},
218 {0x3960, 0x00},
219 {0x3961, 0x00},
220 {0x3962, 0x00},
221 {0x3963, 0x00},
222 {0x3964, 0x00},
223 {0x3965, 0x00},
224 {0x3966, 0x00},
225 {0x3967, 0x00},
226 {0x3968, 0x01},
227 {0x3969, 0x01},
228 {0x396a, 0x01},
229 {0x396b, 0x01},
230 {0x396c, 0x10},
231 {0x396d, 0xf0},
232 {0x396e, 0x11},
233 {0x396f, 0x00},
234 {0x3970, 0x37},
235 {0x3971, 0x37},
236 {0x3972, 0x37},
237 {0x3973, 0x37},
238 {0x3974, 0x00},
239 {0x3975, 0x3c},
240 {0x3976, 0x3c},
241 {0x3977, 0x3c},
242 {0x3978, 0x3c},
243 {0x3c00, 0x0f},
244 {0x3c20, 0x01},
245 {0x3c21, 0x08},
246 {0x3f00, 0x8b},
247 {0x3f02, 0x0f},
248 {0x4000, 0xc3},
249 {0x4001, 0xe0},
250 {0x4002, 0x00},
251 {0x4003, 0x40},
252 {0x4008, 0x04},
253 {0x4009, 0x23},
254 {0x400a, 0x04},
255 {0x400b, 0x01},
256 {0x4077, 0x06},
257 {0x4078, 0x00},
258 {0x4079, 0x1a},
259 {0x407a, 0x7f},
260 {0x407b, 0x01},
261 {0x4080, 0x03},
262 {0x4081, 0x84},
263 {0x4308, 0x03},
264 {0x4309, 0xff},
265 {0x430d, 0x00},
266 {0x4806, 0x00},
267 {0x4813, 0x00},
268 {0x4837, 0x10},
269 {0x4857, 0x05},
270 {0x4500, 0x07},
271 {0x4501, 0x00},
272 {0x4503, 0x00},
273 {0x450a, 0x04},
274 {0x450e, 0x00},
275 {0x450f, 0x00},
276 {0x4900, 0x00},
277 {0x4901, 0x00},
278 {0x4902, 0x01},
279 {0x5001, 0x50},
280 {0x5006, 0x00},
281 {0x5080, 0x40},
282 {0x5181, 0x2b},
283 {0x5202, 0xa3},
284 {0x5206, 0x01},
285 {0x5207, 0x00},
286 {0x520a, 0x01},
287 {0x520b, 0x00},
288 {0x365d, 0x00},
289 {0x4815, 0x40},
290 {0x4816, 0x12},
291 {0x4f00, 0x01},
292 };
293
294 static const struct reg_sequence sensor_1928x1092_30fps_1lane_setting[] = {
295 {0x301b, 0xd2},
296 {0x3027, 0xe1},
297 {0x380c, 0x08},
298 {0x380d, 0xe8},
299 {0x380e, 0x04},
300 {0x380f, 0x8c},
301 {0x394e, 0x0b},
302 {0x4800, 0x24},
303 {0x5000, 0xf5},
304 /* plls */
305 {0x0303, 0x05},
306 {0x0305, 0x90},
307 {0x0316, 0x90},
308 {0x3016, 0x12},
309 };
310
311 static const struct reg_sequence sensor_1928x1092_30fps_2lane_setting[] = {
312 {0x301b, 0xf0},
313 {0x3027, 0xf1},
314 {0x380c, 0x04},
315 {0x380d, 0x74},
316 {0x380e, 0x09},
317 {0x380f, 0x18},
318 {0x394e, 0x0a},
319 {0x4041, 0x20},
320 {0x4884, 0x04},
321 {0x4800, 0x64},
322 {0x4d00, 0x03},
323 {0x4d01, 0xd8},
324 {0x4d02, 0xba},
325 {0x4d03, 0xa0},
326 {0x4d04, 0xb7},
327 {0x4d05, 0x34},
328 {0x4d0d, 0x00},
329 {0x5000, 0xfd},
330 {0x481f, 0x30},
331 /* plls */
332 {0x0303, 0x05},
333 {0x0305, 0x90},
334 {0x0316, 0x90},
335 {0x3016, 0x32},
336 };
337
338 static const char * const ov02c10_test_pattern_menu[] = {
339 "Disabled",
340 "Color Bar",
341 "Top-Bottom Darker Color Bar",
342 "Right-Left Darker Color Bar",
343 "Color Bar type 4",
344 };
345
346 static const s64 link_freq_menu_items[] = {
347 OV02C10_LINK_FREQ_400MHZ,
348 };
349
350 static const struct ov02c10_mode supported_modes[] = {
351 {
352 .width = 1928,
353 .height = 1092,
354 .hts = 2280,
355 .vts_min = 1164,
356 .reg_sequence = sensor_1928x1092_30fps_setting,
357 .sequence_length = ARRAY_SIZE(sensor_1928x1092_30fps_setting),
358 .lane_settings = {
359 sensor_1928x1092_30fps_1lane_setting,
360 sensor_1928x1092_30fps_2lane_setting
361 },
362 .lane_settings_length = {
363 ARRAY_SIZE(sensor_1928x1092_30fps_1lane_setting),
364 ARRAY_SIZE(sensor_1928x1092_30fps_2lane_setting),
365 },
366 },
367 };
368
369 static const char * const ov02c10_supply_names[] = {
370 "dovdd", /* Digital I/O power */
371 "avdd", /* Analog power */
372 "dvdd", /* Digital core power */
373 };
374
375 struct ov02c10 {
376 struct v4l2_subdev sd;
377 struct media_pad pad;
378 struct v4l2_ctrl_handler ctrl_handler;
379 struct regmap *regmap;
380
381 /* V4L2 Controls */
382 struct v4l2_ctrl *link_freq;
383 struct v4l2_ctrl *pixel_rate;
384 struct v4l2_ctrl *vblank;
385 struct v4l2_ctrl *hblank;
386 struct v4l2_ctrl *exposure;
387
388 struct clk *img_clk;
389 struct gpio_desc *reset;
390 struct regulator_bulk_data supplies[ARRAY_SIZE(ov02c10_supply_names)];
391
392 /* MIPI lane info */
393 u32 link_freq_index;
394 u8 mipi_lanes;
395 };
396
to_ov02c10(struct v4l2_subdev * subdev)397 static inline struct ov02c10 *to_ov02c10(struct v4l2_subdev *subdev)
398 {
399 return container_of(subdev, struct ov02c10, sd);
400 }
401
ov02c10_test_pattern(struct ov02c10 * ov02c10,int pattern)402 static int ov02c10_test_pattern(struct ov02c10 *ov02c10, int pattern)
403 {
404 int ret = 0;
405
406 if (!pattern)
407 return cci_update_bits(ov02c10->regmap, OV02C10_REG_TEST_PATTERN,
408 BIT(7), 0, NULL);
409
410 cci_update_bits(ov02c10->regmap, OV02C10_REG_TEST_PATTERN,
411 0x03, pattern - 1, &ret);
412 cci_update_bits(ov02c10->regmap, OV02C10_REG_TEST_PATTERN,
413 BIT(7), OV02C10_TEST_PATTERN_ENABLE, &ret);
414 return ret;
415 }
416
ov02c10_set_ctrl(struct v4l2_ctrl * ctrl)417 static int ov02c10_set_ctrl(struct v4l2_ctrl *ctrl)
418 {
419 struct ov02c10 *ov02c10 = container_of(ctrl->handler,
420 struct ov02c10, ctrl_handler);
421 struct i2c_client *client = v4l2_get_subdevdata(&ov02c10->sd);
422 const u32 height = supported_modes[0].height;
423 s64 exposure_max;
424 int ret = 0;
425
426 /* Propagate change of current control to all related controls */
427 if (ctrl->id == V4L2_CID_VBLANK) {
428 /* Update max exposure while meeting expected vblanking */
429 exposure_max = height + ctrl->val - OV02C10_EXPOSURE_MAX_MARGIN;
430 __v4l2_ctrl_modify_range(ov02c10->exposure,
431 ov02c10->exposure->minimum,
432 exposure_max, ov02c10->exposure->step,
433 exposure_max);
434 }
435
436 /* V4L2 controls values will be applied only when power is already up */
437 if (!pm_runtime_get_if_in_use(&client->dev))
438 return 0;
439
440 switch (ctrl->id) {
441 case V4L2_CID_ANALOGUE_GAIN:
442 cci_write(ov02c10->regmap, OV02C10_REG_ANALOG_GAIN,
443 ctrl->val << 4, &ret);
444 break;
445
446 case V4L2_CID_DIGITAL_GAIN:
447 cci_write(ov02c10->regmap, OV02C10_REG_DIGITAL_GAIN,
448 ctrl->val << 6, &ret);
449 break;
450
451 case V4L2_CID_EXPOSURE:
452 cci_write(ov02c10->regmap, OV02C10_REG_EXPOSURE,
453 ctrl->val, &ret);
454 break;
455
456 case V4L2_CID_VBLANK:
457 cci_write(ov02c10->regmap, OV02C10_REG_VTS, height + ctrl->val,
458 &ret);
459 break;
460
461 case V4L2_CID_TEST_PATTERN:
462 ret = ov02c10_test_pattern(ov02c10, ctrl->val);
463 break;
464
465 default:
466 ret = -EINVAL;
467 break;
468 }
469
470 pm_runtime_put(&client->dev);
471
472 return ret;
473 }
474
475 static const struct v4l2_ctrl_ops ov02c10_ctrl_ops = {
476 .s_ctrl = ov02c10_set_ctrl,
477 };
478
ov02c10_init_controls(struct ov02c10 * ov02c10)479 static int ov02c10_init_controls(struct ov02c10 *ov02c10)
480 {
481 struct i2c_client *client = v4l2_get_subdevdata(&ov02c10->sd);
482 struct v4l2_ctrl_handler *ctrl_hdlr = &ov02c10->ctrl_handler;
483 const struct ov02c10_mode *mode = &supported_modes[0];
484 u32 vblank_min, vblank_max, vblank_default, vts_def;
485 struct v4l2_fwnode_device_properties props;
486 s64 exposure_max, h_blank, pixel_rate;
487 int ret;
488
489 v4l2_ctrl_handler_init(ctrl_hdlr, 10);
490
491 ov02c10->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr,
492 &ov02c10_ctrl_ops,
493 V4L2_CID_LINK_FREQ,
494 ov02c10->link_freq_index, 0,
495 link_freq_menu_items);
496 if (ov02c10->link_freq)
497 ov02c10->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
498
499 /* MIPI lanes are DDR -> use link-freq * 2 */
500 pixel_rate = div_u64(link_freq_menu_items[ov02c10->link_freq_index] *
501 2 * ov02c10->mipi_lanes, OV02C10_RGB_DEPTH);
502
503 ov02c10->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov02c10_ctrl_ops,
504 V4L2_CID_PIXEL_RATE, 0,
505 pixel_rate, 1, pixel_rate);
506
507 /*
508 * For default multiple min by number of lanes to keep the default
509 * FPS the same indepenedent of the lane count.
510 */
511 vts_def = mode->vts_min * ov02c10->mipi_lanes;
512
513 vblank_min = mode->vts_min - mode->height;
514 vblank_max = OV02C10_VTS_MAX - mode->height;
515 vblank_default = vts_def - mode->height;
516 ov02c10->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov02c10_ctrl_ops,
517 V4L2_CID_VBLANK, vblank_min,
518 vblank_max, 1, vblank_default);
519
520 h_blank = mode->hts - mode->width;
521 ov02c10->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov02c10_ctrl_ops,
522 V4L2_CID_HBLANK, h_blank, h_blank,
523 1, h_blank);
524 if (ov02c10->hblank)
525 ov02c10->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
526
527 v4l2_ctrl_new_std(ctrl_hdlr, &ov02c10_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
528 OV02C10_ANAL_GAIN_MIN, OV02C10_ANAL_GAIN_MAX,
529 OV02C10_ANAL_GAIN_STEP, OV02C10_ANAL_GAIN_DEFAULT);
530 v4l2_ctrl_new_std(ctrl_hdlr, &ov02c10_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
531 OV02C10_DGTL_GAIN_MIN, OV02C10_DGTL_GAIN_MAX,
532 OV02C10_DGTL_GAIN_STEP, OV02C10_DGTL_GAIN_DEFAULT);
533 exposure_max = vts_def - OV02C10_EXPOSURE_MAX_MARGIN;
534 ov02c10->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov02c10_ctrl_ops,
535 V4L2_CID_EXPOSURE,
536 OV02C10_EXPOSURE_MIN,
537 exposure_max,
538 OV02C10_EXPOSURE_STEP,
539 exposure_max);
540 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov02c10_ctrl_ops,
541 V4L2_CID_TEST_PATTERN,
542 ARRAY_SIZE(ov02c10_test_pattern_menu) - 1,
543 0, 0, ov02c10_test_pattern_menu);
544
545 ret = v4l2_fwnode_device_parse(&client->dev, &props);
546 if (ret)
547 return ret;
548
549 v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &ov02c10_ctrl_ops, &props);
550
551 if (ctrl_hdlr->error)
552 return ctrl_hdlr->error;
553
554 ov02c10->sd.ctrl_handler = ctrl_hdlr;
555
556 return 0;
557 }
558
ov02c10_update_pad_format(const struct ov02c10_mode * mode,struct v4l2_mbus_framefmt * fmt)559 static void ov02c10_update_pad_format(const struct ov02c10_mode *mode,
560 struct v4l2_mbus_framefmt *fmt)
561 {
562 fmt->width = mode->width;
563 fmt->height = mode->height;
564 fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
565 fmt->field = V4L2_FIELD_NONE;
566 }
567
ov02c10_enable_streams(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,u32 pad,u64 streams_mask)568 static int ov02c10_enable_streams(struct v4l2_subdev *sd,
569 struct v4l2_subdev_state *state,
570 u32 pad, u64 streams_mask)
571 {
572 const struct ov02c10_mode *mode = &supported_modes[0];
573 struct i2c_client *client = v4l2_get_subdevdata(sd);
574 struct ov02c10 *ov02c10 = to_ov02c10(sd);
575 const struct reg_sequence *reg_sequence;
576 int ret, sequence_length;
577
578 ret = pm_runtime_resume_and_get(&client->dev);
579 if (ret)
580 return ret;
581
582 reg_sequence = mode->reg_sequence;
583 sequence_length = mode->sequence_length;
584 ret = regmap_multi_reg_write(ov02c10->regmap,
585 reg_sequence, sequence_length);
586 if (ret) {
587 dev_err(&client->dev, "failed to set mode\n");
588 goto out;
589 }
590
591 reg_sequence = mode->lane_settings[ov02c10->mipi_lanes - 1];
592 sequence_length = mode->lane_settings_length[ov02c10->mipi_lanes - 1];
593 ret = regmap_multi_reg_write(ov02c10->regmap,
594 reg_sequence, sequence_length);
595 if (ret) {
596 dev_err(&client->dev, "failed to write lane settings\n");
597 goto out;
598 }
599
600 ret = __v4l2_ctrl_handler_setup(ov02c10->sd.ctrl_handler);
601 if (ret)
602 goto out;
603
604 ret = cci_write(ov02c10->regmap, OV02C10_REG_STREAM_CONTROL, 1, NULL);
605 out:
606 if (ret)
607 pm_runtime_put(&client->dev);
608
609 return ret;
610 }
611
ov02c10_disable_streams(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,u32 pad,u64 streams_mask)612 static int ov02c10_disable_streams(struct v4l2_subdev *sd,
613 struct v4l2_subdev_state *state,
614 u32 pad, u64 streams_mask)
615 {
616 struct i2c_client *client = v4l2_get_subdevdata(sd);
617 struct ov02c10 *ov02c10 = to_ov02c10(sd);
618
619 cci_write(ov02c10->regmap, OV02C10_REG_STREAM_CONTROL, 0, NULL);
620 pm_runtime_put(&client->dev);
621
622 return 0;
623 }
624
625 /* This function tries to get power control resources */
ov02c10_get_pm_resources(struct device * dev)626 static int ov02c10_get_pm_resources(struct device *dev)
627 {
628 struct v4l2_subdev *sd = dev_get_drvdata(dev);
629 struct ov02c10 *ov02c10 = to_ov02c10(sd);
630 int i;
631
632 ov02c10->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
633 if (IS_ERR(ov02c10->reset))
634 return dev_err_probe(dev, PTR_ERR(ov02c10->reset),
635 "failed to get reset gpio\n");
636
637 for (i = 0; i < ARRAY_SIZE(ov02c10_supply_names); i++)
638 ov02c10->supplies[i].supply = ov02c10_supply_names[i];
639
640 return devm_regulator_bulk_get(dev, ARRAY_SIZE(ov02c10_supply_names),
641 ov02c10->supplies);
642 }
643
ov02c10_power_off(struct device * dev)644 static int ov02c10_power_off(struct device *dev)
645 {
646 struct v4l2_subdev *sd = dev_get_drvdata(dev);
647 struct ov02c10 *ov02c10 = to_ov02c10(sd);
648
649 gpiod_set_value_cansleep(ov02c10->reset, 1);
650
651 regulator_bulk_disable(ARRAY_SIZE(ov02c10_supply_names),
652 ov02c10->supplies);
653
654 clk_disable_unprepare(ov02c10->img_clk);
655
656 return 0;
657 }
658
ov02c10_power_on(struct device * dev)659 static int ov02c10_power_on(struct device *dev)
660 {
661 struct v4l2_subdev *sd = dev_get_drvdata(dev);
662 struct ov02c10 *ov02c10 = to_ov02c10(sd);
663 int ret;
664
665 ret = clk_prepare_enable(ov02c10->img_clk);
666 if (ret < 0) {
667 dev_err(dev, "failed to enable imaging clock: %d", ret);
668 return ret;
669 }
670
671 ret = regulator_bulk_enable(ARRAY_SIZE(ov02c10_supply_names),
672 ov02c10->supplies);
673 if (ret < 0) {
674 dev_err(dev, "failed to enable regulators: %d", ret);
675 clk_disable_unprepare(ov02c10->img_clk);
676 return ret;
677 }
678
679 if (ov02c10->reset) {
680 /* Assert reset for at least 2ms on back to back off-on */
681 usleep_range(2000, 2200);
682 gpiod_set_value_cansleep(ov02c10->reset, 0);
683 usleep_range(5000, 5100);
684 }
685
686 return 0;
687 }
688
ov02c10_set_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)689 static int ov02c10_set_format(struct v4l2_subdev *sd,
690 struct v4l2_subdev_state *sd_state,
691 struct v4l2_subdev_format *fmt)
692 {
693 const struct ov02c10_mode *mode = &supported_modes[0];
694 struct ov02c10 *ov02c10 = to_ov02c10(sd);
695 s32 vblank_def, h_blank;
696
697 ov02c10_update_pad_format(mode, &fmt->format);
698 *v4l2_subdev_state_get_format(sd_state, fmt->pad) = fmt->format;
699
700 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
701 return 0;
702
703 /* Update limits and set FPS to default */
704 vblank_def = mode->vts_min * ov02c10->mipi_lanes - mode->height;
705 __v4l2_ctrl_modify_range(ov02c10->vblank, mode->vts_min - mode->height,
706 OV02C10_VTS_MAX - mode->height, 1, vblank_def);
707 __v4l2_ctrl_s_ctrl(ov02c10->vblank, vblank_def);
708 h_blank = mode->hts - mode->width;
709 __v4l2_ctrl_modify_range(ov02c10->hblank, h_blank, h_blank, 1, h_blank);
710
711 return 0;
712 }
713
ov02c10_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)714 static int ov02c10_enum_mbus_code(struct v4l2_subdev *sd,
715 struct v4l2_subdev_state *sd_state,
716 struct v4l2_subdev_mbus_code_enum *code)
717 {
718 if (code->index > 0)
719 return -EINVAL;
720
721 code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
722
723 return 0;
724 }
725
ov02c10_enum_frame_size(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_size_enum * fse)726 static int ov02c10_enum_frame_size(struct v4l2_subdev *sd,
727 struct v4l2_subdev_state *sd_state,
728 struct v4l2_subdev_frame_size_enum *fse)
729 {
730 if (fse->index >= ARRAY_SIZE(supported_modes))
731 return -EINVAL;
732
733 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
734 return -EINVAL;
735
736 fse->min_width = supported_modes[fse->index].width;
737 fse->max_width = fse->min_width;
738 fse->min_height = supported_modes[fse->index].height;
739 fse->max_height = fse->min_height;
740
741 return 0;
742 }
743
ov02c10_init_state(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state)744 static int ov02c10_init_state(struct v4l2_subdev *sd,
745 struct v4l2_subdev_state *sd_state)
746 {
747 ov02c10_update_pad_format(&supported_modes[0],
748 v4l2_subdev_state_get_format(sd_state, 0));
749
750 return 0;
751 }
752
753 static const struct v4l2_subdev_video_ops ov02c10_video_ops = {
754 .s_stream = v4l2_subdev_s_stream_helper,
755 };
756
757 static const struct v4l2_subdev_pad_ops ov02c10_pad_ops = {
758 .set_fmt = ov02c10_set_format,
759 .get_fmt = v4l2_subdev_get_fmt,
760 .enum_mbus_code = ov02c10_enum_mbus_code,
761 .enum_frame_size = ov02c10_enum_frame_size,
762 .enable_streams = ov02c10_enable_streams,
763 .disable_streams = ov02c10_disable_streams,
764 };
765
766 static const struct v4l2_subdev_ops ov02c10_subdev_ops = {
767 .video = &ov02c10_video_ops,
768 .pad = &ov02c10_pad_ops,
769 };
770
771 static const struct media_entity_operations ov02c10_subdev_entity_ops = {
772 .link_validate = v4l2_subdev_link_validate,
773 };
774
775 static const struct v4l2_subdev_internal_ops ov02c10_internal_ops = {
776 .init_state = ov02c10_init_state,
777 };
778
ov02c10_identify_module(struct ov02c10 * ov02c10)779 static int ov02c10_identify_module(struct ov02c10 *ov02c10)
780 {
781 struct i2c_client *client = v4l2_get_subdevdata(&ov02c10->sd);
782 u64 chip_id;
783 int ret;
784
785 ret = cci_read(ov02c10->regmap, OV02C10_REG_CHIP_ID, &chip_id, NULL);
786 if (ret)
787 return ret;
788
789 if (chip_id != OV02C10_CHIP_ID) {
790 dev_err(&client->dev, "chip id mismatch: %x!=%llx",
791 OV02C10_CHIP_ID, chip_id);
792 return -ENXIO;
793 }
794
795 return 0;
796 }
797
ov02c10_check_hwcfg(struct device * dev,struct ov02c10 * ov02c10)798 static int ov02c10_check_hwcfg(struct device *dev, struct ov02c10 *ov02c10)
799 {
800 struct v4l2_fwnode_endpoint bus_cfg = {
801 .bus_type = V4L2_MBUS_CSI2_DPHY
802 };
803 struct fwnode_handle *ep, *fwnode = dev_fwnode(dev);
804 unsigned long link_freq_bitmap;
805 u32 mclk;
806 int ret;
807
808 /*
809 * Sometimes the fwnode graph is initialized by the bridge driver,
810 * wait for this.
811 */
812 ep = fwnode_graph_get_endpoint_by_id(fwnode, 0, 0, 0);
813 if (!ep)
814 return dev_err_probe(dev, -EPROBE_DEFER,
815 "waiting for fwnode graph endpoint\n");
816
817 ov02c10->img_clk = devm_clk_get_optional(dev, NULL);
818 if (IS_ERR(ov02c10->img_clk)) {
819 fwnode_handle_put(ep);
820 return dev_err_probe(dev, PTR_ERR(ov02c10->img_clk),
821 "failed to get imaging clock\n");
822 }
823
824 if (ov02c10->img_clk) {
825 mclk = clk_get_rate(ov02c10->img_clk);
826 } else {
827 ret = fwnode_property_read_u32(fwnode, "clock-frequency", &mclk);
828 if (ret) {
829 fwnode_handle_put(ep);
830 return dev_err_probe(dev, ret,
831 "reading clock-frequency property\n");
832 }
833 }
834
835 if (mclk != OV02C10_MCLK) {
836 fwnode_handle_put(ep);
837 return dev_err_probe(dev, -EINVAL,
838 "external clock %u is not supported\n",
839 mclk);
840 }
841
842 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
843 fwnode_handle_put(ep);
844 if (ret)
845 return dev_err_probe(dev, ret, "parsing endpoint failed\n");
846
847 ret = v4l2_link_freq_to_bitmap(dev, bus_cfg.link_frequencies,
848 bus_cfg.nr_of_link_frequencies,
849 link_freq_menu_items,
850 ARRAY_SIZE(link_freq_menu_items),
851 &link_freq_bitmap);
852 if (ret)
853 goto check_hwcfg_error;
854
855 /* v4l2_link_freq_to_bitmap() guarantees at least 1 bit is set */
856 ov02c10->link_freq_index = ffs(link_freq_bitmap) - 1;
857
858 if (bus_cfg.bus.mipi_csi2.num_data_lanes != 1 &&
859 bus_cfg.bus.mipi_csi2.num_data_lanes != 2) {
860 ret = dev_err_probe(dev, -EINVAL,
861 "number of CSI2 data lanes %u is not supported\n",
862 bus_cfg.bus.mipi_csi2.num_data_lanes);
863 goto check_hwcfg_error;
864 }
865
866 ov02c10->mipi_lanes = bus_cfg.bus.mipi_csi2.num_data_lanes;
867
868 check_hwcfg_error:
869 v4l2_fwnode_endpoint_free(&bus_cfg);
870 return ret;
871 }
872
ov02c10_remove(struct i2c_client * client)873 static void ov02c10_remove(struct i2c_client *client)
874 {
875 struct v4l2_subdev *sd = i2c_get_clientdata(client);
876
877 v4l2_async_unregister_subdev(sd);
878 v4l2_subdev_cleanup(sd);
879 media_entity_cleanup(&sd->entity);
880 v4l2_ctrl_handler_free(sd->ctrl_handler);
881 pm_runtime_disable(&client->dev);
882 if (!pm_runtime_status_suspended(&client->dev)) {
883 ov02c10_power_off(&client->dev);
884 pm_runtime_set_suspended(&client->dev);
885 }
886 }
887
ov02c10_probe(struct i2c_client * client)888 static int ov02c10_probe(struct i2c_client *client)
889 {
890 struct ov02c10 *ov02c10;
891 int ret;
892
893 ov02c10 = devm_kzalloc(&client->dev, sizeof(*ov02c10), GFP_KERNEL);
894 if (!ov02c10)
895 return -ENOMEM;
896
897 v4l2_i2c_subdev_init(&ov02c10->sd, client, &ov02c10_subdev_ops);
898
899 /* Check HW config */
900 ret = ov02c10_check_hwcfg(&client->dev, ov02c10);
901 if (ret)
902 return ret;
903
904 ret = ov02c10_get_pm_resources(&client->dev);
905 if (ret)
906 return ret;
907
908 ov02c10->regmap = devm_cci_regmap_init_i2c(client, 16);
909 if (IS_ERR(ov02c10->regmap))
910 return PTR_ERR(ov02c10->regmap);
911
912 ret = ov02c10_power_on(&client->dev);
913 if (ret) {
914 dev_err_probe(&client->dev, ret, "failed to power on\n");
915 return ret;
916 }
917
918 ret = ov02c10_identify_module(ov02c10);
919 if (ret) {
920 dev_err(&client->dev, "failed to find sensor: %d", ret);
921 goto probe_error_power_off;
922 }
923
924 ret = ov02c10_init_controls(ov02c10);
925 if (ret) {
926 dev_err(&client->dev, "failed to init controls: %d", ret);
927 goto probe_error_v4l2_ctrl_handler_free;
928 }
929
930 ov02c10->sd.internal_ops = &ov02c10_internal_ops;
931 ov02c10->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
932 ov02c10->sd.entity.ops = &ov02c10_subdev_entity_ops;
933 ov02c10->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
934 ov02c10->pad.flags = MEDIA_PAD_FL_SOURCE;
935 ret = media_entity_pads_init(&ov02c10->sd.entity, 1, &ov02c10->pad);
936 if (ret) {
937 dev_err(&client->dev, "failed to init entity pads: %d", ret);
938 goto probe_error_v4l2_ctrl_handler_free;
939 }
940
941 ov02c10->sd.state_lock = ov02c10->ctrl_handler.lock;
942 ret = v4l2_subdev_init_finalize(&ov02c10->sd);
943 if (ret < 0) {
944 dev_err(&client->dev, "failed to init subdev: %d", ret);
945 goto probe_error_media_entity_cleanup;
946 }
947
948 pm_runtime_set_active(&client->dev);
949 pm_runtime_enable(&client->dev);
950
951 ret = v4l2_async_register_subdev_sensor(&ov02c10->sd);
952 if (ret < 0) {
953 dev_err(&client->dev, "failed to register V4L2 subdev: %d",
954 ret);
955 goto probe_error_v4l2_subdev_cleanup;
956 }
957
958 pm_runtime_idle(&client->dev);
959 return 0;
960
961 probe_error_v4l2_subdev_cleanup:
962 pm_runtime_disable(&client->dev);
963 pm_runtime_set_suspended(&client->dev);
964 v4l2_subdev_cleanup(&ov02c10->sd);
965
966 probe_error_media_entity_cleanup:
967 media_entity_cleanup(&ov02c10->sd.entity);
968
969 probe_error_v4l2_ctrl_handler_free:
970 v4l2_ctrl_handler_free(ov02c10->sd.ctrl_handler);
971
972 probe_error_power_off:
973 ov02c10_power_off(&client->dev);
974
975 return ret;
976 }
977
978 static DEFINE_RUNTIME_DEV_PM_OPS(ov02c10_pm_ops, ov02c10_power_off,
979 ov02c10_power_on, NULL);
980
981 #ifdef CONFIG_ACPI
982 static const struct acpi_device_id ov02c10_acpi_ids[] = {
983 { "OVTI02C1" },
984 { /* sentinel */ }
985 };
986
987 MODULE_DEVICE_TABLE(acpi, ov02c10_acpi_ids);
988 #endif
989
990 static const struct of_device_id ov02c10_of_match[] = {
991 { .compatible = "ovti,ov02c10" },
992 { /* sentinel */ }
993 };
994 MODULE_DEVICE_TABLE(of, ov02c10_of_match);
995
996 static struct i2c_driver ov02c10_i2c_driver = {
997 .driver = {
998 .name = "ov02c10",
999 .pm = pm_sleep_ptr(&ov02c10_pm_ops),
1000 .acpi_match_table = ACPI_PTR(ov02c10_acpi_ids),
1001 .of_match_table = ov02c10_of_match,
1002 },
1003 .probe = ov02c10_probe,
1004 .remove = ov02c10_remove,
1005 };
1006
1007 module_i2c_driver(ov02c10_i2c_driver);
1008
1009 MODULE_AUTHOR("Hao Yao <hao.yao@intel.com>");
1010 MODULE_AUTHOR("Heimir Thor Sverrisson <heimir.sverrisson@gmail.com>");
1011 MODULE_AUTHOR("Hans de Goede <hansg@kernel.org>");
1012 MODULE_DESCRIPTION("OmniVision OV02C10 sensor driver");
1013 MODULE_LICENSE("GPL");
1014