1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2022 Intel Corporation.
3
4 #include <linux/acpi.h>
5 #include <linux/clk.h>
6 #include <linux/delay.h>
7 #include <linux/gpio/consumer.h>
8 #include <linux/i2c.h>
9 #include <linux/module.h>
10 #include <linux/pm_runtime.h>
11 #include <linux/regmap.h>
12 #include <media/v4l2-cci.h>
13 #include <media/v4l2-ctrls.h>
14 #include <media/v4l2-device.h>
15 #include <media/v4l2-fwnode.h>
16
17 #define OV02C10_LINK_FREQ_400MHZ 400000000ULL
18 #define OV02C10_MCLK 19200000
19 #define OV02C10_RGB_DEPTH 10
20
21 #define OV02C10_REG_CHIP_ID CCI_REG16(0x300a)
22 #define OV02C10_CHIP_ID 0x5602
23
24 #define OV02C10_REG_STREAM_CONTROL CCI_REG8(0x0100)
25
26 #define OV02C10_REG_HTS CCI_REG16(0x380c)
27
28 /* vertical-timings from sensor */
29 #define OV02C10_REG_VTS CCI_REG16(0x380e)
30 #define OV02C10_VTS_MAX 0xffff
31
32 /* Exposure controls from sensor */
33 #define OV02C10_REG_EXPOSURE CCI_REG16(0x3501)
34 #define OV02C10_EXPOSURE_MIN 4
35 #define OV02C10_EXPOSURE_MAX_MARGIN 8
36 #define OV02C10_EXPOSURE_STEP 1
37
38 /* Analog gain controls from sensor */
39 #define OV02C10_REG_ANALOG_GAIN CCI_REG16(0x3508)
40 #define OV02C10_ANAL_GAIN_MIN 0x10
41 #define OV02C10_ANAL_GAIN_MAX 0xf8
42 #define OV02C10_ANAL_GAIN_STEP 1
43 #define OV02C10_ANAL_GAIN_DEFAULT 0x10
44
45 /* Digital gain controls from sensor */
46 #define OV02C10_REG_DIGITAL_GAIN CCI_REG24(0x350a)
47 #define OV02C10_DGTL_GAIN_MIN 0x0400
48 #define OV02C10_DGTL_GAIN_MAX 0x3fff
49 #define OV02C10_DGTL_GAIN_STEP 1
50 #define OV02C10_DGTL_GAIN_DEFAULT 0x0400
51
52 /* Rotate */
53 #define OV02C10_ROTATE_CONTROL CCI_REG8(0x3820)
54 #define OV02C10_ISP_X_WIN_CONTROL CCI_REG16(0x3810)
55 #define OV02C10_ISP_Y_WIN_CONTROL CCI_REG16(0x3812)
56 #define OV02C10_CONFIG_ROTATE 0x18
57
58 /* Test Pattern Control */
59 #define OV02C10_REG_TEST_PATTERN CCI_REG8(0x4503)
60 #define OV02C10_TEST_PATTERN_ENABLE BIT(7)
61
62 struct ov02c10_mode {
63 /* Frame width in pixels */
64 u32 width;
65
66 /* Frame height in pixels */
67 u32 height;
68
69 /* Horizontal timining size */
70 u32 hts;
71
72 /* Min vertical timining size */
73 u32 vts_min;
74
75 /* Sensor register settings for this resolution */
76 const struct reg_sequence *reg_sequence;
77 const int sequence_length;
78 /* Sensor register settings for 1 or 2 lane config */
79 const struct reg_sequence *lane_settings[2];
80 const int lane_settings_length[2];
81 };
82
83 static const struct reg_sequence sensor_1928x1092_30fps_setting[] = {
84 {0x0301, 0x08},
85 {0x0303, 0x06},
86 {0x0304, 0x01},
87 {0x0305, 0xe0},
88 {0x0313, 0x40},
89 {0x031c, 0x4f},
90 {0x3020, 0x97},
91 {0x3022, 0x01},
92 {0x3026, 0xb4},
93 {0x303b, 0x00},
94 {0x303c, 0x4f},
95 {0x303d, 0xe6},
96 {0x303e, 0x00},
97 {0x303f, 0x03},
98 {0x3021, 0x23},
99 {0x3501, 0x04},
100 {0x3502, 0x6c},
101 {0x3504, 0x0c},
102 {0x3507, 0x00},
103 {0x3508, 0x08},
104 {0x3509, 0x00},
105 {0x350a, 0x01},
106 {0x350b, 0x00},
107 {0x350c, 0x41},
108 {0x3600, 0x84},
109 {0x3603, 0x08},
110 {0x3610, 0x57},
111 {0x3611, 0x1b},
112 {0x3613, 0x78},
113 {0x3623, 0x00},
114 {0x3632, 0xa0},
115 {0x3642, 0xe8},
116 {0x364c, 0x70},
117 {0x365f, 0x0f},
118 {0x3708, 0x30},
119 {0x3714, 0x24},
120 {0x3725, 0x02},
121 {0x3737, 0x08},
122 {0x3739, 0x28},
123 {0x3749, 0x32},
124 {0x374a, 0x32},
125 {0x374b, 0x32},
126 {0x374c, 0x32},
127 {0x374d, 0x81},
128 {0x374e, 0x81},
129 {0x374f, 0x81},
130 {0x3752, 0x36},
131 {0x3753, 0x36},
132 {0x3754, 0x36},
133 {0x3761, 0x00},
134 {0x376c, 0x81},
135 {0x3774, 0x18},
136 {0x3776, 0x08},
137 {0x377c, 0x81},
138 {0x377d, 0x81},
139 {0x377e, 0x81},
140 {0x37a0, 0x44},
141 {0x37a6, 0x44},
142 {0x37aa, 0x0d},
143 {0x37ae, 0x00},
144 {0x37cb, 0x03},
145 {0x37cc, 0x01},
146 {0x37d8, 0x02},
147 {0x37d9, 0x10},
148 {0x37e1, 0x10},
149 {0x37e2, 0x18},
150 {0x37e3, 0x08},
151 {0x37e4, 0x08},
152 {0x37e5, 0x02},
153 {0x37e6, 0x08},
154
155 /* 1928x1092 */
156 {0x3800, 0x00},
157 {0x3801, 0x00},
158 {0x3802, 0x00},
159 {0x3803, 0x00},
160 {0x3804, 0x07},
161 {0x3805, 0x8f},
162 {0x3806, 0x04},
163 {0x3807, 0x47},
164 {0x3808, 0x07},
165 {0x3809, 0x88},
166 {0x380a, 0x04},
167 {0x380b, 0x44},
168 {0x3810, 0x00},
169 {0x3811, 0x02},
170 {0x3812, 0x00},
171 {0x3813, 0x02},
172 {0x3814, 0x01},
173 {0x3815, 0x01},
174 {0x3816, 0x01},
175 {0x3817, 0x01},
176
177 {0x3820, 0xb0},
178 {0x3821, 0x00},
179 {0x3822, 0x80},
180 {0x3823, 0x08},
181 {0x3824, 0x00},
182 {0x3825, 0x20},
183 {0x3826, 0x00},
184 {0x3827, 0x08},
185 {0x382a, 0x00},
186 {0x382b, 0x08},
187 {0x382d, 0x00},
188 {0x382e, 0x00},
189 {0x382f, 0x23},
190 {0x3834, 0x00},
191 {0x3839, 0x00},
192 {0x383a, 0xd1},
193 {0x383e, 0x03},
194 {0x393d, 0x29},
195 {0x393f, 0x6e},
196 {0x394b, 0x06},
197 {0x394c, 0x06},
198 {0x394d, 0x08},
199 {0x394f, 0x01},
200 {0x3950, 0x01},
201 {0x3951, 0x01},
202 {0x3952, 0x01},
203 {0x3953, 0x01},
204 {0x3954, 0x01},
205 {0x3955, 0x01},
206 {0x3956, 0x01},
207 {0x3957, 0x0e},
208 {0x3958, 0x08},
209 {0x3959, 0x08},
210 {0x395a, 0x08},
211 {0x395b, 0x13},
212 {0x395c, 0x09},
213 {0x395d, 0x05},
214 {0x395e, 0x02},
215 {0x395f, 0x00},
216 {0x395f, 0x00},
217 {0x3960, 0x00},
218 {0x3961, 0x00},
219 {0x3962, 0x00},
220 {0x3963, 0x00},
221 {0x3964, 0x00},
222 {0x3965, 0x00},
223 {0x3966, 0x00},
224 {0x3967, 0x00},
225 {0x3968, 0x01},
226 {0x3969, 0x01},
227 {0x396a, 0x01},
228 {0x396b, 0x01},
229 {0x396c, 0x10},
230 {0x396d, 0xf0},
231 {0x396e, 0x11},
232 {0x396f, 0x00},
233 {0x3970, 0x37},
234 {0x3971, 0x37},
235 {0x3972, 0x37},
236 {0x3973, 0x37},
237 {0x3974, 0x00},
238 {0x3975, 0x3c},
239 {0x3976, 0x3c},
240 {0x3977, 0x3c},
241 {0x3978, 0x3c},
242 {0x3c00, 0x0f},
243 {0x3c20, 0x01},
244 {0x3c21, 0x08},
245 {0x3f00, 0x8b},
246 {0x3f02, 0x0f},
247 {0x4000, 0xc3},
248 {0x4001, 0xe0},
249 {0x4002, 0x00},
250 {0x4003, 0x40},
251 {0x4008, 0x04},
252 {0x4009, 0x23},
253 {0x400a, 0x04},
254 {0x400b, 0x01},
255 {0x4077, 0x06},
256 {0x4078, 0x00},
257 {0x4079, 0x1a},
258 {0x407a, 0x7f},
259 {0x407b, 0x01},
260 {0x4080, 0x03},
261 {0x4081, 0x84},
262 {0x4308, 0x03},
263 {0x4309, 0xff},
264 {0x430d, 0x00},
265 {0x4806, 0x00},
266 {0x4813, 0x00},
267 {0x4837, 0x10},
268 {0x4857, 0x05},
269 {0x4500, 0x07},
270 {0x4501, 0x00},
271 {0x4503, 0x00},
272 {0x450a, 0x04},
273 {0x450e, 0x00},
274 {0x450f, 0x00},
275 {0x4900, 0x00},
276 {0x4901, 0x00},
277 {0x4902, 0x01},
278 {0x5001, 0x50},
279 {0x5006, 0x00},
280 {0x5080, 0x40},
281 {0x5181, 0x2b},
282 {0x5202, 0xa3},
283 {0x5206, 0x01},
284 {0x5207, 0x00},
285 {0x520a, 0x01},
286 {0x520b, 0x00},
287 {0x365d, 0x00},
288 {0x4815, 0x40},
289 {0x4816, 0x12},
290 {0x4f00, 0x01},
291 };
292
293 static const struct reg_sequence sensor_1928x1092_30fps_1lane_setting[] = {
294 {0x301b, 0xd2},
295 {0x3027, 0xe1},
296 {0x380c, 0x08},
297 {0x380d, 0xe8},
298 {0x380e, 0x04},
299 {0x380f, 0x8c},
300 {0x394e, 0x0b},
301 {0x4800, 0x24},
302 {0x5000, 0xf5},
303 /* plls */
304 {0x0303, 0x05},
305 {0x0305, 0x90},
306 {0x0316, 0x90},
307 {0x3016, 0x12},
308 };
309
310 static const struct reg_sequence sensor_1928x1092_30fps_2lane_setting[] = {
311 {0x301b, 0xf0},
312 {0x3027, 0xf1},
313 {0x380c, 0x04},
314 {0x380d, 0x74},
315 {0x380e, 0x09},
316 {0x380f, 0x18},
317 {0x394e, 0x0a},
318 {0x4041, 0x20},
319 {0x4884, 0x04},
320 {0x4800, 0x64},
321 {0x4d00, 0x03},
322 {0x4d01, 0xd8},
323 {0x4d02, 0xba},
324 {0x4d03, 0xa0},
325 {0x4d04, 0xb7},
326 {0x4d05, 0x34},
327 {0x4d0d, 0x00},
328 {0x5000, 0xfd},
329 {0x481f, 0x30},
330 /* plls */
331 {0x0303, 0x05},
332 {0x0305, 0x90},
333 {0x0316, 0x90},
334 {0x3016, 0x32},
335 };
336
337 static const char * const ov02c10_test_pattern_menu[] = {
338 "Disabled",
339 "Color Bar",
340 "Top-Bottom Darker Color Bar",
341 "Right-Left Darker Color Bar",
342 "Color Bar type 4",
343 };
344
345 static const s64 link_freq_menu_items[] = {
346 OV02C10_LINK_FREQ_400MHZ,
347 };
348
349 static const struct ov02c10_mode supported_modes[] = {
350 {
351 .width = 1928,
352 .height = 1092,
353 .hts = 2280,
354 .vts_min = 1164,
355 .reg_sequence = sensor_1928x1092_30fps_setting,
356 .sequence_length = ARRAY_SIZE(sensor_1928x1092_30fps_setting),
357 .lane_settings = {
358 sensor_1928x1092_30fps_1lane_setting,
359 sensor_1928x1092_30fps_2lane_setting
360 },
361 .lane_settings_length = {
362 ARRAY_SIZE(sensor_1928x1092_30fps_1lane_setting),
363 ARRAY_SIZE(sensor_1928x1092_30fps_2lane_setting),
364 },
365 },
366 };
367
368 static const char * const ov02c10_supply_names[] = {
369 "dovdd", /* Digital I/O power */
370 "avdd", /* Analog power */
371 "dvdd", /* Digital core power */
372 };
373
374 struct ov02c10 {
375 struct device *dev;
376
377 struct v4l2_subdev sd;
378 struct media_pad pad;
379 struct v4l2_ctrl_handler ctrl_handler;
380 struct regmap *regmap;
381
382 /* V4L2 Controls */
383 struct v4l2_ctrl *link_freq;
384 struct v4l2_ctrl *pixel_rate;
385 struct v4l2_ctrl *vblank;
386 struct v4l2_ctrl *hblank;
387 struct v4l2_ctrl *exposure;
388
389 struct clk *img_clk;
390 struct gpio_desc *reset;
391 struct regulator_bulk_data supplies[ARRAY_SIZE(ov02c10_supply_names)];
392
393 /* MIPI lane info */
394 u32 link_freq_index;
395 u8 mipi_lanes;
396 };
397
to_ov02c10(struct v4l2_subdev * subdev)398 static inline struct ov02c10 *to_ov02c10(struct v4l2_subdev *subdev)
399 {
400 return container_of(subdev, struct ov02c10, sd);
401 }
402
ov02c10_test_pattern(struct ov02c10 * ov02c10,int pattern)403 static int ov02c10_test_pattern(struct ov02c10 *ov02c10, int pattern)
404 {
405 int ret = 0;
406
407 if (!pattern)
408 return cci_update_bits(ov02c10->regmap, OV02C10_REG_TEST_PATTERN,
409 BIT(7), 0, NULL);
410
411 cci_update_bits(ov02c10->regmap, OV02C10_REG_TEST_PATTERN,
412 0x03, pattern - 1, &ret);
413 cci_update_bits(ov02c10->regmap, OV02C10_REG_TEST_PATTERN,
414 BIT(7), OV02C10_TEST_PATTERN_ENABLE, &ret);
415 return ret;
416 }
417
ov02c10_set_ctrl(struct v4l2_ctrl * ctrl)418 static int ov02c10_set_ctrl(struct v4l2_ctrl *ctrl)
419 {
420 struct ov02c10 *ov02c10 = container_of(ctrl->handler,
421 struct ov02c10, ctrl_handler);
422 const u32 height = supported_modes[0].height;
423 s64 exposure_max;
424 int ret = 0;
425
426 /* Propagate change of current control to all related controls */
427 if (ctrl->id == V4L2_CID_VBLANK) {
428 /* Update max exposure while meeting expected vblanking */
429 exposure_max = height + ctrl->val - OV02C10_EXPOSURE_MAX_MARGIN;
430 __v4l2_ctrl_modify_range(ov02c10->exposure,
431 ov02c10->exposure->minimum,
432 exposure_max, ov02c10->exposure->step,
433 exposure_max);
434 }
435
436 /* V4L2 controls values will be applied only when power is already up */
437 if (!pm_runtime_get_if_in_use(ov02c10->dev))
438 return 0;
439
440 switch (ctrl->id) {
441 case V4L2_CID_ANALOGUE_GAIN:
442 cci_write(ov02c10->regmap, OV02C10_REG_ANALOG_GAIN,
443 ctrl->val << 4, &ret);
444 break;
445
446 case V4L2_CID_DIGITAL_GAIN:
447 cci_write(ov02c10->regmap, OV02C10_REG_DIGITAL_GAIN,
448 ctrl->val << 6, &ret);
449 break;
450
451 case V4L2_CID_EXPOSURE:
452 cci_write(ov02c10->regmap, OV02C10_REG_EXPOSURE,
453 ctrl->val, &ret);
454 break;
455
456 case V4L2_CID_VBLANK:
457 cci_write(ov02c10->regmap, OV02C10_REG_VTS, height + ctrl->val,
458 &ret);
459 break;
460
461 case V4L2_CID_TEST_PATTERN:
462 ret = ov02c10_test_pattern(ov02c10, ctrl->val);
463 break;
464
465 default:
466 ret = -EINVAL;
467 break;
468 }
469
470 pm_runtime_put(ov02c10->dev);
471
472 return ret;
473 }
474
475 static const struct v4l2_ctrl_ops ov02c10_ctrl_ops = {
476 .s_ctrl = ov02c10_set_ctrl,
477 };
478
ov02c10_init_controls(struct ov02c10 * ov02c10)479 static int ov02c10_init_controls(struct ov02c10 *ov02c10)
480 {
481 struct v4l2_ctrl_handler *ctrl_hdlr = &ov02c10->ctrl_handler;
482 const struct ov02c10_mode *mode = &supported_modes[0];
483 u32 vblank_min, vblank_max, vblank_default, vts_def;
484 struct v4l2_fwnode_device_properties props;
485 s64 exposure_max, h_blank, pixel_rate;
486 int ret;
487
488 v4l2_ctrl_handler_init(ctrl_hdlr, 10);
489
490 ov02c10->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr,
491 &ov02c10_ctrl_ops,
492 V4L2_CID_LINK_FREQ,
493 ov02c10->link_freq_index, 0,
494 link_freq_menu_items);
495 if (ov02c10->link_freq)
496 ov02c10->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
497
498 /* MIPI lanes are DDR -> use link-freq * 2 */
499 pixel_rate = div_u64(link_freq_menu_items[ov02c10->link_freq_index] *
500 2 * ov02c10->mipi_lanes, OV02C10_RGB_DEPTH);
501
502 ov02c10->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov02c10_ctrl_ops,
503 V4L2_CID_PIXEL_RATE, 0,
504 pixel_rate, 1, pixel_rate);
505
506 /*
507 * For default multiple min by number of lanes to keep the default
508 * FPS the same indepenedent of the lane count.
509 */
510 vts_def = mode->vts_min * ov02c10->mipi_lanes;
511
512 vblank_min = mode->vts_min - mode->height;
513 vblank_max = OV02C10_VTS_MAX - mode->height;
514 vblank_default = vts_def - mode->height;
515 ov02c10->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov02c10_ctrl_ops,
516 V4L2_CID_VBLANK, vblank_min,
517 vblank_max, 1, vblank_default);
518
519 h_blank = mode->hts - mode->width;
520 ov02c10->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov02c10_ctrl_ops,
521 V4L2_CID_HBLANK, h_blank, h_blank,
522 1, h_blank);
523 if (ov02c10->hblank)
524 ov02c10->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
525
526 v4l2_ctrl_new_std(ctrl_hdlr, &ov02c10_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
527 OV02C10_ANAL_GAIN_MIN, OV02C10_ANAL_GAIN_MAX,
528 OV02C10_ANAL_GAIN_STEP, OV02C10_ANAL_GAIN_DEFAULT);
529 v4l2_ctrl_new_std(ctrl_hdlr, &ov02c10_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
530 OV02C10_DGTL_GAIN_MIN, OV02C10_DGTL_GAIN_MAX,
531 OV02C10_DGTL_GAIN_STEP, OV02C10_DGTL_GAIN_DEFAULT);
532 exposure_max = vts_def - OV02C10_EXPOSURE_MAX_MARGIN;
533 ov02c10->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov02c10_ctrl_ops,
534 V4L2_CID_EXPOSURE,
535 OV02C10_EXPOSURE_MIN,
536 exposure_max,
537 OV02C10_EXPOSURE_STEP,
538 exposure_max);
539 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov02c10_ctrl_ops,
540 V4L2_CID_TEST_PATTERN,
541 ARRAY_SIZE(ov02c10_test_pattern_menu) - 1,
542 0, 0, ov02c10_test_pattern_menu);
543
544 ret = v4l2_fwnode_device_parse(ov02c10->dev, &props);
545 if (ret)
546 return ret;
547
548 v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &ov02c10_ctrl_ops, &props);
549
550 if (ctrl_hdlr->error)
551 return ctrl_hdlr->error;
552
553 ov02c10->sd.ctrl_handler = ctrl_hdlr;
554
555 return 0;
556 }
557
ov02c10_update_pad_format(const struct ov02c10_mode * mode,struct v4l2_mbus_framefmt * fmt)558 static void ov02c10_update_pad_format(const struct ov02c10_mode *mode,
559 struct v4l2_mbus_framefmt *fmt)
560 {
561 fmt->width = mode->width;
562 fmt->height = mode->height;
563 fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
564 fmt->field = V4L2_FIELD_NONE;
565 }
566
ov02c10_enable_streams(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,u32 pad,u64 streams_mask)567 static int ov02c10_enable_streams(struct v4l2_subdev *sd,
568 struct v4l2_subdev_state *state,
569 u32 pad, u64 streams_mask)
570 {
571 const struct ov02c10_mode *mode = &supported_modes[0];
572 struct ov02c10 *ov02c10 = to_ov02c10(sd);
573 const struct reg_sequence *reg_sequence;
574 int ret, sequence_length;
575
576 ret = pm_runtime_resume_and_get(ov02c10->dev);
577 if (ret)
578 return ret;
579
580 reg_sequence = mode->reg_sequence;
581 sequence_length = mode->sequence_length;
582 ret = regmap_multi_reg_write(ov02c10->regmap,
583 reg_sequence, sequence_length);
584 if (ret) {
585 dev_err(ov02c10->dev, "failed to set mode\n");
586 goto out;
587 }
588
589 reg_sequence = mode->lane_settings[ov02c10->mipi_lanes - 1];
590 sequence_length = mode->lane_settings_length[ov02c10->mipi_lanes - 1];
591 ret = regmap_multi_reg_write(ov02c10->regmap,
592 reg_sequence, sequence_length);
593 if (ret) {
594 dev_err(ov02c10->dev, "failed to write lane settings\n");
595 goto out;
596 }
597
598 ret = __v4l2_ctrl_handler_setup(ov02c10->sd.ctrl_handler);
599 if (ret)
600 goto out;
601
602 ret = cci_write(ov02c10->regmap, OV02C10_REG_STREAM_CONTROL, 1, NULL);
603 out:
604 if (ret)
605 pm_runtime_put(ov02c10->dev);
606
607 return ret;
608 }
609
ov02c10_disable_streams(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,u32 pad,u64 streams_mask)610 static int ov02c10_disable_streams(struct v4l2_subdev *sd,
611 struct v4l2_subdev_state *state,
612 u32 pad, u64 streams_mask)
613 {
614 struct ov02c10 *ov02c10 = to_ov02c10(sd);
615
616 cci_write(ov02c10->regmap, OV02C10_REG_STREAM_CONTROL, 0, NULL);
617 pm_runtime_put(ov02c10->dev);
618
619 return 0;
620 }
621
622 /* This function tries to get power control resources */
ov02c10_get_pm_resources(struct device * dev)623 static int ov02c10_get_pm_resources(struct device *dev)
624 {
625 struct v4l2_subdev *sd = dev_get_drvdata(dev);
626 struct ov02c10 *ov02c10 = to_ov02c10(sd);
627 int i;
628
629 ov02c10->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
630 if (IS_ERR(ov02c10->reset))
631 return dev_err_probe(dev, PTR_ERR(ov02c10->reset),
632 "failed to get reset gpio\n");
633
634 for (i = 0; i < ARRAY_SIZE(ov02c10_supply_names); i++)
635 ov02c10->supplies[i].supply = ov02c10_supply_names[i];
636
637 return devm_regulator_bulk_get(dev, ARRAY_SIZE(ov02c10_supply_names),
638 ov02c10->supplies);
639 }
640
ov02c10_power_off(struct device * dev)641 static int ov02c10_power_off(struct device *dev)
642 {
643 struct v4l2_subdev *sd = dev_get_drvdata(dev);
644 struct ov02c10 *ov02c10 = to_ov02c10(sd);
645
646 gpiod_set_value_cansleep(ov02c10->reset, 1);
647
648 regulator_bulk_disable(ARRAY_SIZE(ov02c10_supply_names),
649 ov02c10->supplies);
650
651 clk_disable_unprepare(ov02c10->img_clk);
652
653 return 0;
654 }
655
ov02c10_power_on(struct device * dev)656 static int ov02c10_power_on(struct device *dev)
657 {
658 struct v4l2_subdev *sd = dev_get_drvdata(dev);
659 struct ov02c10 *ov02c10 = to_ov02c10(sd);
660 int ret;
661
662 ret = clk_prepare_enable(ov02c10->img_clk);
663 if (ret < 0) {
664 dev_err(dev, "failed to enable imaging clock: %d", ret);
665 return ret;
666 }
667
668 ret = regulator_bulk_enable(ARRAY_SIZE(ov02c10_supply_names),
669 ov02c10->supplies);
670 if (ret < 0) {
671 dev_err(dev, "failed to enable regulators: %d", ret);
672 clk_disable_unprepare(ov02c10->img_clk);
673 return ret;
674 }
675
676 if (ov02c10->reset) {
677 /* Assert reset for at least 2ms on back to back off-on */
678 usleep_range(2000, 2200);
679 gpiod_set_value_cansleep(ov02c10->reset, 0);
680 usleep_range(5000, 5100);
681 }
682
683 return 0;
684 }
685
ov02c10_set_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)686 static int ov02c10_set_format(struct v4l2_subdev *sd,
687 struct v4l2_subdev_state *sd_state,
688 struct v4l2_subdev_format *fmt)
689 {
690 const struct ov02c10_mode *mode = &supported_modes[0];
691 struct ov02c10 *ov02c10 = to_ov02c10(sd);
692 s32 vblank_def, h_blank;
693
694 ov02c10_update_pad_format(mode, &fmt->format);
695 *v4l2_subdev_state_get_format(sd_state, fmt->pad) = fmt->format;
696
697 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
698 return 0;
699
700 /* Update limits and set FPS to default */
701 vblank_def = mode->vts_min * ov02c10->mipi_lanes - mode->height;
702 __v4l2_ctrl_modify_range(ov02c10->vblank, mode->vts_min - mode->height,
703 OV02C10_VTS_MAX - mode->height, 1, vblank_def);
704 __v4l2_ctrl_s_ctrl(ov02c10->vblank, vblank_def);
705 h_blank = mode->hts - mode->width;
706 __v4l2_ctrl_modify_range(ov02c10->hblank, h_blank, h_blank, 1, h_blank);
707
708 return 0;
709 }
710
ov02c10_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)711 static int ov02c10_enum_mbus_code(struct v4l2_subdev *sd,
712 struct v4l2_subdev_state *sd_state,
713 struct v4l2_subdev_mbus_code_enum *code)
714 {
715 if (code->index > 0)
716 return -EINVAL;
717
718 code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
719
720 return 0;
721 }
722
ov02c10_enum_frame_size(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_size_enum * fse)723 static int ov02c10_enum_frame_size(struct v4l2_subdev *sd,
724 struct v4l2_subdev_state *sd_state,
725 struct v4l2_subdev_frame_size_enum *fse)
726 {
727 if (fse->index >= ARRAY_SIZE(supported_modes))
728 return -EINVAL;
729
730 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
731 return -EINVAL;
732
733 fse->min_width = supported_modes[fse->index].width;
734 fse->max_width = fse->min_width;
735 fse->min_height = supported_modes[fse->index].height;
736 fse->max_height = fse->min_height;
737
738 return 0;
739 }
740
ov02c10_init_state(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state)741 static int ov02c10_init_state(struct v4l2_subdev *sd,
742 struct v4l2_subdev_state *sd_state)
743 {
744 ov02c10_update_pad_format(&supported_modes[0],
745 v4l2_subdev_state_get_format(sd_state, 0));
746
747 return 0;
748 }
749
750 static const struct v4l2_subdev_video_ops ov02c10_video_ops = {
751 .s_stream = v4l2_subdev_s_stream_helper,
752 };
753
754 static const struct v4l2_subdev_pad_ops ov02c10_pad_ops = {
755 .set_fmt = ov02c10_set_format,
756 .get_fmt = v4l2_subdev_get_fmt,
757 .enum_mbus_code = ov02c10_enum_mbus_code,
758 .enum_frame_size = ov02c10_enum_frame_size,
759 .enable_streams = ov02c10_enable_streams,
760 .disable_streams = ov02c10_disable_streams,
761 };
762
763 static const struct v4l2_subdev_ops ov02c10_subdev_ops = {
764 .video = &ov02c10_video_ops,
765 .pad = &ov02c10_pad_ops,
766 };
767
768 static const struct media_entity_operations ov02c10_subdev_entity_ops = {
769 .link_validate = v4l2_subdev_link_validate,
770 };
771
772 static const struct v4l2_subdev_internal_ops ov02c10_internal_ops = {
773 .init_state = ov02c10_init_state,
774 };
775
ov02c10_identify_module(struct ov02c10 * ov02c10)776 static int ov02c10_identify_module(struct ov02c10 *ov02c10)
777 {
778 u64 chip_id;
779 int ret;
780
781 ret = cci_read(ov02c10->regmap, OV02C10_REG_CHIP_ID, &chip_id, NULL);
782 if (ret)
783 return ret;
784
785 if (chip_id != OV02C10_CHIP_ID) {
786 dev_err(ov02c10->dev, "chip id mismatch: %x!=%llx",
787 OV02C10_CHIP_ID, chip_id);
788 return -ENXIO;
789 }
790
791 return 0;
792 }
793
ov02c10_check_hwcfg(struct ov02c10 * ov02c10)794 static int ov02c10_check_hwcfg(struct ov02c10 *ov02c10)
795 {
796 struct v4l2_fwnode_endpoint bus_cfg = {
797 .bus_type = V4L2_MBUS_CSI2_DPHY
798 };
799 struct device *dev = ov02c10->dev;
800 struct fwnode_handle *ep, *fwnode = dev_fwnode(dev);
801 unsigned long link_freq_bitmap;
802 int ret;
803
804 /*
805 * Sometimes the fwnode graph is initialized by the bridge driver,
806 * wait for this.
807 */
808 ep = fwnode_graph_get_endpoint_by_id(fwnode, 0, 0, 0);
809 if (!ep)
810 return dev_err_probe(dev, -EPROBE_DEFER,
811 "waiting for fwnode graph endpoint\n");
812
813 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
814 fwnode_handle_put(ep);
815 if (ret)
816 return dev_err_probe(dev, ret, "parsing endpoint failed\n");
817
818 ret = v4l2_link_freq_to_bitmap(dev, bus_cfg.link_frequencies,
819 bus_cfg.nr_of_link_frequencies,
820 link_freq_menu_items,
821 ARRAY_SIZE(link_freq_menu_items),
822 &link_freq_bitmap);
823 if (ret)
824 goto check_hwcfg_error;
825
826 /* v4l2_link_freq_to_bitmap() guarantees at least 1 bit is set */
827 ov02c10->link_freq_index = ffs(link_freq_bitmap) - 1;
828
829 if (bus_cfg.bus.mipi_csi2.num_data_lanes != 1 &&
830 bus_cfg.bus.mipi_csi2.num_data_lanes != 2) {
831 ret = dev_err_probe(dev, -EINVAL,
832 "number of CSI2 data lanes %u is not supported\n",
833 bus_cfg.bus.mipi_csi2.num_data_lanes);
834 goto check_hwcfg_error;
835 }
836
837 ov02c10->mipi_lanes = bus_cfg.bus.mipi_csi2.num_data_lanes;
838
839 check_hwcfg_error:
840 v4l2_fwnode_endpoint_free(&bus_cfg);
841 return ret;
842 }
843
ov02c10_remove(struct i2c_client * client)844 static void ov02c10_remove(struct i2c_client *client)
845 {
846 struct v4l2_subdev *sd = i2c_get_clientdata(client);
847 struct ov02c10 *ov02c10 = to_ov02c10(sd);
848
849 v4l2_async_unregister_subdev(sd);
850 v4l2_subdev_cleanup(sd);
851 media_entity_cleanup(&sd->entity);
852 v4l2_ctrl_handler_free(sd->ctrl_handler);
853 pm_runtime_disable(ov02c10->dev);
854 if (!pm_runtime_status_suspended(ov02c10->dev)) {
855 ov02c10_power_off(ov02c10->dev);
856 pm_runtime_set_suspended(ov02c10->dev);
857 }
858 }
859
ov02c10_probe(struct i2c_client * client)860 static int ov02c10_probe(struct i2c_client *client)
861 {
862 struct ov02c10 *ov02c10;
863 unsigned long freq;
864 int ret;
865
866 ov02c10 = devm_kzalloc(&client->dev, sizeof(*ov02c10), GFP_KERNEL);
867 if (!ov02c10)
868 return -ENOMEM;
869
870 ov02c10->dev = &client->dev;
871
872 ov02c10->img_clk = devm_v4l2_sensor_clk_get(ov02c10->dev, NULL);
873 if (IS_ERR(ov02c10->img_clk))
874 return dev_err_probe(ov02c10->dev, PTR_ERR(ov02c10->img_clk),
875 "failed to get imaging clock\n");
876
877 freq = clk_get_rate(ov02c10->img_clk);
878 if (freq != OV02C10_MCLK)
879 return dev_err_probe(ov02c10->dev, -EINVAL,
880 "external clock %lu is not supported",
881 freq);
882
883 v4l2_i2c_subdev_init(&ov02c10->sd, client, &ov02c10_subdev_ops);
884
885 /* Check HW config */
886 ret = ov02c10_check_hwcfg(ov02c10);
887 if (ret)
888 return ret;
889
890 ret = ov02c10_get_pm_resources(ov02c10->dev);
891 if (ret)
892 return ret;
893
894 ov02c10->regmap = devm_cci_regmap_init_i2c(client, 16);
895 if (IS_ERR(ov02c10->regmap))
896 return PTR_ERR(ov02c10->regmap);
897
898 ret = ov02c10_power_on(ov02c10->dev);
899 if (ret) {
900 dev_err_probe(ov02c10->dev, ret, "failed to power on\n");
901 return ret;
902 }
903
904 ret = ov02c10_identify_module(ov02c10);
905 if (ret) {
906 dev_err(ov02c10->dev, "failed to find sensor: %d", ret);
907 goto probe_error_power_off;
908 }
909
910 ret = ov02c10_init_controls(ov02c10);
911 if (ret) {
912 dev_err(ov02c10->dev, "failed to init controls: %d", ret);
913 goto probe_error_v4l2_ctrl_handler_free;
914 }
915
916 ov02c10->sd.internal_ops = &ov02c10_internal_ops;
917 ov02c10->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
918 ov02c10->sd.entity.ops = &ov02c10_subdev_entity_ops;
919 ov02c10->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
920 ov02c10->pad.flags = MEDIA_PAD_FL_SOURCE;
921 ret = media_entity_pads_init(&ov02c10->sd.entity, 1, &ov02c10->pad);
922 if (ret) {
923 dev_err(ov02c10->dev, "failed to init entity pads: %d", ret);
924 goto probe_error_v4l2_ctrl_handler_free;
925 }
926
927 ov02c10->sd.state_lock = ov02c10->ctrl_handler.lock;
928 ret = v4l2_subdev_init_finalize(&ov02c10->sd);
929 if (ret < 0) {
930 dev_err(ov02c10->dev, "failed to init subdev: %d", ret);
931 goto probe_error_media_entity_cleanup;
932 }
933
934 pm_runtime_set_active(ov02c10->dev);
935 pm_runtime_enable(ov02c10->dev);
936
937 ret = v4l2_async_register_subdev_sensor(&ov02c10->sd);
938 if (ret < 0) {
939 dev_err(ov02c10->dev, "failed to register V4L2 subdev: %d",
940 ret);
941 goto probe_error_v4l2_subdev_cleanup;
942 }
943
944 pm_runtime_idle(ov02c10->dev);
945 return 0;
946
947 probe_error_v4l2_subdev_cleanup:
948 pm_runtime_disable(ov02c10->dev);
949 pm_runtime_set_suspended(ov02c10->dev);
950 v4l2_subdev_cleanup(&ov02c10->sd);
951
952 probe_error_media_entity_cleanup:
953 media_entity_cleanup(&ov02c10->sd.entity);
954
955 probe_error_v4l2_ctrl_handler_free:
956 v4l2_ctrl_handler_free(ov02c10->sd.ctrl_handler);
957
958 probe_error_power_off:
959 ov02c10_power_off(ov02c10->dev);
960
961 return ret;
962 }
963
964 static DEFINE_RUNTIME_DEV_PM_OPS(ov02c10_pm_ops, ov02c10_power_off,
965 ov02c10_power_on, NULL);
966
967 #ifdef CONFIG_ACPI
968 static const struct acpi_device_id ov02c10_acpi_ids[] = {
969 { "OVTI02C1" },
970 { /* sentinel */ }
971 };
972
973 MODULE_DEVICE_TABLE(acpi, ov02c10_acpi_ids);
974 #endif
975
976 static const struct of_device_id ov02c10_of_match[] = {
977 { .compatible = "ovti,ov02c10" },
978 { /* sentinel */ }
979 };
980 MODULE_DEVICE_TABLE(of, ov02c10_of_match);
981
982 static struct i2c_driver ov02c10_i2c_driver = {
983 .driver = {
984 .name = "ov02c10",
985 .pm = pm_sleep_ptr(&ov02c10_pm_ops),
986 .acpi_match_table = ACPI_PTR(ov02c10_acpi_ids),
987 .of_match_table = ov02c10_of_match,
988 },
989 .probe = ov02c10_probe,
990 .remove = ov02c10_remove,
991 };
992
993 module_i2c_driver(ov02c10_i2c_driver);
994
995 MODULE_AUTHOR("Hao Yao <hao.yao@intel.com>");
996 MODULE_AUTHOR("Heimir Thor Sverrisson <heimir.sverrisson@gmail.com>");
997 MODULE_AUTHOR("Hans de Goede <hansg@kernel.org>");
998 MODULE_DESCRIPTION("OmniVision OV02C10 sensor driver");
999 MODULE_LICENSE("GPL");
1000