1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * A V4L2 driver for Sony IMX219 cameras.
4 * Copyright (C) 2019, Raspberry Pi (Trading) Ltd
5 *
6 * Based on Sony imx258 camera driver
7 * Copyright (C) 2018 Intel Corporation
8 *
9 * DT / fwnode changes, and regulator / GPIO control taken from imx214 driver
10 * Copyright 2018 Qtechnology A/S
11 *
12 * Flip handling taken from the Sony IMX319 driver.
13 * Copyright (C) 2018 Intel Corporation
14 *
15 */
16
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/gpio/consumer.h>
20 #include <linux/i2c.h>
21 #include <linux/minmax.h>
22 #include <linux/module.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/regulator/consumer.h>
25
26 #include <media/v4l2-cci.h>
27 #include <media/v4l2-ctrls.h>
28 #include <media/v4l2-device.h>
29 #include <media/v4l2-fwnode.h>
30 #include <media/v4l2-mediabus.h>
31
32 /* Chip ID */
33 #define IMX219_REG_CHIP_ID CCI_REG16(0x0000)
34 #define IMX219_CHIP_ID 0x0219
35
36 #define IMX219_REG_MODE_SELECT CCI_REG8(0x0100)
37 #define IMX219_MODE_STANDBY 0x00
38 #define IMX219_MODE_STREAMING 0x01
39
40 #define IMX219_REG_CSI_LANE_MODE CCI_REG8(0x0114)
41 #define IMX219_CSI_2_LANE_MODE 0x01
42 #define IMX219_CSI_4_LANE_MODE 0x03
43
44 #define IMX219_REG_DPHY_CTRL CCI_REG8(0x0128)
45 #define IMX219_DPHY_CTRL_TIMING_AUTO 0
46 #define IMX219_DPHY_CTRL_TIMING_MANUAL 1
47
48 #define IMX219_REG_EXCK_FREQ CCI_REG16(0x012a)
49 #define IMX219_EXCK_FREQ(n) ((n) * 256) /* n expressed in MHz */
50
51 /* Analog gain control */
52 #define IMX219_REG_ANALOG_GAIN CCI_REG8(0x0157)
53 #define IMX219_ANA_GAIN_MIN 0
54 #define IMX219_ANA_GAIN_MAX 232
55 #define IMX219_ANA_GAIN_STEP 1
56 #define IMX219_ANA_GAIN_DEFAULT 0x0
57
58 /* Digital gain control */
59 #define IMX219_REG_DIGITAL_GAIN CCI_REG16(0x0158)
60 #define IMX219_DGTL_GAIN_MIN 0x0100
61 #define IMX219_DGTL_GAIN_MAX 0x0fff
62 #define IMX219_DGTL_GAIN_DEFAULT 0x0100
63 #define IMX219_DGTL_GAIN_STEP 1
64
65 /* Exposure control */
66 #define IMX219_REG_EXPOSURE CCI_REG16(0x015a)
67 #define IMX219_EXPOSURE_MIN 4
68 #define IMX219_EXPOSURE_STEP 1
69 #define IMX219_EXPOSURE_DEFAULT 0x640
70 #define IMX219_EXPOSURE_MAX 65535
71
72 /* V_TIMING internal */
73 #define IMX219_REG_FRM_LENGTH_A CCI_REG16(0x0160)
74 #define IMX219_FLL_MAX 0xffff
75 #define IMX219_VBLANK_MIN 32
76 #define IMX219_REG_LINE_LENGTH_A CCI_REG16(0x0162)
77 #define IMX219_LLP_MIN 0x0d78
78 #define IMX219_BINNED_LLP_MIN 0x0de8
79 #define IMX219_LLP_MAX 0x7ff0
80
81 #define IMX219_REG_X_ADD_STA_A CCI_REG16(0x0164)
82 #define IMX219_REG_X_ADD_END_A CCI_REG16(0x0166)
83 #define IMX219_REG_Y_ADD_STA_A CCI_REG16(0x0168)
84 #define IMX219_REG_Y_ADD_END_A CCI_REG16(0x016a)
85 #define IMX219_REG_X_OUTPUT_SIZE CCI_REG16(0x016c)
86 #define IMX219_REG_Y_OUTPUT_SIZE CCI_REG16(0x016e)
87 #define IMX219_REG_X_ODD_INC_A CCI_REG8(0x0170)
88 #define IMX219_REG_Y_ODD_INC_A CCI_REG8(0x0171)
89 #define IMX219_REG_ORIENTATION CCI_REG8(0x0172)
90
91 /* Binning Mode */
92 #define IMX219_REG_BINNING_MODE_H CCI_REG8(0x0174)
93 #define IMX219_REG_BINNING_MODE_V CCI_REG8(0x0175)
94 #define IMX219_BINNING_NONE 0x00
95 #define IMX219_BINNING_X2 0x01
96 #define IMX219_BINNING_X2_ANALOG 0x03
97
98 #define IMX219_REG_CSI_DATA_FORMAT_A CCI_REG16(0x018c)
99
100 /* PLL Settings */
101 #define IMX219_REG_VTPXCK_DIV CCI_REG8(0x0301)
102 #define IMX219_REG_VTSYCK_DIV CCI_REG8(0x0303)
103 #define IMX219_REG_PREPLLCK_VT_DIV CCI_REG8(0x0304)
104 #define IMX219_REG_PREPLLCK_OP_DIV CCI_REG8(0x0305)
105 #define IMX219_REG_PLL_VT_MPY CCI_REG16(0x0306)
106 #define IMX219_REG_OPPXCK_DIV CCI_REG8(0x0309)
107 #define IMX219_REG_OPSYCK_DIV CCI_REG8(0x030b)
108 #define IMX219_REG_PLL_OP_MPY CCI_REG16(0x030c)
109
110 /* Test Pattern Control */
111 #define IMX219_REG_TEST_PATTERN CCI_REG16(0x0600)
112 #define IMX219_TEST_PATTERN_DISABLE 0
113 #define IMX219_TEST_PATTERN_SOLID_COLOR 1
114 #define IMX219_TEST_PATTERN_COLOR_BARS 2
115 #define IMX219_TEST_PATTERN_GREY_COLOR 3
116 #define IMX219_TEST_PATTERN_PN9 4
117
118 /* Test pattern colour components */
119 #define IMX219_REG_TESTP_RED CCI_REG16(0x0602)
120 #define IMX219_REG_TESTP_GREENR CCI_REG16(0x0604)
121 #define IMX219_REG_TESTP_BLUE CCI_REG16(0x0606)
122 #define IMX219_REG_TESTP_GREENB CCI_REG16(0x0608)
123 #define IMX219_TESTP_COLOUR_MIN 0
124 #define IMX219_TESTP_COLOUR_MAX 0x03ff
125 #define IMX219_TESTP_COLOUR_STEP 1
126
127 #define IMX219_REG_TP_WINDOW_WIDTH CCI_REG16(0x0624)
128 #define IMX219_REG_TP_WINDOW_HEIGHT CCI_REG16(0x0626)
129
130 /* External clock frequency is 24.0M */
131 #define IMX219_XCLK_FREQ 24000000
132
133 /* Pixel rate is fixed for all the modes */
134 #define IMX219_PIXEL_RATE 182400000
135 #define IMX219_PIXEL_RATE_4LANE 281600000
136
137 #define IMX219_DEFAULT_LINK_FREQ 456000000
138 #define IMX219_DEFAULT_LINK_FREQ_4LANE_UNSUPPORTED 363000000
139 #define IMX219_DEFAULT_LINK_FREQ_4LANE 364000000
140
141 /* IMX219 native and active pixel array size. */
142 #define IMX219_NATIVE_WIDTH 3296U
143 #define IMX219_NATIVE_HEIGHT 2480U
144 #define IMX219_PIXEL_ARRAY_LEFT 8U
145 #define IMX219_PIXEL_ARRAY_TOP 8U
146 #define IMX219_PIXEL_ARRAY_WIDTH 3280U
147 #define IMX219_PIXEL_ARRAY_HEIGHT 2464U
148
149 /* Mode : resolution and related config&values */
150 struct imx219_mode {
151 /* Frame width */
152 unsigned int width;
153 /* Frame height */
154 unsigned int height;
155
156 /* V-timing */
157 unsigned int fll_def;
158 };
159
160 static const struct cci_reg_sequence imx219_common_regs[] = {
161 { IMX219_REG_MODE_SELECT, 0x00 }, /* Mode Select */
162
163 /* To Access Addresses 3000-5fff, send the following commands */
164 { CCI_REG8(0x30eb), 0x05 },
165 { CCI_REG8(0x30eb), 0x0c },
166 { CCI_REG8(0x300a), 0xff },
167 { CCI_REG8(0x300b), 0xff },
168 { CCI_REG8(0x30eb), 0x05 },
169 { CCI_REG8(0x30eb), 0x09 },
170
171 /* Undocumented registers */
172 { CCI_REG8(0x455e), 0x00 },
173 { CCI_REG8(0x471e), 0x4b },
174 { CCI_REG8(0x4767), 0x0f },
175 { CCI_REG8(0x4750), 0x14 },
176 { CCI_REG8(0x4540), 0x00 },
177 { CCI_REG8(0x47b4), 0x14 },
178 { CCI_REG8(0x4713), 0x30 },
179 { CCI_REG8(0x478b), 0x10 },
180 { CCI_REG8(0x478f), 0x10 },
181 { CCI_REG8(0x4793), 0x10 },
182 { CCI_REG8(0x4797), 0x0e },
183 { CCI_REG8(0x479b), 0x0e },
184
185 /* Frame Bank Register Group "A" */
186 { IMX219_REG_X_ODD_INC_A, 1 },
187 { IMX219_REG_Y_ODD_INC_A, 1 },
188
189 /* Output setup registers */
190 { IMX219_REG_DPHY_CTRL, IMX219_DPHY_CTRL_TIMING_AUTO },
191 { IMX219_REG_EXCK_FREQ, IMX219_EXCK_FREQ(IMX219_XCLK_FREQ / 1000000) },
192 };
193
194 static const struct cci_reg_sequence imx219_2lane_regs[] = {
195 /* PLL Clock Table */
196 { IMX219_REG_VTPXCK_DIV, 5 },
197 { IMX219_REG_VTSYCK_DIV, 1 },
198 { IMX219_REG_PREPLLCK_VT_DIV, 3 }, /* 0x03 = AUTO set */
199 { IMX219_REG_PREPLLCK_OP_DIV, 3 }, /* 0x03 = AUTO set */
200 { IMX219_REG_PLL_VT_MPY, 57 },
201 { IMX219_REG_OPSYCK_DIV, 1 },
202 { IMX219_REG_PLL_OP_MPY, 114 },
203
204 /* 2-Lane CSI Mode */
205 { IMX219_REG_CSI_LANE_MODE, IMX219_CSI_2_LANE_MODE },
206 };
207
208 static const struct cci_reg_sequence imx219_4lane_regs[] = {
209 /* PLL Clock Table */
210 { IMX219_REG_VTPXCK_DIV, 5 },
211 { IMX219_REG_VTSYCK_DIV, 1 },
212 { IMX219_REG_PREPLLCK_VT_DIV, 3 }, /* 0x03 = AUTO set */
213 { IMX219_REG_PREPLLCK_OP_DIV, 3 }, /* 0x03 = AUTO set */
214 { IMX219_REG_PLL_VT_MPY, 88 },
215 { IMX219_REG_OPSYCK_DIV, 1 },
216 { IMX219_REG_PLL_OP_MPY, 91 },
217
218 /* 4-Lane CSI Mode */
219 { IMX219_REG_CSI_LANE_MODE, IMX219_CSI_4_LANE_MODE },
220 };
221
222 static const s64 imx219_link_freq_menu[] = {
223 IMX219_DEFAULT_LINK_FREQ,
224 };
225
226 static const s64 imx219_link_freq_4lane_menu[] = {
227 IMX219_DEFAULT_LINK_FREQ_4LANE,
228 /*
229 * This will never be advertised to userspace, but will be used for
230 * v4l2_link_freq_to_bitmap
231 */
232 IMX219_DEFAULT_LINK_FREQ_4LANE_UNSUPPORTED,
233 };
234
235 static const char * const imx219_test_pattern_menu[] = {
236 "Disabled",
237 "Color Bars",
238 "Solid Color",
239 "Grey Color Bars",
240 "PN9"
241 };
242
243 static const int imx219_test_pattern_val[] = {
244 IMX219_TEST_PATTERN_DISABLE,
245 IMX219_TEST_PATTERN_COLOR_BARS,
246 IMX219_TEST_PATTERN_SOLID_COLOR,
247 IMX219_TEST_PATTERN_GREY_COLOR,
248 IMX219_TEST_PATTERN_PN9,
249 };
250
251 /* regulator supplies */
252 static const char * const imx219_supply_name[] = {
253 /* Supplies can be enabled in any order */
254 "VANA", /* Analog (2.8V) supply */
255 "VDIG", /* Digital Core (1.8V) supply */
256 "VDDL", /* IF (1.2V) supply */
257 };
258
259 #define IMX219_NUM_SUPPLIES ARRAY_SIZE(imx219_supply_name)
260
261 /*
262 * The supported formats.
263 * This table MUST contain 4 entries per format, to cover the various flip
264 * combinations in the order
265 * - no flip
266 * - h flip
267 * - v flip
268 * - h&v flips
269 */
270 static const u32 imx219_mbus_formats[] = {
271 MEDIA_BUS_FMT_SRGGB10_1X10,
272 MEDIA_BUS_FMT_SGRBG10_1X10,
273 MEDIA_BUS_FMT_SGBRG10_1X10,
274 MEDIA_BUS_FMT_SBGGR10_1X10,
275
276 MEDIA_BUS_FMT_SRGGB8_1X8,
277 MEDIA_BUS_FMT_SGRBG8_1X8,
278 MEDIA_BUS_FMT_SGBRG8_1X8,
279 MEDIA_BUS_FMT_SBGGR8_1X8,
280 };
281
282 /*
283 * Initialisation delay between XCLR low->high and the moment when the sensor
284 * can start capture (i.e. can leave software stanby) must be not less than:
285 * t4 + max(t5, t6 + <time to initialize the sensor register over I2C>)
286 * where
287 * t4 is fixed, and is max 200uS,
288 * t5 is fixed, and is 6000uS,
289 * t6 depends on the sensor external clock, and is max 32000 clock periods.
290 * As per sensor datasheet, the external clock must be from 6MHz to 27MHz.
291 * So for any acceptable external clock t6 is always within the range of
292 * 1185 to 5333 uS, and is always less than t5.
293 * For this reason this is always safe to wait (t4 + t5) = 6200 uS, then
294 * initialize the sensor over I2C, and then exit the software standby.
295 *
296 * This start-up time can be optimized a bit more, if we start the writes
297 * over I2C after (t4+t6), but before (t4+t5) expires. But then sensor
298 * initialization over I2C may complete before (t4+t5) expires, and we must
299 * ensure that capture is not started before (t4+t5).
300 *
301 * This delay doesn't account for the power supply startup time. If needed,
302 * this should be taken care of via the regulator framework. E.g. in the
303 * case of DT for regulator-fixed one should define the startup-delay-us
304 * property.
305 */
306 #define IMX219_XCLR_MIN_DELAY_US 6200
307 #define IMX219_XCLR_DELAY_RANGE_US 1000
308
309 /* Mode configs */
310 static const struct imx219_mode supported_modes[] = {
311 {
312 /* 8MPix 15fps mode */
313 .width = 3280,
314 .height = 2464,
315 .fll_def = 3526,
316 },
317 {
318 /* 1080P 30fps cropped */
319 .width = 1920,
320 .height = 1080,
321 .fll_def = 1763,
322 },
323 {
324 /* 2x2 binned 60fps mode */
325 .width = 1640,
326 .height = 1232,
327 .fll_def = 1707,
328 },
329 {
330 /* 640x480 60fps mode */
331 .width = 640,
332 .height = 480,
333 .fll_def = 1707,
334 },
335 };
336
337 struct imx219 {
338 struct v4l2_subdev sd;
339 struct media_pad pad;
340
341 struct regmap *regmap;
342 struct clk *xclk; /* system clock to IMX219 */
343 u32 xclk_freq;
344
345 struct gpio_desc *reset_gpio;
346 struct regulator_bulk_data supplies[IMX219_NUM_SUPPLIES];
347
348 struct v4l2_ctrl_handler ctrl_handler;
349 /* V4L2 Controls */
350 struct v4l2_ctrl *pixel_rate;
351 struct v4l2_ctrl *link_freq;
352 struct v4l2_ctrl *exposure;
353 struct v4l2_ctrl *vflip;
354 struct v4l2_ctrl *hflip;
355 struct v4l2_ctrl *vblank;
356 struct v4l2_ctrl *hblank;
357
358 /* Two or Four lanes */
359 u8 lanes;
360 };
361
to_imx219(struct v4l2_subdev * _sd)362 static inline struct imx219 *to_imx219(struct v4l2_subdev *_sd)
363 {
364 return container_of(_sd, struct imx219, sd);
365 }
366
367 /* Get bayer order based on flip setting. */
imx219_get_format_code(struct imx219 * imx219,u32 code)368 static u32 imx219_get_format_code(struct imx219 *imx219, u32 code)
369 {
370 unsigned int i;
371
372 for (i = 0; i < ARRAY_SIZE(imx219_mbus_formats); i++)
373 if (imx219_mbus_formats[i] == code)
374 break;
375
376 if (i >= ARRAY_SIZE(imx219_mbus_formats))
377 i = 0;
378
379 i = (i & ~3) | (imx219->vflip->val ? 2 : 0) |
380 (imx219->hflip->val ? 1 : 0);
381
382 return imx219_mbus_formats[i];
383 }
384
imx219_get_format_bpp(const struct v4l2_mbus_framefmt * format)385 static u32 imx219_get_format_bpp(const struct v4l2_mbus_framefmt *format)
386 {
387 switch (format->code) {
388 case MEDIA_BUS_FMT_SRGGB8_1X8:
389 case MEDIA_BUS_FMT_SGRBG8_1X8:
390 case MEDIA_BUS_FMT_SGBRG8_1X8:
391 case MEDIA_BUS_FMT_SBGGR8_1X8:
392 return 8;
393
394 case MEDIA_BUS_FMT_SRGGB10_1X10:
395 case MEDIA_BUS_FMT_SGRBG10_1X10:
396 case MEDIA_BUS_FMT_SGBRG10_1X10:
397 case MEDIA_BUS_FMT_SBGGR10_1X10:
398 default:
399 return 10;
400 }
401 }
402
imx219_get_binning(struct v4l2_subdev_state * state,u8 * bin_h,u8 * bin_v)403 static void imx219_get_binning(struct v4l2_subdev_state *state, u8 *bin_h,
404 u8 *bin_v)
405 {
406 const struct v4l2_mbus_framefmt *format =
407 v4l2_subdev_state_get_format(state, 0);
408 const struct v4l2_rect *crop = v4l2_subdev_state_get_crop(state, 0);
409 u32 hbin = crop->width / format->width;
410 u32 vbin = crop->height / format->height;
411
412 *bin_h = IMX219_BINNING_NONE;
413 *bin_v = IMX219_BINNING_NONE;
414
415 /*
416 * Use analog binning only if both dimensions are binned, as it crops
417 * the other dimension.
418 */
419 if (hbin == 2 && vbin == 2) {
420 *bin_h = IMX219_BINNING_X2_ANALOG;
421 *bin_v = IMX219_BINNING_X2_ANALOG;
422
423 return;
424 }
425
426 if (hbin == 2)
427 *bin_h = IMX219_BINNING_X2;
428 if (vbin == 2)
429 *bin_v = IMX219_BINNING_X2;
430 }
431
imx219_get_rate_factor(struct v4l2_subdev_state * state)432 static inline u32 imx219_get_rate_factor(struct v4l2_subdev_state *state)
433 {
434 u8 bin_h, bin_v;
435
436 imx219_get_binning(state, &bin_h, &bin_v);
437
438 return (bin_h & bin_v) == IMX219_BINNING_X2_ANALOG ? 2 : 1;
439 }
440
441 /* -----------------------------------------------------------------------------
442 * Controls
443 */
444
imx219_set_ctrl(struct v4l2_ctrl * ctrl)445 static int imx219_set_ctrl(struct v4l2_ctrl *ctrl)
446 {
447 struct imx219 *imx219 =
448 container_of(ctrl->handler, struct imx219, ctrl_handler);
449 struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd);
450 const struct v4l2_mbus_framefmt *format;
451 struct v4l2_subdev_state *state;
452 u32 rate_factor;
453 int ret = 0;
454
455 state = v4l2_subdev_get_locked_active_state(&imx219->sd);
456 format = v4l2_subdev_state_get_format(state, 0);
457 rate_factor = imx219_get_rate_factor(state);
458
459 if (ctrl->id == V4L2_CID_VBLANK) {
460 int exposure_max, exposure_def;
461
462 /* Update max exposure while meeting expected vblanking */
463 exposure_max = format->height + ctrl->val - 4;
464 exposure_def = (exposure_max < IMX219_EXPOSURE_DEFAULT) ?
465 exposure_max : IMX219_EXPOSURE_DEFAULT;
466 __v4l2_ctrl_modify_range(imx219->exposure,
467 imx219->exposure->minimum,
468 exposure_max, imx219->exposure->step,
469 exposure_def);
470 }
471
472 /*
473 * Applying V4L2 control value only happens
474 * when power is up for streaming
475 */
476 if (pm_runtime_get_if_in_use(&client->dev) == 0)
477 return 0;
478
479 switch (ctrl->id) {
480 case V4L2_CID_ANALOGUE_GAIN:
481 cci_write(imx219->regmap, IMX219_REG_ANALOG_GAIN,
482 ctrl->val, &ret);
483 break;
484 case V4L2_CID_EXPOSURE:
485 cci_write(imx219->regmap, IMX219_REG_EXPOSURE,
486 ctrl->val / rate_factor, &ret);
487 break;
488 case V4L2_CID_DIGITAL_GAIN:
489 cci_write(imx219->regmap, IMX219_REG_DIGITAL_GAIN,
490 ctrl->val, &ret);
491 break;
492 case V4L2_CID_TEST_PATTERN:
493 cci_write(imx219->regmap, IMX219_REG_TEST_PATTERN,
494 imx219_test_pattern_val[ctrl->val], &ret);
495 break;
496 case V4L2_CID_HFLIP:
497 case V4L2_CID_VFLIP:
498 cci_write(imx219->regmap, IMX219_REG_ORIENTATION,
499 imx219->hflip->val | imx219->vflip->val << 1, &ret);
500 break;
501 case V4L2_CID_VBLANK:
502 cci_write(imx219->regmap, IMX219_REG_FRM_LENGTH_A,
503 (format->height + ctrl->val) / rate_factor, &ret);
504 break;
505 case V4L2_CID_HBLANK:
506 cci_write(imx219->regmap, IMX219_REG_LINE_LENGTH_A,
507 format->width + ctrl->val, &ret);
508 break;
509 case V4L2_CID_TEST_PATTERN_RED:
510 cci_write(imx219->regmap, IMX219_REG_TESTP_RED,
511 ctrl->val, &ret);
512 break;
513 case V4L2_CID_TEST_PATTERN_GREENR:
514 cci_write(imx219->regmap, IMX219_REG_TESTP_GREENR,
515 ctrl->val, &ret);
516 break;
517 case V4L2_CID_TEST_PATTERN_BLUE:
518 cci_write(imx219->regmap, IMX219_REG_TESTP_BLUE,
519 ctrl->val, &ret);
520 break;
521 case V4L2_CID_TEST_PATTERN_GREENB:
522 cci_write(imx219->regmap, IMX219_REG_TESTP_GREENB,
523 ctrl->val, &ret);
524 break;
525 default:
526 dev_info(&client->dev,
527 "ctrl(id:0x%x,val:0x%x) is not handled\n",
528 ctrl->id, ctrl->val);
529 ret = -EINVAL;
530 break;
531 }
532
533 pm_runtime_put(&client->dev);
534
535 return ret;
536 }
537
538 static const struct v4l2_ctrl_ops imx219_ctrl_ops = {
539 .s_ctrl = imx219_set_ctrl,
540 };
541
imx219_get_pixel_rate(struct imx219 * imx219)542 static unsigned long imx219_get_pixel_rate(struct imx219 *imx219)
543 {
544 return (imx219->lanes == 2) ? IMX219_PIXEL_RATE : IMX219_PIXEL_RATE_4LANE;
545 }
546
547 /* Initialize control handlers */
imx219_init_controls(struct imx219 * imx219)548 static int imx219_init_controls(struct imx219 *imx219)
549 {
550 struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd);
551 const struct imx219_mode *mode = &supported_modes[0];
552 struct v4l2_ctrl_handler *ctrl_hdlr;
553 struct v4l2_fwnode_device_properties props;
554 int exposure_max, exposure_def;
555 int i, ret;
556
557 ctrl_hdlr = &imx219->ctrl_handler;
558 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 12);
559 if (ret)
560 return ret;
561
562 /* By default, PIXEL_RATE is read only */
563 imx219->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops,
564 V4L2_CID_PIXEL_RATE,
565 imx219_get_pixel_rate(imx219),
566 imx219_get_pixel_rate(imx219), 1,
567 imx219_get_pixel_rate(imx219));
568
569 imx219->link_freq =
570 v4l2_ctrl_new_int_menu(ctrl_hdlr, &imx219_ctrl_ops,
571 V4L2_CID_LINK_FREQ,
572 ARRAY_SIZE(imx219_link_freq_menu) - 1, 0,
573 (imx219->lanes == 2) ? imx219_link_freq_menu :
574 imx219_link_freq_4lane_menu);
575 if (imx219->link_freq)
576 imx219->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
577
578 /* Initial blanking and exposure. Limits are updated during set_fmt */
579 imx219->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops,
580 V4L2_CID_VBLANK, IMX219_VBLANK_MIN,
581 IMX219_FLL_MAX - mode->height, 1,
582 mode->fll_def - mode->height);
583 imx219->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops,
584 V4L2_CID_HBLANK,
585 IMX219_LLP_MIN - mode->width,
586 IMX219_LLP_MAX - mode->width, 1,
587 IMX219_LLP_MIN - mode->width);
588 exposure_max = mode->fll_def - 4;
589 exposure_def = (exposure_max < IMX219_EXPOSURE_DEFAULT) ?
590 exposure_max : IMX219_EXPOSURE_DEFAULT;
591 imx219->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops,
592 V4L2_CID_EXPOSURE,
593 IMX219_EXPOSURE_MIN, exposure_max,
594 IMX219_EXPOSURE_STEP,
595 exposure_def);
596
597 v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
598 IMX219_ANA_GAIN_MIN, IMX219_ANA_GAIN_MAX,
599 IMX219_ANA_GAIN_STEP, IMX219_ANA_GAIN_DEFAULT);
600
601 v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
602 IMX219_DGTL_GAIN_MIN, IMX219_DGTL_GAIN_MAX,
603 IMX219_DGTL_GAIN_STEP, IMX219_DGTL_GAIN_DEFAULT);
604
605 imx219->hflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops,
606 V4L2_CID_HFLIP, 0, 1, 1, 0);
607 if (imx219->hflip)
608 imx219->hflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;
609
610 imx219->vflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops,
611 V4L2_CID_VFLIP, 0, 1, 1, 0);
612 if (imx219->vflip)
613 imx219->vflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;
614
615 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &imx219_ctrl_ops,
616 V4L2_CID_TEST_PATTERN,
617 ARRAY_SIZE(imx219_test_pattern_menu) - 1,
618 0, 0, imx219_test_pattern_menu);
619 for (i = 0; i < 4; i++) {
620 /*
621 * The assumption is that
622 * V4L2_CID_TEST_PATTERN_GREENR == V4L2_CID_TEST_PATTERN_RED + 1
623 * V4L2_CID_TEST_PATTERN_BLUE == V4L2_CID_TEST_PATTERN_RED + 2
624 * V4L2_CID_TEST_PATTERN_GREENB == V4L2_CID_TEST_PATTERN_RED + 3
625 */
626 v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops,
627 V4L2_CID_TEST_PATTERN_RED + i,
628 IMX219_TESTP_COLOUR_MIN,
629 IMX219_TESTP_COLOUR_MAX,
630 IMX219_TESTP_COLOUR_STEP,
631 IMX219_TESTP_COLOUR_MAX);
632 /* The "Solid color" pattern is white by default */
633 }
634
635 if (ctrl_hdlr->error) {
636 ret = ctrl_hdlr->error;
637 dev_err_probe(&client->dev, ret, "Control init failed\n");
638 goto error;
639 }
640
641 ret = v4l2_fwnode_device_parse(&client->dev, &props);
642 if (ret)
643 goto error;
644
645 ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &imx219_ctrl_ops,
646 &props);
647 if (ret)
648 goto error;
649
650 imx219->sd.ctrl_handler = ctrl_hdlr;
651
652 return 0;
653
654 error:
655 v4l2_ctrl_handler_free(ctrl_hdlr);
656
657 return ret;
658 }
659
imx219_free_controls(struct imx219 * imx219)660 static void imx219_free_controls(struct imx219 *imx219)
661 {
662 v4l2_ctrl_handler_free(imx219->sd.ctrl_handler);
663 }
664
665 /* -----------------------------------------------------------------------------
666 * Subdev operations
667 */
668
imx219_set_framefmt(struct imx219 * imx219,struct v4l2_subdev_state * state)669 static int imx219_set_framefmt(struct imx219 *imx219,
670 struct v4l2_subdev_state *state)
671 {
672 const struct v4l2_mbus_framefmt *format;
673 const struct v4l2_rect *crop;
674 u8 bin_h, bin_v;
675 u32 bpp;
676 int ret = 0;
677
678 format = v4l2_subdev_state_get_format(state, 0);
679 crop = v4l2_subdev_state_get_crop(state, 0);
680 bpp = imx219_get_format_bpp(format);
681
682 cci_write(imx219->regmap, IMX219_REG_X_ADD_STA_A,
683 crop->left - IMX219_PIXEL_ARRAY_LEFT, &ret);
684 cci_write(imx219->regmap, IMX219_REG_X_ADD_END_A,
685 crop->left - IMX219_PIXEL_ARRAY_LEFT + crop->width - 1, &ret);
686 cci_write(imx219->regmap, IMX219_REG_Y_ADD_STA_A,
687 crop->top - IMX219_PIXEL_ARRAY_TOP, &ret);
688 cci_write(imx219->regmap, IMX219_REG_Y_ADD_END_A,
689 crop->top - IMX219_PIXEL_ARRAY_TOP + crop->height - 1, &ret);
690
691 imx219_get_binning(state, &bin_h, &bin_v);
692 cci_write(imx219->regmap, IMX219_REG_BINNING_MODE_H, bin_h, &ret);
693 cci_write(imx219->regmap, IMX219_REG_BINNING_MODE_V, bin_v, &ret);
694
695 cci_write(imx219->regmap, IMX219_REG_X_OUTPUT_SIZE,
696 format->width, &ret);
697 cci_write(imx219->regmap, IMX219_REG_Y_OUTPUT_SIZE,
698 format->height, &ret);
699
700 cci_write(imx219->regmap, IMX219_REG_TP_WINDOW_WIDTH,
701 format->width, &ret);
702 cci_write(imx219->regmap, IMX219_REG_TP_WINDOW_HEIGHT,
703 format->height, &ret);
704
705 cci_write(imx219->regmap, IMX219_REG_CSI_DATA_FORMAT_A,
706 (bpp << 8) | bpp, &ret);
707 cci_write(imx219->regmap, IMX219_REG_OPPXCK_DIV, bpp, &ret);
708
709 return ret;
710 }
711
imx219_configure_lanes(struct imx219 * imx219)712 static int imx219_configure_lanes(struct imx219 *imx219)
713 {
714 /* Write the appropriate PLL settings for the number of MIPI lanes */
715 return cci_multi_reg_write(imx219->regmap,
716 imx219->lanes == 2 ? imx219_2lane_regs : imx219_4lane_regs,
717 imx219->lanes == 2 ? ARRAY_SIZE(imx219_2lane_regs) :
718 ARRAY_SIZE(imx219_4lane_regs), NULL);
719 };
720
imx219_start_streaming(struct imx219 * imx219,struct v4l2_subdev_state * state)721 static int imx219_start_streaming(struct imx219 *imx219,
722 struct v4l2_subdev_state *state)
723 {
724 struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd);
725 int ret;
726
727 ret = pm_runtime_resume_and_get(&client->dev);
728 if (ret < 0)
729 return ret;
730
731 /* Send all registers that are common to all modes */
732 ret = cci_multi_reg_write(imx219->regmap, imx219_common_regs,
733 ARRAY_SIZE(imx219_common_regs), NULL);
734 if (ret) {
735 dev_err(&client->dev, "%s failed to send mfg header\n", __func__);
736 goto err_rpm_put;
737 }
738
739 /* Configure two or four Lane mode */
740 ret = imx219_configure_lanes(imx219);
741 if (ret) {
742 dev_err(&client->dev, "%s failed to configure lanes\n", __func__);
743 goto err_rpm_put;
744 }
745
746 /* Apply format and crop settings. */
747 ret = imx219_set_framefmt(imx219, state);
748 if (ret) {
749 dev_err(&client->dev, "%s failed to set frame format: %d\n",
750 __func__, ret);
751 goto err_rpm_put;
752 }
753
754 /* Apply customized values from user */
755 ret = __v4l2_ctrl_handler_setup(imx219->sd.ctrl_handler);
756 if (ret)
757 goto err_rpm_put;
758
759 /* set stream on register */
760 ret = cci_write(imx219->regmap, IMX219_REG_MODE_SELECT,
761 IMX219_MODE_STREAMING, NULL);
762 if (ret)
763 goto err_rpm_put;
764
765 /* vflip and hflip cannot change during streaming */
766 __v4l2_ctrl_grab(imx219->vflip, true);
767 __v4l2_ctrl_grab(imx219->hflip, true);
768
769 return 0;
770
771 err_rpm_put:
772 pm_runtime_put(&client->dev);
773 return ret;
774 }
775
imx219_stop_streaming(struct imx219 * imx219)776 static void imx219_stop_streaming(struct imx219 *imx219)
777 {
778 struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd);
779 int ret;
780
781 /* set stream off register */
782 ret = cci_write(imx219->regmap, IMX219_REG_MODE_SELECT,
783 IMX219_MODE_STANDBY, NULL);
784 if (ret)
785 dev_err(&client->dev, "%s failed to set stream\n", __func__);
786
787 __v4l2_ctrl_grab(imx219->vflip, false);
788 __v4l2_ctrl_grab(imx219->hflip, false);
789
790 pm_runtime_put(&client->dev);
791 }
792
imx219_set_stream(struct v4l2_subdev * sd,int enable)793 static int imx219_set_stream(struct v4l2_subdev *sd, int enable)
794 {
795 struct imx219 *imx219 = to_imx219(sd);
796 struct v4l2_subdev_state *state;
797 int ret = 0;
798
799 state = v4l2_subdev_lock_and_get_active_state(sd);
800
801 if (enable)
802 ret = imx219_start_streaming(imx219, state);
803 else
804 imx219_stop_streaming(imx219);
805
806 v4l2_subdev_unlock_state(state);
807 return ret;
808 }
809
imx219_update_pad_format(struct imx219 * imx219,const struct imx219_mode * mode,struct v4l2_mbus_framefmt * fmt,u32 code)810 static void imx219_update_pad_format(struct imx219 *imx219,
811 const struct imx219_mode *mode,
812 struct v4l2_mbus_framefmt *fmt, u32 code)
813 {
814 /* Bayer order varies with flips */
815 fmt->code = imx219_get_format_code(imx219, code);
816 fmt->width = mode->width;
817 fmt->height = mode->height;
818 fmt->field = V4L2_FIELD_NONE;
819 fmt->colorspace = V4L2_COLORSPACE_RAW;
820 fmt->ycbcr_enc = V4L2_YCBCR_ENC_601;
821 fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE;
822 fmt->xfer_func = V4L2_XFER_FUNC_NONE;
823 }
824
imx219_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,struct v4l2_subdev_mbus_code_enum * code)825 static int imx219_enum_mbus_code(struct v4l2_subdev *sd,
826 struct v4l2_subdev_state *state,
827 struct v4l2_subdev_mbus_code_enum *code)
828 {
829 struct imx219 *imx219 = to_imx219(sd);
830
831 if (code->index >= (ARRAY_SIZE(imx219_mbus_formats) / 4))
832 return -EINVAL;
833
834 code->code = imx219_get_format_code(imx219, imx219_mbus_formats[code->index * 4]);
835
836 return 0;
837 }
838
imx219_enum_frame_size(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,struct v4l2_subdev_frame_size_enum * fse)839 static int imx219_enum_frame_size(struct v4l2_subdev *sd,
840 struct v4l2_subdev_state *state,
841 struct v4l2_subdev_frame_size_enum *fse)
842 {
843 struct imx219 *imx219 = to_imx219(sd);
844 u32 code;
845
846 if (fse->index >= ARRAY_SIZE(supported_modes))
847 return -EINVAL;
848
849 code = imx219_get_format_code(imx219, fse->code);
850 if (fse->code != code)
851 return -EINVAL;
852
853 fse->min_width = supported_modes[fse->index].width;
854 fse->max_width = fse->min_width;
855 fse->min_height = supported_modes[fse->index].height;
856 fse->max_height = fse->min_height;
857
858 return 0;
859 }
860
imx219_set_pad_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,struct v4l2_subdev_format * fmt)861 static int imx219_set_pad_format(struct v4l2_subdev *sd,
862 struct v4l2_subdev_state *state,
863 struct v4l2_subdev_format *fmt)
864 {
865 struct imx219 *imx219 = to_imx219(sd);
866 const struct imx219_mode *mode;
867 struct v4l2_mbus_framefmt *format;
868 struct v4l2_rect *crop;
869 u8 bin_h, bin_v;
870 u32 prev_line_len;
871
872 format = v4l2_subdev_state_get_format(state, 0);
873 prev_line_len = format->width + imx219->hblank->val;
874
875 mode = v4l2_find_nearest_size(supported_modes,
876 ARRAY_SIZE(supported_modes),
877 width, height,
878 fmt->format.width, fmt->format.height);
879
880 imx219_update_pad_format(imx219, mode, &fmt->format, fmt->format.code);
881 *format = fmt->format;
882
883 /*
884 * Use binning to maximize the crop rectangle size, and centre it in the
885 * sensor.
886 */
887 bin_h = min(IMX219_PIXEL_ARRAY_WIDTH / format->width, 2U);
888 bin_v = min(IMX219_PIXEL_ARRAY_HEIGHT / format->height, 2U);
889
890 crop = v4l2_subdev_state_get_crop(state, 0);
891 crop->width = format->width * bin_h;
892 crop->height = format->height * bin_v;
893 crop->left = (IMX219_NATIVE_WIDTH - crop->width) / 2;
894 crop->top = (IMX219_NATIVE_HEIGHT - crop->height) / 2;
895
896 if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
897 int exposure_max;
898 int exposure_def;
899 int hblank, llp_min;
900 int pixel_rate;
901
902 /* Update limits and set FPS to default */
903 __v4l2_ctrl_modify_range(imx219->vblank, IMX219_VBLANK_MIN,
904 IMX219_FLL_MAX - mode->height, 1,
905 mode->fll_def - mode->height);
906 __v4l2_ctrl_s_ctrl(imx219->vblank,
907 mode->fll_def - mode->height);
908 /* Update max exposure while meeting expected vblanking */
909 exposure_max = mode->fll_def - 4;
910 exposure_def = (exposure_max < IMX219_EXPOSURE_DEFAULT) ?
911 exposure_max : IMX219_EXPOSURE_DEFAULT;
912 __v4l2_ctrl_modify_range(imx219->exposure,
913 imx219->exposure->minimum,
914 exposure_max, imx219->exposure->step,
915 exposure_def);
916
917 /*
918 * With analog binning the default minimum line length of 3448
919 * can cause artefacts with RAW10 formats, because the ADC
920 * operates on two lines together. So we switch to a higher
921 * minimum of 3560.
922 */
923 imx219_get_binning(state, &bin_h, &bin_v);
924 llp_min = (bin_h & bin_v) == IMX219_BINNING_X2_ANALOG ?
925 IMX219_BINNED_LLP_MIN : IMX219_LLP_MIN;
926 __v4l2_ctrl_modify_range(imx219->hblank, llp_min - mode->width,
927 IMX219_LLP_MAX - mode->width, 1,
928 llp_min - mode->width);
929 /*
930 * Retain PPL setting from previous mode so that the
931 * line time does not change on a mode change.
932 * Limits have to be recomputed as the controls define
933 * the blanking only, so PPL values need to have the
934 * mode width subtracted.
935 */
936 hblank = prev_line_len - mode->width;
937 __v4l2_ctrl_s_ctrl(imx219->hblank, hblank);
938
939 /* Scale the pixel rate based on the mode specific factor */
940 pixel_rate = imx219_get_pixel_rate(imx219) *
941 imx219_get_rate_factor(state);
942 __v4l2_ctrl_modify_range(imx219->pixel_rate, pixel_rate,
943 pixel_rate, 1, pixel_rate);
944 }
945
946 return 0;
947 }
948
imx219_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,struct v4l2_subdev_selection * sel)949 static int imx219_get_selection(struct v4l2_subdev *sd,
950 struct v4l2_subdev_state *state,
951 struct v4l2_subdev_selection *sel)
952 {
953 switch (sel->target) {
954 case V4L2_SEL_TGT_CROP:
955 sel->r = *v4l2_subdev_state_get_crop(state, 0);
956 return 0;
957
958 case V4L2_SEL_TGT_NATIVE_SIZE:
959 sel->r.top = 0;
960 sel->r.left = 0;
961 sel->r.width = IMX219_NATIVE_WIDTH;
962 sel->r.height = IMX219_NATIVE_HEIGHT;
963
964 return 0;
965
966 case V4L2_SEL_TGT_CROP_DEFAULT:
967 case V4L2_SEL_TGT_CROP_BOUNDS:
968 sel->r.top = IMX219_PIXEL_ARRAY_TOP;
969 sel->r.left = IMX219_PIXEL_ARRAY_LEFT;
970 sel->r.width = IMX219_PIXEL_ARRAY_WIDTH;
971 sel->r.height = IMX219_PIXEL_ARRAY_HEIGHT;
972
973 return 0;
974 }
975
976 return -EINVAL;
977 }
978
imx219_init_state(struct v4l2_subdev * sd,struct v4l2_subdev_state * state)979 static int imx219_init_state(struct v4l2_subdev *sd,
980 struct v4l2_subdev_state *state)
981 {
982 struct v4l2_subdev_format fmt = {
983 .which = V4L2_SUBDEV_FORMAT_TRY,
984 .pad = 0,
985 .format = {
986 .code = MEDIA_BUS_FMT_SRGGB10_1X10,
987 .width = supported_modes[0].width,
988 .height = supported_modes[0].height,
989 },
990 };
991
992 imx219_set_pad_format(sd, state, &fmt);
993
994 return 0;
995 }
996
997 static const struct v4l2_subdev_video_ops imx219_video_ops = {
998 .s_stream = imx219_set_stream,
999 };
1000
1001 static const struct v4l2_subdev_pad_ops imx219_pad_ops = {
1002 .enum_mbus_code = imx219_enum_mbus_code,
1003 .get_fmt = v4l2_subdev_get_fmt,
1004 .set_fmt = imx219_set_pad_format,
1005 .get_selection = imx219_get_selection,
1006 .enum_frame_size = imx219_enum_frame_size,
1007 };
1008
1009 static const struct v4l2_subdev_ops imx219_subdev_ops = {
1010 .video = &imx219_video_ops,
1011 .pad = &imx219_pad_ops,
1012 };
1013
1014 static const struct v4l2_subdev_internal_ops imx219_internal_ops = {
1015 .init_state = imx219_init_state,
1016 };
1017
1018 /* -----------------------------------------------------------------------------
1019 * Power management
1020 */
1021
imx219_power_on(struct device * dev)1022 static int imx219_power_on(struct device *dev)
1023 {
1024 struct v4l2_subdev *sd = dev_get_drvdata(dev);
1025 struct imx219 *imx219 = to_imx219(sd);
1026 int ret;
1027
1028 ret = regulator_bulk_enable(IMX219_NUM_SUPPLIES,
1029 imx219->supplies);
1030 if (ret) {
1031 dev_err(dev, "%s: failed to enable regulators\n",
1032 __func__);
1033 return ret;
1034 }
1035
1036 ret = clk_prepare_enable(imx219->xclk);
1037 if (ret) {
1038 dev_err(dev, "%s: failed to enable clock\n",
1039 __func__);
1040 goto reg_off;
1041 }
1042
1043 gpiod_set_value_cansleep(imx219->reset_gpio, 1);
1044 usleep_range(IMX219_XCLR_MIN_DELAY_US,
1045 IMX219_XCLR_MIN_DELAY_US + IMX219_XCLR_DELAY_RANGE_US);
1046
1047 return 0;
1048
1049 reg_off:
1050 regulator_bulk_disable(IMX219_NUM_SUPPLIES, imx219->supplies);
1051
1052 return ret;
1053 }
1054
imx219_power_off(struct device * dev)1055 static int imx219_power_off(struct device *dev)
1056 {
1057 struct v4l2_subdev *sd = dev_get_drvdata(dev);
1058 struct imx219 *imx219 = to_imx219(sd);
1059
1060 gpiod_set_value_cansleep(imx219->reset_gpio, 0);
1061 regulator_bulk_disable(IMX219_NUM_SUPPLIES, imx219->supplies);
1062 clk_disable_unprepare(imx219->xclk);
1063
1064 return 0;
1065 }
1066
1067 /* -----------------------------------------------------------------------------
1068 * Probe & remove
1069 */
1070
imx219_get_regulators(struct imx219 * imx219)1071 static int imx219_get_regulators(struct imx219 *imx219)
1072 {
1073 struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd);
1074 unsigned int i;
1075
1076 for (i = 0; i < IMX219_NUM_SUPPLIES; i++)
1077 imx219->supplies[i].supply = imx219_supply_name[i];
1078
1079 return devm_regulator_bulk_get(&client->dev,
1080 IMX219_NUM_SUPPLIES,
1081 imx219->supplies);
1082 }
1083
1084 /* Verify chip ID */
imx219_identify_module(struct imx219 * imx219)1085 static int imx219_identify_module(struct imx219 *imx219)
1086 {
1087 struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd);
1088 int ret;
1089 u64 val;
1090
1091 ret = cci_read(imx219->regmap, IMX219_REG_CHIP_ID, &val, NULL);
1092 if (ret)
1093 return dev_err_probe(&client->dev, ret,
1094 "failed to read chip id %x\n",
1095 IMX219_CHIP_ID);
1096
1097 if (val != IMX219_CHIP_ID)
1098 return dev_err_probe(&client->dev, -EIO,
1099 "chip id mismatch: %x!=%llx\n",
1100 IMX219_CHIP_ID, val);
1101
1102 return 0;
1103 }
1104
imx219_check_hwcfg(struct device * dev,struct imx219 * imx219)1105 static int imx219_check_hwcfg(struct device *dev, struct imx219 *imx219)
1106 {
1107 struct fwnode_handle *endpoint;
1108 struct v4l2_fwnode_endpoint ep_cfg = {
1109 .bus_type = V4L2_MBUS_CSI2_DPHY
1110 };
1111 unsigned long link_freq_bitmap;
1112 int ret = -EINVAL;
1113
1114 endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(dev), NULL);
1115 if (!endpoint)
1116 return dev_err_probe(dev, -EINVAL, "endpoint node not found\n");
1117
1118 if (v4l2_fwnode_endpoint_alloc_parse(endpoint, &ep_cfg)) {
1119 dev_err_probe(dev, -EINVAL, "could not parse endpoint\n");
1120 goto error_out;
1121 }
1122
1123 /* Check the number of MIPI CSI2 data lanes */
1124 if (ep_cfg.bus.mipi_csi2.num_data_lanes != 2 &&
1125 ep_cfg.bus.mipi_csi2.num_data_lanes != 4) {
1126 dev_err_probe(dev, -EINVAL,
1127 "only 2 or 4 data lanes are currently supported\n");
1128 goto error_out;
1129 }
1130 imx219->lanes = ep_cfg.bus.mipi_csi2.num_data_lanes;
1131
1132 /* Check the link frequency set in device tree */
1133 switch (imx219->lanes) {
1134 case 2:
1135 ret = v4l2_link_freq_to_bitmap(dev,
1136 ep_cfg.link_frequencies,
1137 ep_cfg.nr_of_link_frequencies,
1138 imx219_link_freq_menu,
1139 ARRAY_SIZE(imx219_link_freq_menu),
1140 &link_freq_bitmap);
1141 break;
1142 case 4:
1143 ret = v4l2_link_freq_to_bitmap(dev,
1144 ep_cfg.link_frequencies,
1145 ep_cfg.nr_of_link_frequencies,
1146 imx219_link_freq_4lane_menu,
1147 ARRAY_SIZE(imx219_link_freq_4lane_menu),
1148 &link_freq_bitmap);
1149
1150 if (!ret && (link_freq_bitmap & BIT(1))) {
1151 dev_warn(dev, "Link frequency of %d not supported, but has been incorrectly advertised previously\n",
1152 IMX219_DEFAULT_LINK_FREQ_4LANE_UNSUPPORTED);
1153 dev_warn(dev, "Using link frequency of %d\n",
1154 IMX219_DEFAULT_LINK_FREQ_4LANE);
1155 link_freq_bitmap |= BIT(0);
1156 }
1157 break;
1158 }
1159
1160 if (ret || !(link_freq_bitmap & BIT(0))) {
1161 ret = -EINVAL;
1162 dev_err_probe(dev, -EINVAL,
1163 "Link frequency not supported: %lld\n",
1164 ep_cfg.link_frequencies[0]);
1165 }
1166
1167 error_out:
1168 v4l2_fwnode_endpoint_free(&ep_cfg);
1169 fwnode_handle_put(endpoint);
1170
1171 return ret;
1172 }
1173
imx219_probe(struct i2c_client * client)1174 static int imx219_probe(struct i2c_client *client)
1175 {
1176 struct device *dev = &client->dev;
1177 struct imx219 *imx219;
1178 int ret;
1179
1180 imx219 = devm_kzalloc(&client->dev, sizeof(*imx219), GFP_KERNEL);
1181 if (!imx219)
1182 return -ENOMEM;
1183
1184 v4l2_i2c_subdev_init(&imx219->sd, client, &imx219_subdev_ops);
1185 imx219->sd.internal_ops = &imx219_internal_ops;
1186
1187 /* Check the hardware configuration in device tree */
1188 if (imx219_check_hwcfg(dev, imx219))
1189 return -EINVAL;
1190
1191 imx219->regmap = devm_cci_regmap_init_i2c(client, 16);
1192 if (IS_ERR(imx219->regmap))
1193 return dev_err_probe(dev, PTR_ERR(imx219->regmap),
1194 "failed to initialize CCI\n");
1195
1196 /* Get system clock (xclk) */
1197 imx219->xclk = devm_clk_get(dev, NULL);
1198 if (IS_ERR(imx219->xclk))
1199 return dev_err_probe(dev, PTR_ERR(imx219->xclk),
1200 "failed to get xclk\n");
1201
1202 imx219->xclk_freq = clk_get_rate(imx219->xclk);
1203 if (imx219->xclk_freq != IMX219_XCLK_FREQ)
1204 return dev_err_probe(dev, -EINVAL,
1205 "xclk frequency not supported: %d Hz\n",
1206 imx219->xclk_freq);
1207
1208 ret = imx219_get_regulators(imx219);
1209 if (ret)
1210 return dev_err_probe(dev, ret, "failed to get regulators\n");
1211
1212 /* Request optional enable pin */
1213 imx219->reset_gpio = devm_gpiod_get_optional(dev, "reset",
1214 GPIOD_OUT_HIGH);
1215
1216 /*
1217 * The sensor must be powered for imx219_identify_module()
1218 * to be able to read the CHIP_ID register
1219 */
1220 ret = imx219_power_on(dev);
1221 if (ret)
1222 return ret;
1223
1224 ret = imx219_identify_module(imx219);
1225 if (ret)
1226 goto error_power_off;
1227
1228 /*
1229 * Sensor doesn't enter LP-11 state upon power up until and unless
1230 * streaming is started, so upon power up switch the modes to:
1231 * streaming -> standby
1232 */
1233 ret = cci_write(imx219->regmap, IMX219_REG_MODE_SELECT,
1234 IMX219_MODE_STREAMING, NULL);
1235 if (ret < 0)
1236 goto error_power_off;
1237
1238 usleep_range(100, 110);
1239
1240 /* put sensor back to standby mode */
1241 ret = cci_write(imx219->regmap, IMX219_REG_MODE_SELECT,
1242 IMX219_MODE_STANDBY, NULL);
1243 if (ret < 0)
1244 goto error_power_off;
1245
1246 usleep_range(100, 110);
1247
1248 ret = imx219_init_controls(imx219);
1249 if (ret)
1250 goto error_power_off;
1251
1252 /* Initialize subdev */
1253 imx219->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1254 imx219->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1255
1256 /* Initialize source pad */
1257 imx219->pad.flags = MEDIA_PAD_FL_SOURCE;
1258
1259 ret = media_entity_pads_init(&imx219->sd.entity, 1, &imx219->pad);
1260 if (ret) {
1261 dev_err_probe(dev, ret, "failed to init entity pads\n");
1262 goto error_handler_free;
1263 }
1264
1265 imx219->sd.state_lock = imx219->ctrl_handler.lock;
1266 ret = v4l2_subdev_init_finalize(&imx219->sd);
1267 if (ret < 0) {
1268 dev_err_probe(dev, ret, "subdev init error\n");
1269 goto error_media_entity;
1270 }
1271
1272 pm_runtime_set_active(dev);
1273 pm_runtime_enable(dev);
1274
1275 ret = v4l2_async_register_subdev_sensor(&imx219->sd);
1276 if (ret < 0) {
1277 dev_err_probe(dev, ret,
1278 "failed to register sensor sub-device\n");
1279 goto error_subdev_cleanup;
1280 }
1281
1282 pm_runtime_idle(dev);
1283
1284 return 0;
1285
1286 error_subdev_cleanup:
1287 v4l2_subdev_cleanup(&imx219->sd);
1288 pm_runtime_disable(dev);
1289 pm_runtime_set_suspended(dev);
1290
1291 error_media_entity:
1292 media_entity_cleanup(&imx219->sd.entity);
1293
1294 error_handler_free:
1295 imx219_free_controls(imx219);
1296
1297 error_power_off:
1298 imx219_power_off(dev);
1299
1300 return ret;
1301 }
1302
imx219_remove(struct i2c_client * client)1303 static void imx219_remove(struct i2c_client *client)
1304 {
1305 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1306 struct imx219 *imx219 = to_imx219(sd);
1307
1308 v4l2_async_unregister_subdev(sd);
1309 v4l2_subdev_cleanup(sd);
1310 media_entity_cleanup(&sd->entity);
1311 imx219_free_controls(imx219);
1312
1313 pm_runtime_disable(&client->dev);
1314 if (!pm_runtime_status_suspended(&client->dev)) {
1315 imx219_power_off(&client->dev);
1316 pm_runtime_set_suspended(&client->dev);
1317 }
1318 }
1319
1320 static const struct of_device_id imx219_dt_ids[] = {
1321 { .compatible = "sony,imx219" },
1322 { /* sentinel */ }
1323 };
1324 MODULE_DEVICE_TABLE(of, imx219_dt_ids);
1325
1326 static const struct dev_pm_ops imx219_pm_ops = {
1327 SET_RUNTIME_PM_OPS(imx219_power_off, imx219_power_on, NULL)
1328 };
1329
1330 static struct i2c_driver imx219_i2c_driver = {
1331 .driver = {
1332 .name = "imx219",
1333 .of_match_table = imx219_dt_ids,
1334 .pm = &imx219_pm_ops,
1335 },
1336 .probe = imx219_probe,
1337 .remove = imx219_remove,
1338 };
1339
1340 module_i2c_driver(imx219_i2c_driver);
1341
1342 MODULE_AUTHOR("Dave Stevenson <dave.stevenson@raspberrypi.com");
1343 MODULE_DESCRIPTION("Sony IMX219 sensor driver");
1344 MODULE_LICENSE("GPL v2");
1345