1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * imx214.c - imx214 sensor driver
4 *
5 * Copyright 2018 Qtechnology A/S
6 *
7 * Ricardo Ribalda <ribalda@kernel.org>
8 */
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/i2c.h>
13 #include <linux/module.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/regmap.h>
16 #include <linux/regulator/consumer.h>
17 #include <media/media-entity.h>
18 #include <media/v4l2-cci.h>
19 #include <media/v4l2-ctrls.h>
20 #include <media/v4l2-fwnode.h>
21 #include <media/v4l2-subdev.h>
22
23 /* Chip ID */
24 #define IMX214_REG_CHIP_ID CCI_REG16(0x0016)
25 #define IMX214_CHIP_ID 0x0214
26
27 #define IMX214_REG_MODE_SELECT CCI_REG8(0x0100)
28 #define IMX214_MODE_STANDBY 0x00
29 #define IMX214_MODE_STREAMING 0x01
30
31 #define IMX214_REG_FAST_STANDBY_CTRL CCI_REG8(0x0106)
32
33 #define IMX214_DEFAULT_CLK_FREQ 24000000
34 #define IMX214_DEFAULT_LINK_FREQ 600000000
35 /* Keep wrong link frequency for backward compatibility */
36 #define IMX214_DEFAULT_LINK_FREQ_LEGACY 480000000
37 #define IMX214_DEFAULT_PIXEL_RATE ((IMX214_DEFAULT_LINK_FREQ * 8LL) / 10)
38 #define IMX214_FPS 30
39
40 /* V-TIMING internal */
41 #define IMX214_REG_FRM_LENGTH_LINES CCI_REG16(0x0340)
42 #define IMX214_VTS_MAX 0xffff
43
44 #define IMX214_VBLANK_MIN 890
45
46 /* HBLANK control - read only */
47 #define IMX214_PPL_DEFAULT 5008
48
49 /* Exposure control */
50 #define IMX214_REG_EXPOSURE CCI_REG16(0x0202)
51 #define IMX214_EXPOSURE_OFFSET 10
52 #define IMX214_EXPOSURE_MIN 1
53 #define IMX214_EXPOSURE_STEP 1
54 #define IMX214_EXPOSURE_DEFAULT 3184
55 #define IMX214_REG_EXPOSURE_RATIO CCI_REG8(0x0222)
56 #define IMX214_REG_SHORT_EXPOSURE CCI_REG16(0x0224)
57
58 /* Analog gain control */
59 #define IMX214_REG_ANALOG_GAIN CCI_REG16(0x0204)
60 #define IMX214_REG_SHORT_ANALOG_GAIN CCI_REG16(0x0216)
61 #define IMX214_ANA_GAIN_MIN 0
62 #define IMX214_ANA_GAIN_MAX 448
63 #define IMX214_ANA_GAIN_STEP 1
64 #define IMX214_ANA_GAIN_DEFAULT 0x0
65
66 /* Digital gain control */
67 #define IMX214_REG_DIG_GAIN_GREENR CCI_REG16(0x020e)
68 #define IMX214_REG_DIG_GAIN_RED CCI_REG16(0x0210)
69 #define IMX214_REG_DIG_GAIN_BLUE CCI_REG16(0x0212)
70 #define IMX214_REG_DIG_GAIN_GREENB CCI_REG16(0x0214)
71 #define IMX214_DGTL_GAIN_MIN 0x0100
72 #define IMX214_DGTL_GAIN_MAX 0x0fff
73 #define IMX214_DGTL_GAIN_DEFAULT 0x0100
74 #define IMX214_DGTL_GAIN_STEP 1
75
76 #define IMX214_REG_ORIENTATION CCI_REG8(0x0101)
77
78 #define IMX214_REG_MASK_CORR_FRAMES CCI_REG8(0x0105)
79 #define IMX214_CORR_FRAMES_TRANSMIT 0
80 #define IMX214_CORR_FRAMES_MASK 1
81
82 #define IMX214_REG_CSI_DATA_FORMAT CCI_REG16(0x0112)
83 #define IMX214_CSI_DATA_FORMAT_RAW8 0x0808
84 #define IMX214_CSI_DATA_FORMAT_RAW10 0x0A0A
85 #define IMX214_CSI_DATA_FORMAT_COMP6 0x0A06
86 #define IMX214_CSI_DATA_FORMAT_COMP8 0x0A08
87
88 #define IMX214_REG_CSI_LANE_MODE CCI_REG8(0x0114)
89 #define IMX214_CSI_2_LANE_MODE 1
90 #define IMX214_CSI_4_LANE_MODE 3
91
92 #define IMX214_REG_EXCK_FREQ CCI_REG16(0x0136)
93 #define IMX214_EXCK_FREQ(n) ((n) * 256) /* n expressed in MHz */
94
95 #define IMX214_REG_TEMP_SENSOR_CONTROL CCI_REG8(0x0138)
96
97 #define IMX214_REG_HDR_MODE CCI_REG8(0x0220)
98 #define IMX214_HDR_MODE_OFF 0
99 #define IMX214_HDR_MODE_ON 1
100
101 #define IMX214_REG_HDR_RES_REDUCTION CCI_REG8(0x0221)
102 #define IMX214_HDR_RES_REDU_THROUGH 0x11
103 #define IMX214_HDR_RES_REDU_2_BINNING 0x22
104
105 /* PLL settings */
106 #define IMX214_REG_VTPXCK_DIV CCI_REG8(0x0301)
107 #define IMX214_REG_VTSYCK_DIV CCI_REG8(0x0303)
108 #define IMX214_REG_PREPLLCK_VT_DIV CCI_REG8(0x0305)
109 #define IMX214_REG_PLL_VT_MPY CCI_REG16(0x0306)
110 #define IMX214_REG_OPPXCK_DIV CCI_REG8(0x0309)
111 #define IMX214_REG_OPSYCK_DIV CCI_REG8(0x030b)
112 #define IMX214_REG_PLL_MULT_DRIV CCI_REG8(0x0310)
113 #define IMX214_PLL_SINGLE 0
114 #define IMX214_PLL_DUAL 1
115
116 #define IMX214_REG_LINE_LENGTH_PCK CCI_REG16(0x0342)
117 #define IMX214_REG_X_ADD_STA CCI_REG16(0x0344)
118 #define IMX214_REG_Y_ADD_STA CCI_REG16(0x0346)
119 #define IMX214_REG_X_ADD_END CCI_REG16(0x0348)
120 #define IMX214_REG_Y_ADD_END CCI_REG16(0x034a)
121 #define IMX214_REG_X_OUTPUT_SIZE CCI_REG16(0x034c)
122 #define IMX214_REG_Y_OUTPUT_SIZE CCI_REG16(0x034e)
123 #define IMX214_REG_X_EVEN_INC CCI_REG8(0x0381)
124 #define IMX214_REG_X_ODD_INC CCI_REG8(0x0383)
125 #define IMX214_REG_Y_EVEN_INC CCI_REG8(0x0385)
126 #define IMX214_REG_Y_ODD_INC CCI_REG8(0x0387)
127
128 #define IMX214_REG_SCALE_MODE CCI_REG8(0x0401)
129 #define IMX214_SCALE_NONE 0
130 #define IMX214_SCALE_HORIZONTAL 1
131 #define IMX214_SCALE_FULL 2
132 #define IMX214_REG_SCALE_M CCI_REG16(0x0404)
133
134 #define IMX214_REG_DIG_CROP_X_OFFSET CCI_REG16(0x0408)
135 #define IMX214_REG_DIG_CROP_Y_OFFSET CCI_REG16(0x040a)
136 #define IMX214_REG_DIG_CROP_WIDTH CCI_REG16(0x040c)
137 #define IMX214_REG_DIG_CROP_HEIGHT CCI_REG16(0x040e)
138
139 #define IMX214_REG_REQ_LINK_BIT_RATE CCI_REG32(0x0820)
140 #define IMX214_LINK_BIT_RATE_MBPS(n) ((n) << 16)
141
142 /* Binning mode */
143 #define IMX214_REG_BINNING_MODE CCI_REG8(0x0900)
144 #define IMX214_BINNING_NONE 0
145 #define IMX214_BINNING_ENABLE 1
146 #define IMX214_REG_BINNING_TYPE CCI_REG8(0x0901)
147 #define IMX214_REG_BINNING_WEIGHTING CCI_REG8(0x0902)
148 #define IMX214_BINNING_AVERAGE 0x00
149 #define IMX214_BINNING_SUMMED 0x01
150 #define IMX214_BINNING_BAYER 0x02
151
152 #define IMX214_REG_SING_DEF_CORR_EN CCI_REG8(0x0b06)
153 #define IMX214_SING_DEF_CORR_OFF 0
154 #define IMX214_SING_DEF_CORR_ON 1
155
156 /* AWB control */
157 #define IMX214_REG_ABS_GAIN_GREENR CCI_REG16(0x0b8e)
158 #define IMX214_REG_ABS_GAIN_RED CCI_REG16(0x0b90)
159 #define IMX214_REG_ABS_GAIN_BLUE CCI_REG16(0x0b92)
160 #define IMX214_REG_ABS_GAIN_GREENB CCI_REG16(0x0b94)
161
162 #define IMX214_REG_RMSC_NR_MODE CCI_REG8(0x3001)
163 #define IMX214_REG_STATS_OUT_EN CCI_REG8(0x3013)
164 #define IMX214_STATS_OUT_OFF 0
165 #define IMX214_STATS_OUT_ON 1
166
167 /* Chroma noise reduction */
168 #define IMX214_REG_NML_NR_EN CCI_REG8(0x30a2)
169 #define IMX214_NML_NR_OFF 0
170 #define IMX214_NML_NR_ON 1
171
172 #define IMX214_REG_EBD_SIZE_V CCI_REG8(0x5041)
173 #define IMX214_EBD_NO 0
174 #define IMX214_EBD_4_LINE 4
175
176 #define IMX214_REG_RG_STATS_LMT CCI_REG16(0x6d12)
177 #define IMX214_RG_STATS_LMT_10_BIT 0x03FF
178 #define IMX214_RG_STATS_LMT_14_BIT 0x3FFF
179
180 #define IMX214_REG_ATR_FAST_MOVE CCI_REG8(0x9300)
181
182 /* Test Pattern Control */
183 #define IMX214_REG_TEST_PATTERN CCI_REG16(0x0600)
184 #define IMX214_TEST_PATTERN_DISABLE 0
185 #define IMX214_TEST_PATTERN_SOLID_COLOR 1
186 #define IMX214_TEST_PATTERN_COLOR_BARS 2
187 #define IMX214_TEST_PATTERN_GREY_COLOR 3
188 #define IMX214_TEST_PATTERN_PN9 4
189
190 /* Test pattern colour components */
191 #define IMX214_REG_TESTP_RED CCI_REG16(0x0602)
192 #define IMX214_REG_TESTP_GREENR CCI_REG16(0x0604)
193 #define IMX214_REG_TESTP_BLUE CCI_REG16(0x0606)
194 #define IMX214_REG_TESTP_GREENB CCI_REG16(0x0608)
195 #define IMX214_TESTP_COLOUR_MIN 0
196 #define IMX214_TESTP_COLOUR_MAX 0x03ff
197 #define IMX214_TESTP_COLOUR_STEP 1
198
199 /* IMX214 native and active pixel array size */
200 #define IMX214_NATIVE_WIDTH 4224U
201 #define IMX214_NATIVE_HEIGHT 3136U
202 #define IMX214_PIXEL_ARRAY_LEFT 8U
203 #define IMX214_PIXEL_ARRAY_TOP 8U
204 #define IMX214_PIXEL_ARRAY_WIDTH 4208U
205 #define IMX214_PIXEL_ARRAY_HEIGHT 3120U
206
207 static const char * const imx214_supply_name[] = {
208 "vdda",
209 "vddd",
210 "vdddo",
211 };
212
213 #define IMX214_NUM_SUPPLIES ARRAY_SIZE(imx214_supply_name)
214
215 /*
216 * The supported formats.
217 * This table MUST contain 4 entries per format, to cover the various flip
218 * combinations in the order
219 * - no flip
220 * - h flip
221 * - v flip
222 * - h&v flips
223 */
224 static const u32 imx214_mbus_formats[] = {
225 MEDIA_BUS_FMT_SRGGB10_1X10,
226 MEDIA_BUS_FMT_SGRBG10_1X10,
227 MEDIA_BUS_FMT_SGBRG10_1X10,
228 MEDIA_BUS_FMT_SBGGR10_1X10,
229 };
230
231 static const char * const imx214_test_pattern_menu[] = {
232 "Disabled",
233 "Color Bars",
234 "Solid Color",
235 "Grey Color Bars",
236 "PN9"
237 };
238
239 static const int imx214_test_pattern_val[] = {
240 IMX214_TEST_PATTERN_DISABLE,
241 IMX214_TEST_PATTERN_COLOR_BARS,
242 IMX214_TEST_PATTERN_SOLID_COLOR,
243 IMX214_TEST_PATTERN_GREY_COLOR,
244 IMX214_TEST_PATTERN_PN9,
245 };
246
247 struct imx214 {
248 struct device *dev;
249 struct clk *xclk;
250 struct regmap *regmap;
251
252 struct v4l2_subdev sd;
253 struct media_pad pad;
254
255 struct v4l2_ctrl_handler ctrls;
256 struct v4l2_ctrl *pixel_rate;
257 struct v4l2_ctrl *link_freq;
258 struct v4l2_ctrl *vblank;
259 struct v4l2_ctrl *hblank;
260 struct v4l2_ctrl *exposure;
261 struct v4l2_ctrl *unit_size;
262 struct {
263 struct v4l2_ctrl *hflip;
264 struct v4l2_ctrl *vflip;
265 };
266
267 struct regulator_bulk_data supplies[IMX214_NUM_SUPPLIES];
268
269 struct gpio_desc *enable_gpio;
270 };
271
272 /*From imx214_mode_tbls.h*/
273 static const struct cci_reg_sequence mode_4096x2304[] = {
274 { IMX214_REG_HDR_MODE, IMX214_HDR_MODE_OFF },
275 { IMX214_REG_HDR_RES_REDUCTION, IMX214_HDR_RES_REDU_THROUGH },
276 { IMX214_REG_EXPOSURE_RATIO, 1 },
277 { IMX214_REG_X_ADD_STA, 56 },
278 { IMX214_REG_Y_ADD_STA, 408 },
279 { IMX214_REG_X_ADD_END, 4151 },
280 { IMX214_REG_Y_ADD_END, 2711 },
281 { IMX214_REG_X_EVEN_INC, 1 },
282 { IMX214_REG_X_ODD_INC, 1 },
283 { IMX214_REG_Y_EVEN_INC, 1 },
284 { IMX214_REG_Y_ODD_INC, 1 },
285 { IMX214_REG_BINNING_MODE, IMX214_BINNING_NONE },
286 { IMX214_REG_BINNING_TYPE, 0 },
287 { IMX214_REG_BINNING_WEIGHTING, IMX214_BINNING_AVERAGE },
288 { CCI_REG8(0x3000), 0x35 },
289 { CCI_REG8(0x3054), 0x01 },
290 { CCI_REG8(0x305C), 0x11 },
291
292 { IMX214_REG_CSI_DATA_FORMAT, IMX214_CSI_DATA_FORMAT_RAW10 },
293 { IMX214_REG_X_OUTPUT_SIZE, 4096 },
294 { IMX214_REG_Y_OUTPUT_SIZE, 2304 },
295 { IMX214_REG_SCALE_MODE, IMX214_SCALE_NONE },
296 { IMX214_REG_SCALE_M, 2 },
297 { IMX214_REG_DIG_CROP_X_OFFSET, 0 },
298 { IMX214_REG_DIG_CROP_Y_OFFSET, 0 },
299 { IMX214_REG_DIG_CROP_WIDTH, 4096 },
300 { IMX214_REG_DIG_CROP_HEIGHT, 2304 },
301
302 { IMX214_REG_VTPXCK_DIV, 5 },
303 { IMX214_REG_VTSYCK_DIV, 2 },
304 { IMX214_REG_PREPLLCK_VT_DIV, 3 },
305 { IMX214_REG_PLL_VT_MPY, 150 },
306 { IMX214_REG_OPPXCK_DIV, 10 },
307 { IMX214_REG_OPSYCK_DIV, 1 },
308 { IMX214_REG_PLL_MULT_DRIV, IMX214_PLL_SINGLE },
309
310 { IMX214_REG_REQ_LINK_BIT_RATE, IMX214_LINK_BIT_RATE_MBPS(4800) },
311
312 { CCI_REG8(0x3A03), 0x09 },
313 { CCI_REG8(0x3A04), 0x50 },
314 { CCI_REG8(0x3A05), 0x01 },
315
316 { IMX214_REG_SING_DEF_CORR_EN, IMX214_SING_DEF_CORR_ON },
317 { IMX214_REG_NML_NR_EN, IMX214_NML_NR_OFF },
318
319 { CCI_REG8(0x30B4), 0x00 },
320
321 { CCI_REG8(0x3A02), 0xFF },
322
323 { CCI_REG8(0x3011), 0x00 },
324 { IMX214_REG_STATS_OUT_EN, IMX214_STATS_OUT_ON },
325
326 { IMX214_REG_SHORT_EXPOSURE, 500 },
327
328 { CCI_REG8(0x4170), 0x00 },
329 { CCI_REG8(0x4171), 0x10 },
330 { CCI_REG8(0x4176), 0x00 },
331 { CCI_REG8(0x4177), 0x3C },
332 { CCI_REG8(0xAE20), 0x04 },
333 { CCI_REG8(0xAE21), 0x5C },
334 };
335
336 static const struct cci_reg_sequence mode_1920x1080[] = {
337 { IMX214_REG_HDR_MODE, IMX214_HDR_MODE_OFF },
338 { IMX214_REG_HDR_RES_REDUCTION, IMX214_HDR_RES_REDU_THROUGH },
339 { IMX214_REG_EXPOSURE_RATIO, 1 },
340 { IMX214_REG_X_ADD_STA, 1144 },
341 { IMX214_REG_Y_ADD_STA, 1020 },
342 { IMX214_REG_X_ADD_END, 3063 },
343 { IMX214_REG_Y_ADD_END, 2099 },
344 { IMX214_REG_X_EVEN_INC, 1 },
345 { IMX214_REG_X_ODD_INC, 1 },
346 { IMX214_REG_Y_EVEN_INC, 1 },
347 { IMX214_REG_Y_ODD_INC, 1 },
348 { IMX214_REG_BINNING_MODE, IMX214_BINNING_NONE },
349 { IMX214_REG_BINNING_TYPE, 0 },
350 { IMX214_REG_BINNING_WEIGHTING, IMX214_BINNING_AVERAGE },
351 { CCI_REG8(0x3000), 0x35 },
352 { CCI_REG8(0x3054), 0x01 },
353 { CCI_REG8(0x305C), 0x11 },
354
355 { IMX214_REG_CSI_DATA_FORMAT, IMX214_CSI_DATA_FORMAT_RAW10 },
356 { IMX214_REG_X_OUTPUT_SIZE, 1920 },
357 { IMX214_REG_Y_OUTPUT_SIZE, 1080 },
358 { IMX214_REG_SCALE_MODE, IMX214_SCALE_NONE },
359 { IMX214_REG_SCALE_M, 2 },
360 { IMX214_REG_DIG_CROP_X_OFFSET, 0 },
361 { IMX214_REG_DIG_CROP_Y_OFFSET, 0 },
362 { IMX214_REG_DIG_CROP_WIDTH, 1920 },
363 { IMX214_REG_DIG_CROP_HEIGHT, 1080 },
364
365 { IMX214_REG_VTPXCK_DIV, 5 },
366 { IMX214_REG_VTSYCK_DIV, 2 },
367 { IMX214_REG_PREPLLCK_VT_DIV, 3 },
368 { IMX214_REG_PLL_VT_MPY, 150 },
369 { IMX214_REG_OPPXCK_DIV, 10 },
370 { IMX214_REG_OPSYCK_DIV, 1 },
371 { IMX214_REG_PLL_MULT_DRIV, IMX214_PLL_SINGLE },
372
373 { IMX214_REG_REQ_LINK_BIT_RATE, IMX214_LINK_BIT_RATE_MBPS(4800) },
374
375 { CCI_REG8(0x3A03), 0x04 },
376 { CCI_REG8(0x3A04), 0xF8 },
377 { CCI_REG8(0x3A05), 0x02 },
378
379 { IMX214_REG_SING_DEF_CORR_EN, IMX214_SING_DEF_CORR_ON },
380 { IMX214_REG_NML_NR_EN, IMX214_NML_NR_OFF },
381
382 { CCI_REG8(0x30B4), 0x00 },
383
384 { CCI_REG8(0x3A02), 0xFF },
385
386 { CCI_REG8(0x3011), 0x00 },
387 { IMX214_REG_STATS_OUT_EN, IMX214_STATS_OUT_ON },
388
389 { IMX214_REG_SHORT_EXPOSURE, 500 },
390
391 { CCI_REG8(0x4170), 0x00 },
392 { CCI_REG8(0x4171), 0x10 },
393 { CCI_REG8(0x4176), 0x00 },
394 { CCI_REG8(0x4177), 0x3C },
395 { CCI_REG8(0xAE20), 0x04 },
396 { CCI_REG8(0xAE21), 0x5C },
397 };
398
399 static const struct cci_reg_sequence mode_table_common[] = {
400 /* software reset */
401
402 /* software standby settings */
403 { IMX214_REG_MODE_SELECT, IMX214_MODE_STANDBY },
404
405 /* ATR setting */
406 { IMX214_REG_ATR_FAST_MOVE, 2 },
407
408 /* external clock setting */
409 { IMX214_REG_EXCK_FREQ, IMX214_EXCK_FREQ(IMX214_DEFAULT_CLK_FREQ / 1000000) },
410
411 /* global setting */
412 /* basic config */
413 { IMX214_REG_MASK_CORR_FRAMES, IMX214_CORR_FRAMES_MASK },
414 { IMX214_REG_FAST_STANDBY_CTRL, 1 },
415 { IMX214_REG_LINE_LENGTH_PCK, IMX214_PPL_DEFAULT },
416 { CCI_REG8(0x4550), 0x02 },
417 { CCI_REG8(0x4601), 0x00 },
418 { CCI_REG8(0x4642), 0x05 },
419 { CCI_REG8(0x6227), 0x11 },
420 { CCI_REG8(0x6276), 0x00 },
421 { CCI_REG8(0x900E), 0x06 },
422 { CCI_REG8(0xA802), 0x90 },
423 { CCI_REG8(0xA803), 0x11 },
424 { CCI_REG8(0xA804), 0x62 },
425 { CCI_REG8(0xA805), 0x77 },
426 { CCI_REG8(0xA806), 0xAE },
427 { CCI_REG8(0xA807), 0x34 },
428 { CCI_REG8(0xA808), 0xAE },
429 { CCI_REG8(0xA809), 0x35 },
430 { CCI_REG8(0xA80A), 0x62 },
431 { CCI_REG8(0xA80B), 0x83 },
432 { CCI_REG8(0xAE33), 0x00 },
433
434 /* analog setting */
435 { CCI_REG8(0x4174), 0x00 },
436 { CCI_REG8(0x4175), 0x11 },
437 { CCI_REG8(0x4612), 0x29 },
438 { CCI_REG8(0x461B), 0x12 },
439 { CCI_REG8(0x461F), 0x06 },
440 { CCI_REG8(0x4635), 0x07 },
441 { CCI_REG8(0x4637), 0x30 },
442 { CCI_REG8(0x463F), 0x18 },
443 { CCI_REG8(0x4641), 0x0D },
444 { CCI_REG8(0x465B), 0x12 },
445 { CCI_REG8(0x465F), 0x11 },
446 { CCI_REG8(0x4663), 0x11 },
447 { CCI_REG8(0x4667), 0x0F },
448 { CCI_REG8(0x466F), 0x0F },
449 { CCI_REG8(0x470E), 0x09 },
450 { CCI_REG8(0x4909), 0xAB },
451 { CCI_REG8(0x490B), 0x95 },
452 { CCI_REG8(0x4915), 0x5D },
453 { CCI_REG8(0x4A5F), 0xFF },
454 { CCI_REG8(0x4A61), 0xFF },
455 { CCI_REG8(0x4A73), 0x62 },
456 { CCI_REG8(0x4A85), 0x00 },
457 { CCI_REG8(0x4A87), 0xFF },
458
459 /* embedded data */
460 { IMX214_REG_EBD_SIZE_V, IMX214_EBD_4_LINE },
461 { CCI_REG8(0x583C), 0x04 },
462 { CCI_REG8(0x620E), 0x04 },
463 { CCI_REG8(0x6EB2), 0x01 },
464 { CCI_REG8(0x6EB3), 0x00 },
465 { IMX214_REG_ATR_FAST_MOVE, 2 },
466
467 /* imagequality */
468 /* HDR setting */
469 { IMX214_REG_RMSC_NR_MODE, 0x07 },
470 { IMX214_REG_RG_STATS_LMT, IMX214_RG_STATS_LMT_14_BIT },
471 { CCI_REG8(0x9344), 0x03 },
472 { CCI_REG8(0x9706), 0x10 },
473 { CCI_REG8(0x9707), 0x03 },
474 { CCI_REG8(0x9708), 0x03 },
475 { CCI_REG8(0x9E04), 0x01 },
476 { CCI_REG8(0x9E05), 0x00 },
477 { CCI_REG8(0x9E0C), 0x01 },
478 { CCI_REG8(0x9E0D), 0x02 },
479 { CCI_REG8(0x9E24), 0x00 },
480 { CCI_REG8(0x9E25), 0x8C },
481 { CCI_REG8(0x9E26), 0x00 },
482 { CCI_REG8(0x9E27), 0x94 },
483 { CCI_REG8(0x9E28), 0x00 },
484 { CCI_REG8(0x9E29), 0x96 },
485
486 /* CNR parameter setting */
487 { CCI_REG8(0x69DB), 0x01 },
488
489 /* Moire reduction */
490 { CCI_REG8(0x6957), 0x01 },
491
492 /* image enhancement */
493 { CCI_REG8(0x6987), 0x17 },
494 { CCI_REG8(0x698A), 0x03 },
495 { CCI_REG8(0x698B), 0x03 },
496
497 /* white balanace */
498 { IMX214_REG_ABS_GAIN_GREENR, 0x0100 },
499 { IMX214_REG_ABS_GAIN_RED, 0x0100 },
500 { IMX214_REG_ABS_GAIN_BLUE, 0x0100 },
501 { IMX214_REG_ABS_GAIN_GREENB, 0x0100 },
502
503 /* ATR setting */
504 { CCI_REG8(0x6E50), 0x00 },
505 { CCI_REG8(0x6E51), 0x32 },
506 { CCI_REG8(0x9340), 0x00 },
507 { CCI_REG8(0x9341), 0x3C },
508 { CCI_REG8(0x9342), 0x03 },
509 { CCI_REG8(0x9343), 0xFF },
510 };
511
512 /*
513 * Declare modes in order, from biggest
514 * to smallest height.
515 */
516 static const struct imx214_mode {
517 u32 width;
518 u32 height;
519
520 /* V-timing */
521 unsigned int vts_def;
522
523 unsigned int num_of_regs;
524 const struct cci_reg_sequence *reg_table;
525 } imx214_modes[] = {
526 {
527 .width = 4096,
528 .height = 2304,
529 .vts_def = 3194,
530 .num_of_regs = ARRAY_SIZE(mode_4096x2304),
531 .reg_table = mode_4096x2304,
532 },
533 {
534 .width = 1920,
535 .height = 1080,
536 .vts_def = 3194,
537 .num_of_regs = ARRAY_SIZE(mode_1920x1080),
538 .reg_table = mode_1920x1080,
539 },
540 };
541
to_imx214(struct v4l2_subdev * sd)542 static inline struct imx214 *to_imx214(struct v4l2_subdev *sd)
543 {
544 return container_of(sd, struct imx214, sd);
545 }
546
imx214_power_on(struct device * dev)547 static int __maybe_unused imx214_power_on(struct device *dev)
548 {
549 struct i2c_client *client = to_i2c_client(dev);
550 struct v4l2_subdev *sd = i2c_get_clientdata(client);
551 struct imx214 *imx214 = to_imx214(sd);
552 int ret;
553
554 ret = regulator_bulk_enable(IMX214_NUM_SUPPLIES, imx214->supplies);
555 if (ret < 0) {
556 dev_err(imx214->dev, "failed to enable regulators: %d\n", ret);
557 return ret;
558 }
559
560 usleep_range(2000, 3000);
561
562 ret = clk_prepare_enable(imx214->xclk);
563 if (ret < 0) {
564 regulator_bulk_disable(IMX214_NUM_SUPPLIES, imx214->supplies);
565 dev_err(imx214->dev, "clk prepare enable failed\n");
566 return ret;
567 }
568
569 gpiod_set_value_cansleep(imx214->enable_gpio, 1);
570 usleep_range(12000, 15000);
571
572 return 0;
573 }
574
imx214_power_off(struct device * dev)575 static int __maybe_unused imx214_power_off(struct device *dev)
576 {
577 struct i2c_client *client = to_i2c_client(dev);
578 struct v4l2_subdev *sd = i2c_get_clientdata(client);
579 struct imx214 *imx214 = to_imx214(sd);
580
581 gpiod_set_value_cansleep(imx214->enable_gpio, 0);
582
583 clk_disable_unprepare(imx214->xclk);
584
585 regulator_bulk_disable(IMX214_NUM_SUPPLIES, imx214->supplies);
586 usleep_range(10, 20);
587
588 return 0;
589 }
590
591 /* Get bayer order based on flip setting. */
imx214_get_format_code(struct imx214 * imx214)592 static u32 imx214_get_format_code(struct imx214 *imx214)
593 {
594 unsigned int i;
595
596 i = (imx214->vflip->val ? 2 : 0) | (imx214->hflip->val ? 1 : 0);
597
598 return imx214_mbus_formats[i];
599 }
600
imx214_update_pad_format(struct imx214 * imx214,const struct imx214_mode * mode,struct v4l2_mbus_framefmt * fmt,u32 code)601 static void imx214_update_pad_format(struct imx214 *imx214,
602 const struct imx214_mode *mode,
603 struct v4l2_mbus_framefmt *fmt, u32 code)
604 {
605 fmt->code = imx214_get_format_code(imx214);
606 fmt->width = mode->width;
607 fmt->height = mode->height;
608 fmt->field = V4L2_FIELD_NONE;
609 fmt->colorspace = V4L2_COLORSPACE_SRGB;
610 fmt->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt->colorspace);
611 fmt->quantization = V4L2_MAP_QUANTIZATION_DEFAULT(true,
612 fmt->colorspace,
613 fmt->ycbcr_enc);
614 fmt->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt->colorspace);
615 }
616
imx214_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)617 static int imx214_enum_mbus_code(struct v4l2_subdev *sd,
618 struct v4l2_subdev_state *sd_state,
619 struct v4l2_subdev_mbus_code_enum *code)
620 {
621 struct imx214 *imx214 = to_imx214(sd);
622
623 if (code->index >= (ARRAY_SIZE(imx214_mbus_formats) / 4))
624 return -EINVAL;
625
626 code->code = imx214_get_format_code(imx214);
627
628 return 0;
629 }
630
imx214_enum_frame_size(struct v4l2_subdev * subdev,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_size_enum * fse)631 static int imx214_enum_frame_size(struct v4l2_subdev *subdev,
632 struct v4l2_subdev_state *sd_state,
633 struct v4l2_subdev_frame_size_enum *fse)
634 {
635 struct imx214 *imx214 = to_imx214(subdev);
636 u32 code;
637
638 code = imx214_get_format_code(imx214);
639 if (fse->code != code)
640 return -EINVAL;
641
642 if (fse->index >= ARRAY_SIZE(imx214_modes))
643 return -EINVAL;
644
645 fse->min_width = fse->max_width = imx214_modes[fse->index].width;
646 fse->min_height = fse->max_height = imx214_modes[fse->index].height;
647
648 return 0;
649 }
650
651 #ifdef CONFIG_VIDEO_ADV_DEBUG
imx214_s_register(struct v4l2_subdev * subdev,const struct v4l2_dbg_register * reg)652 static int imx214_s_register(struct v4l2_subdev *subdev,
653 const struct v4l2_dbg_register *reg)
654 {
655 struct imx214 *imx214 = container_of(subdev, struct imx214, sd);
656
657 return regmap_write(imx214->regmap, reg->reg, reg->val);
658 }
659
imx214_g_register(struct v4l2_subdev * subdev,struct v4l2_dbg_register * reg)660 static int imx214_g_register(struct v4l2_subdev *subdev,
661 struct v4l2_dbg_register *reg)
662 {
663 struct imx214 *imx214 = container_of(subdev, struct imx214, sd);
664 unsigned int aux;
665 int ret;
666
667 reg->size = 1;
668 ret = regmap_read(imx214->regmap, reg->reg, &aux);
669 reg->val = aux;
670
671 return ret;
672 }
673 #endif
674
675 static const struct v4l2_subdev_core_ops imx214_core_ops = {
676 #ifdef CONFIG_VIDEO_ADV_DEBUG
677 .g_register = imx214_g_register,
678 .s_register = imx214_s_register,
679 #endif
680 };
681
imx214_set_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)682 static int imx214_set_format(struct v4l2_subdev *sd,
683 struct v4l2_subdev_state *sd_state,
684 struct v4l2_subdev_format *format)
685 {
686 struct imx214 *imx214 = to_imx214(sd);
687 struct v4l2_mbus_framefmt *__format;
688 struct v4l2_rect *__crop;
689 const struct imx214_mode *mode;
690
691 mode = v4l2_find_nearest_size(imx214_modes,
692 ARRAY_SIZE(imx214_modes), width, height,
693 format->format.width,
694 format->format.height);
695
696 imx214_update_pad_format(imx214, mode, &format->format,
697 format->format.code);
698 __format = v4l2_subdev_state_get_format(sd_state, 0);
699
700 *__format = format->format;
701
702 __crop = v4l2_subdev_state_get_crop(sd_state, 0);
703 __crop->width = mode->width;
704 __crop->height = mode->height;
705
706 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
707 int exposure_max;
708 int exposure_def;
709 int hblank;
710
711 /* Update blank limits */
712 __v4l2_ctrl_modify_range(imx214->vblank, IMX214_VBLANK_MIN,
713 IMX214_VTS_MAX - mode->height, 2,
714 mode->vts_def - mode->height);
715
716 /* Update max exposure while meeting expected vblanking */
717 exposure_max = mode->vts_def - IMX214_EXPOSURE_OFFSET;
718 exposure_def = min(exposure_max, IMX214_EXPOSURE_DEFAULT);
719 __v4l2_ctrl_modify_range(imx214->exposure,
720 imx214->exposure->minimum,
721 exposure_max, imx214->exposure->step,
722 exposure_def);
723
724 /*
725 * Currently PPL is fixed to IMX214_PPL_DEFAULT, so hblank
726 * depends on mode->width only, and is not changeable in any
727 * way other than changing the mode.
728 */
729 hblank = IMX214_PPL_DEFAULT - mode->width;
730 __v4l2_ctrl_modify_range(imx214->hblank, hblank, hblank, 1,
731 hblank);
732 }
733
734 return 0;
735 }
736
imx214_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_selection * sel)737 static int imx214_get_selection(struct v4l2_subdev *sd,
738 struct v4l2_subdev_state *sd_state,
739 struct v4l2_subdev_selection *sel)
740 {
741 switch (sel->target) {
742 case V4L2_SEL_TGT_CROP:
743 sel->r = *v4l2_subdev_state_get_crop(sd_state, 0);
744 return 0;
745
746 case V4L2_SEL_TGT_NATIVE_SIZE:
747 sel->r.top = 0;
748 sel->r.left = 0;
749 sel->r.width = IMX214_NATIVE_WIDTH;
750 sel->r.height = IMX214_NATIVE_HEIGHT;
751 return 0;
752
753 case V4L2_SEL_TGT_CROP_DEFAULT:
754 case V4L2_SEL_TGT_CROP_BOUNDS:
755 sel->r.top = IMX214_PIXEL_ARRAY_TOP;
756 sel->r.left = IMX214_PIXEL_ARRAY_LEFT;
757 sel->r.width = IMX214_PIXEL_ARRAY_WIDTH;
758 sel->r.height = IMX214_PIXEL_ARRAY_HEIGHT;
759 return 0;
760 }
761
762 return -EINVAL;
763 }
764
imx214_entity_init_state(struct v4l2_subdev * subdev,struct v4l2_subdev_state * sd_state)765 static int imx214_entity_init_state(struct v4l2_subdev *subdev,
766 struct v4l2_subdev_state *sd_state)
767 {
768 struct v4l2_subdev_format fmt = { };
769
770 fmt.which = sd_state ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
771 fmt.format.code = MEDIA_BUS_FMT_SRGGB10_1X10;
772 fmt.format.width = imx214_modes[0].width;
773 fmt.format.height = imx214_modes[0].height;
774
775 imx214_set_format(subdev, sd_state, &fmt);
776
777 return 0;
778 }
779
imx214_update_digital_gain(struct imx214 * imx214,u32 val)780 static int imx214_update_digital_gain(struct imx214 *imx214, u32 val)
781 {
782 int ret = 0;
783
784 cci_write(imx214->regmap, IMX214_REG_DIG_GAIN_GREENR, val, &ret);
785 cci_write(imx214->regmap, IMX214_REG_DIG_GAIN_RED, val, &ret);
786 cci_write(imx214->regmap, IMX214_REG_DIG_GAIN_BLUE, val, &ret);
787 cci_write(imx214->regmap, IMX214_REG_DIG_GAIN_GREENB, val, &ret);
788
789 return ret;
790 }
791
imx214_set_ctrl(struct v4l2_ctrl * ctrl)792 static int imx214_set_ctrl(struct v4l2_ctrl *ctrl)
793 {
794 struct imx214 *imx214 = container_of(ctrl->handler,
795 struct imx214, ctrls);
796 const struct v4l2_mbus_framefmt *format = NULL;
797 struct v4l2_subdev_state *state;
798 int ret = 0;
799
800 if (ctrl->id == V4L2_CID_VBLANK) {
801 int exposure_max, exposure_def;
802
803 state = v4l2_subdev_get_locked_active_state(&imx214->sd);
804 format = v4l2_subdev_state_get_format(state, 0);
805
806 /* Update max exposure while meeting expected vblanking */
807 exposure_max =
808 format->height + ctrl->val - IMX214_EXPOSURE_OFFSET;
809 exposure_def = min(exposure_max, IMX214_EXPOSURE_DEFAULT);
810 __v4l2_ctrl_modify_range(imx214->exposure,
811 imx214->exposure->minimum,
812 exposure_max, imx214->exposure->step,
813 exposure_def);
814 }
815
816 /*
817 * Applying V4L2 control value only happens
818 * when power is up for streaming
819 */
820 if (!pm_runtime_get_if_in_use(imx214->dev))
821 return 0;
822
823 switch (ctrl->id) {
824 case V4L2_CID_ANALOGUE_GAIN:
825 cci_write(imx214->regmap, IMX214_REG_ANALOG_GAIN,
826 ctrl->val, &ret);
827 cci_write(imx214->regmap, IMX214_REG_SHORT_ANALOG_GAIN,
828 ctrl->val, &ret);
829 break;
830 case V4L2_CID_DIGITAL_GAIN:
831 ret = imx214_update_digital_gain(imx214, ctrl->val);
832 break;
833 case V4L2_CID_EXPOSURE:
834 cci_write(imx214->regmap, IMX214_REG_EXPOSURE, ctrl->val, &ret);
835 break;
836 case V4L2_CID_HFLIP:
837 case V4L2_CID_VFLIP:
838 cci_write(imx214->regmap, IMX214_REG_ORIENTATION,
839 imx214->hflip->val | imx214->vflip->val << 1, &ret);
840 break;
841 case V4L2_CID_VBLANK:
842 cci_write(imx214->regmap, IMX214_REG_FRM_LENGTH_LINES,
843 format->height + ctrl->val, &ret);
844 break;
845 case V4L2_CID_TEST_PATTERN:
846 cci_write(imx214->regmap, IMX214_REG_TEST_PATTERN,
847 imx214_test_pattern_val[ctrl->val], &ret);
848 break;
849 case V4L2_CID_TEST_PATTERN_RED:
850 cci_write(imx214->regmap, IMX214_REG_TESTP_RED,
851 ctrl->val, &ret);
852 break;
853 case V4L2_CID_TEST_PATTERN_GREENR:
854 cci_write(imx214->regmap, IMX214_REG_TESTP_GREENR,
855 ctrl->val, &ret);
856 break;
857 case V4L2_CID_TEST_PATTERN_BLUE:
858 cci_write(imx214->regmap, IMX214_REG_TESTP_BLUE,
859 ctrl->val, &ret);
860 break;
861 case V4L2_CID_TEST_PATTERN_GREENB:
862 cci_write(imx214->regmap, IMX214_REG_TESTP_GREENB,
863 ctrl->val, &ret);
864 break;
865 default:
866 ret = -EINVAL;
867 }
868
869 pm_runtime_put(imx214->dev);
870
871 return ret;
872 }
873
874 static const struct v4l2_ctrl_ops imx214_ctrl_ops = {
875 .s_ctrl = imx214_set_ctrl,
876 };
877
imx214_ctrls_init(struct imx214 * imx214)878 static int imx214_ctrls_init(struct imx214 *imx214)
879 {
880 static const s64 link_freq[] = {
881 IMX214_DEFAULT_LINK_FREQ
882 };
883 static const struct v4l2_area unit_size = {
884 .width = 1120,
885 .height = 1120,
886 };
887 const struct imx214_mode *mode = &imx214_modes[0];
888 struct v4l2_fwnode_device_properties props;
889 struct v4l2_ctrl_handler *ctrl_hdlr;
890 int exposure_max, exposure_def;
891 int hblank;
892 int i, ret;
893
894 ret = v4l2_fwnode_device_parse(imx214->dev, &props);
895 if (ret < 0)
896 return ret;
897
898 ctrl_hdlr = &imx214->ctrls;
899 ret = v4l2_ctrl_handler_init(&imx214->ctrls, 13);
900 if (ret)
901 return ret;
902
903 imx214->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, NULL,
904 V4L2_CID_PIXEL_RATE, 0,
905 IMX214_DEFAULT_PIXEL_RATE, 1,
906 IMX214_DEFAULT_PIXEL_RATE);
907
908 imx214->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, NULL,
909 V4L2_CID_LINK_FREQ,
910 ARRAY_SIZE(link_freq) - 1,
911 0, link_freq);
912 if (imx214->link_freq)
913 imx214->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
914
915 /*
916 * WARNING!
917 * Values obtained reverse engineering blobs and/or devices.
918 * Ranges and functionality might be wrong.
919 *
920 * Sony, please release some register set documentation for the
921 * device.
922 *
923 * Yours sincerely, Ricardo.
924 */
925
926 /* Initial vblank/hblank/exposure parameters based on current mode */
927 imx214->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &imx214_ctrl_ops,
928 V4L2_CID_VBLANK, IMX214_VBLANK_MIN,
929 IMX214_VTS_MAX - mode->height, 2,
930 mode->vts_def - mode->height);
931
932 hblank = IMX214_PPL_DEFAULT - mode->width;
933 imx214->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &imx214_ctrl_ops,
934 V4L2_CID_HBLANK, hblank, hblank,
935 1, hblank);
936 if (imx214->hblank)
937 imx214->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
938
939 exposure_max = mode->vts_def - IMX214_EXPOSURE_OFFSET;
940 exposure_def = min(exposure_max, IMX214_EXPOSURE_DEFAULT);
941 imx214->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &imx214_ctrl_ops,
942 V4L2_CID_EXPOSURE,
943 IMX214_EXPOSURE_MIN,
944 exposure_max,
945 IMX214_EXPOSURE_STEP,
946 exposure_def);
947
948 v4l2_ctrl_new_std(ctrl_hdlr, &imx214_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
949 IMX214_ANA_GAIN_MIN, IMX214_ANA_GAIN_MAX,
950 IMX214_ANA_GAIN_STEP, IMX214_ANA_GAIN_DEFAULT);
951
952 v4l2_ctrl_new_std(ctrl_hdlr, &imx214_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
953 IMX214_DGTL_GAIN_MIN, IMX214_DGTL_GAIN_MAX,
954 IMX214_DGTL_GAIN_STEP, IMX214_DGTL_GAIN_DEFAULT);
955
956 imx214->hflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx214_ctrl_ops,
957 V4L2_CID_HFLIP, 0, 1, 1, 0);
958 if (imx214->hflip)
959 imx214->hflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;
960
961 imx214->vflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx214_ctrl_ops,
962 V4L2_CID_VFLIP, 0, 1, 1, 0);
963 if (imx214->vflip)
964 imx214->vflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;
965
966 v4l2_ctrl_cluster(2, &imx214->hflip);
967
968 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &imx214_ctrl_ops,
969 V4L2_CID_TEST_PATTERN,
970 ARRAY_SIZE(imx214_test_pattern_menu) - 1,
971 0, 0, imx214_test_pattern_menu);
972 for (i = 0; i < 4; i++) {
973 /*
974 * The assumption is that
975 * V4L2_CID_TEST_PATTERN_GREENR == V4L2_CID_TEST_PATTERN_RED + 1
976 * V4L2_CID_TEST_PATTERN_BLUE == V4L2_CID_TEST_PATTERN_RED + 2
977 * V4L2_CID_TEST_PATTERN_GREENB == V4L2_CID_TEST_PATTERN_RED + 3
978 */
979 v4l2_ctrl_new_std(ctrl_hdlr, &imx214_ctrl_ops,
980 V4L2_CID_TEST_PATTERN_RED + i,
981 IMX214_TESTP_COLOUR_MIN,
982 IMX214_TESTP_COLOUR_MAX,
983 IMX214_TESTP_COLOUR_STEP,
984 IMX214_TESTP_COLOUR_MAX);
985 /* The "Solid color" pattern is white by default */
986 }
987
988 imx214->unit_size = v4l2_ctrl_new_std_compound(ctrl_hdlr,
989 NULL,
990 V4L2_CID_UNIT_CELL_SIZE,
991 v4l2_ctrl_ptr_create((void *)&unit_size),
992 v4l2_ctrl_ptr_create(NULL),
993 v4l2_ctrl_ptr_create(NULL));
994
995 v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &imx214_ctrl_ops, &props);
996
997 ret = ctrl_hdlr->error;
998 if (ret) {
999 v4l2_ctrl_handler_free(ctrl_hdlr);
1000 dev_err(imx214->dev, "failed to add controls: %d\n", ret);
1001 return ret;
1002 }
1003
1004 imx214->sd.ctrl_handler = ctrl_hdlr;
1005
1006 return 0;
1007 };
1008
imx214_start_streaming(struct imx214 * imx214)1009 static int imx214_start_streaming(struct imx214 *imx214)
1010 {
1011 const struct v4l2_mbus_framefmt *fmt;
1012 struct v4l2_subdev_state *state;
1013 const struct imx214_mode *mode;
1014 int ret;
1015
1016 ret = cci_multi_reg_write(imx214->regmap, mode_table_common,
1017 ARRAY_SIZE(mode_table_common), NULL);
1018 if (ret < 0) {
1019 dev_err(imx214->dev, "could not sent common table %d\n", ret);
1020 return ret;
1021 }
1022
1023 ret = cci_write(imx214->regmap, IMX214_REG_CSI_LANE_MODE,
1024 IMX214_CSI_4_LANE_MODE, NULL);
1025 if (ret) {
1026 dev_err(imx214->dev, "failed to configure lanes\n");
1027 return ret;
1028 }
1029
1030 state = v4l2_subdev_get_locked_active_state(&imx214->sd);
1031 fmt = v4l2_subdev_state_get_format(state, 0);
1032 mode = v4l2_find_nearest_size(imx214_modes, ARRAY_SIZE(imx214_modes),
1033 width, height, fmt->width, fmt->height);
1034 ret = cci_multi_reg_write(imx214->regmap, mode->reg_table,
1035 mode->num_of_regs, NULL);
1036 if (ret < 0) {
1037 dev_err(imx214->dev, "could not sent mode table %d\n", ret);
1038 return ret;
1039 }
1040
1041 usleep_range(10000, 10500);
1042
1043 cci_write(imx214->regmap, IMX214_REG_TEMP_SENSOR_CONTROL, 0x01, NULL);
1044
1045 ret = __v4l2_ctrl_handler_setup(&imx214->ctrls);
1046 if (ret < 0) {
1047 dev_err(imx214->dev, "could not sync v4l2 controls\n");
1048 return ret;
1049 }
1050 ret = cci_write(imx214->regmap, IMX214_REG_MODE_SELECT,
1051 IMX214_MODE_STREAMING, NULL);
1052 if (ret < 0)
1053 dev_err(imx214->dev, "could not sent start table %d\n", ret);
1054
1055 return ret;
1056 }
1057
imx214_stop_streaming(struct imx214 * imx214)1058 static int imx214_stop_streaming(struct imx214 *imx214)
1059 {
1060 int ret;
1061
1062 ret = cci_write(imx214->regmap, IMX214_REG_MODE_SELECT,
1063 IMX214_MODE_STANDBY, NULL);
1064 if (ret < 0)
1065 dev_err(imx214->dev, "could not sent stop table %d\n", ret);
1066
1067 return ret;
1068 }
1069
imx214_s_stream(struct v4l2_subdev * subdev,int enable)1070 static int imx214_s_stream(struct v4l2_subdev *subdev, int enable)
1071 {
1072 struct imx214 *imx214 = to_imx214(subdev);
1073 struct v4l2_subdev_state *state;
1074 int ret;
1075
1076 if (enable) {
1077 ret = pm_runtime_resume_and_get(imx214->dev);
1078 if (ret < 0)
1079 return ret;
1080
1081 state = v4l2_subdev_lock_and_get_active_state(subdev);
1082 ret = imx214_start_streaming(imx214);
1083 v4l2_subdev_unlock_state(state);
1084 if (ret < 0)
1085 goto err_rpm_put;
1086 } else {
1087 ret = imx214_stop_streaming(imx214);
1088 if (ret < 0)
1089 goto err_rpm_put;
1090 pm_runtime_put(imx214->dev);
1091 }
1092
1093 return 0;
1094
1095 err_rpm_put:
1096 pm_runtime_put(imx214->dev);
1097 return ret;
1098 }
1099
imx214_get_frame_interval(struct v4l2_subdev * subdev,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_interval * fival)1100 static int imx214_get_frame_interval(struct v4l2_subdev *subdev,
1101 struct v4l2_subdev_state *sd_state,
1102 struct v4l2_subdev_frame_interval *fival)
1103 {
1104 /*
1105 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2
1106 * subdev active state API.
1107 */
1108 if (fival->which != V4L2_SUBDEV_FORMAT_ACTIVE)
1109 return -EINVAL;
1110
1111 fival->interval.numerator = 1;
1112 fival->interval.denominator = IMX214_FPS;
1113
1114 return 0;
1115 }
1116
1117 /*
1118 * Raw sensors should be using the VBLANK and HBLANK controls to determine
1119 * the frame rate. However this driver was initially added using the
1120 * [S|G|ENUM]_FRAME_INTERVAL ioctls with a fixed rate of 30fps.
1121 * Retain the frame_interval ops for backwards compatibility, but they do
1122 * nothing.
1123 */
imx214_enum_frame_interval(struct v4l2_subdev * subdev,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_interval_enum * fie)1124 static int imx214_enum_frame_interval(struct v4l2_subdev *subdev,
1125 struct v4l2_subdev_state *sd_state,
1126 struct v4l2_subdev_frame_interval_enum *fie)
1127 {
1128 struct imx214 *imx214 = to_imx214(subdev);
1129 const struct imx214_mode *mode;
1130
1131 dev_warn_once(imx214->dev, "frame_interval functions return an unreliable value for compatibility reasons. Use the VBLANK and HBLANK controls to determine the correct frame rate.\n");
1132
1133 if (fie->index != 0)
1134 return -EINVAL;
1135
1136 mode = v4l2_find_nearest_size(imx214_modes,
1137 ARRAY_SIZE(imx214_modes), width, height,
1138 fie->width, fie->height);
1139
1140 fie->code = imx214_get_format_code(imx214);
1141 fie->width = mode->width;
1142 fie->height = mode->height;
1143 fie->interval.numerator = 1;
1144 fie->interval.denominator = IMX214_FPS;
1145
1146 return 0;
1147 }
1148
1149 static const struct v4l2_subdev_video_ops imx214_video_ops = {
1150 .s_stream = imx214_s_stream,
1151 };
1152
1153 static const struct v4l2_subdev_pad_ops imx214_subdev_pad_ops = {
1154 .enum_mbus_code = imx214_enum_mbus_code,
1155 .enum_frame_size = imx214_enum_frame_size,
1156 .enum_frame_interval = imx214_enum_frame_interval,
1157 .get_fmt = v4l2_subdev_get_fmt,
1158 .set_fmt = imx214_set_format,
1159 .get_selection = imx214_get_selection,
1160 .get_frame_interval = imx214_get_frame_interval,
1161 .set_frame_interval = imx214_get_frame_interval,
1162 };
1163
1164 static const struct v4l2_subdev_ops imx214_subdev_ops = {
1165 .core = &imx214_core_ops,
1166 .video = &imx214_video_ops,
1167 .pad = &imx214_subdev_pad_ops,
1168 };
1169
1170 static const struct v4l2_subdev_internal_ops imx214_internal_ops = {
1171 .init_state = imx214_entity_init_state,
1172 };
1173
imx214_get_regulators(struct device * dev,struct imx214 * imx214)1174 static int imx214_get_regulators(struct device *dev, struct imx214 *imx214)
1175 {
1176 unsigned int i;
1177
1178 for (i = 0; i < IMX214_NUM_SUPPLIES; i++)
1179 imx214->supplies[i].supply = imx214_supply_name[i];
1180
1181 return devm_regulator_bulk_get(dev, IMX214_NUM_SUPPLIES,
1182 imx214->supplies);
1183 }
1184
1185 /* Verify chip ID */
imx214_identify_module(struct imx214 * imx214)1186 static int imx214_identify_module(struct imx214 *imx214)
1187 {
1188 struct i2c_client *client = v4l2_get_subdevdata(&imx214->sd);
1189 int ret;
1190 u64 val;
1191
1192 ret = cci_read(imx214->regmap, IMX214_REG_CHIP_ID, &val, NULL);
1193 if (ret)
1194 return dev_err_probe(&client->dev, ret,
1195 "failed to read chip id %x\n",
1196 IMX214_CHIP_ID);
1197
1198 if (val != IMX214_CHIP_ID)
1199 return dev_err_probe(&client->dev, -EIO,
1200 "chip id mismatch: %x!=%llx\n",
1201 IMX214_CHIP_ID, val);
1202
1203 return 0;
1204 }
1205
imx214_parse_fwnode(struct device * dev)1206 static int imx214_parse_fwnode(struct device *dev)
1207 {
1208 struct fwnode_handle *endpoint;
1209 struct v4l2_fwnode_endpoint bus_cfg = {
1210 .bus_type = V4L2_MBUS_CSI2_DPHY,
1211 };
1212 unsigned int i;
1213 int ret;
1214
1215 endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(dev), NULL);
1216 if (!endpoint)
1217 return dev_err_probe(dev, -EINVAL, "endpoint node not found\n");
1218
1219 ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, &bus_cfg);
1220 if (ret) {
1221 dev_err_probe(dev, ret, "parsing endpoint node failed\n");
1222 goto done;
1223 }
1224
1225 /* Check the number of MIPI CSI2 data lanes */
1226 if (bus_cfg.bus.mipi_csi2.num_data_lanes != 4) {
1227 ret = dev_err_probe(dev, -EINVAL,
1228 "only 4 data lanes are currently supported\n");
1229 goto done;
1230 }
1231
1232 if (bus_cfg.nr_of_link_frequencies != 1)
1233 dev_warn(dev, "Only one link-frequency supported, please review your DT. Continuing anyway\n");
1234
1235 for (i = 0; i < bus_cfg.nr_of_link_frequencies; i++) {
1236 if (bus_cfg.link_frequencies[i] == IMX214_DEFAULT_LINK_FREQ)
1237 break;
1238 if (bus_cfg.link_frequencies[i] ==
1239 IMX214_DEFAULT_LINK_FREQ_LEGACY) {
1240 dev_warn(dev,
1241 "link-frequencies %d not supported, please review your DT. Continuing anyway\n",
1242 IMX214_DEFAULT_LINK_FREQ);
1243 break;
1244 }
1245 }
1246
1247 if (i == bus_cfg.nr_of_link_frequencies)
1248 ret = dev_err_probe(dev, -EINVAL,
1249 "link-frequencies %d not supported, please review your DT\n",
1250 IMX214_DEFAULT_LINK_FREQ);
1251
1252 done:
1253 v4l2_fwnode_endpoint_free(&bus_cfg);
1254 fwnode_handle_put(endpoint);
1255 return ret;
1256 }
1257
imx214_probe(struct i2c_client * client)1258 static int imx214_probe(struct i2c_client *client)
1259 {
1260 struct device *dev = &client->dev;
1261 struct imx214 *imx214;
1262 int ret;
1263
1264 ret = imx214_parse_fwnode(dev);
1265 if (ret)
1266 return ret;
1267
1268 imx214 = devm_kzalloc(dev, sizeof(*imx214), GFP_KERNEL);
1269 if (!imx214)
1270 return -ENOMEM;
1271
1272 imx214->dev = dev;
1273
1274 imx214->xclk = devm_clk_get(dev, NULL);
1275 if (IS_ERR(imx214->xclk))
1276 return dev_err_probe(dev, PTR_ERR(imx214->xclk),
1277 "failed to get xclk\n");
1278
1279 ret = clk_set_rate(imx214->xclk, IMX214_DEFAULT_CLK_FREQ);
1280 if (ret)
1281 return dev_err_probe(dev, ret,
1282 "failed to set xclk frequency\n");
1283
1284 ret = imx214_get_regulators(dev, imx214);
1285 if (ret < 0)
1286 return dev_err_probe(dev, ret, "failed to get regulators\n");
1287
1288 imx214->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW);
1289 if (IS_ERR(imx214->enable_gpio))
1290 return dev_err_probe(dev, PTR_ERR(imx214->enable_gpio),
1291 "failed to get enable gpio\n");
1292
1293 imx214->regmap = devm_cci_regmap_init_i2c(client, 16);
1294 if (IS_ERR(imx214->regmap))
1295 return dev_err_probe(dev, PTR_ERR(imx214->regmap),
1296 "failed to initialize CCI\n");
1297
1298 v4l2_i2c_subdev_init(&imx214->sd, client, &imx214_subdev_ops);
1299 imx214->sd.internal_ops = &imx214_internal_ops;
1300
1301 /*
1302 * Enable power initially, to avoid warnings
1303 * from clk_disable on power_off
1304 */
1305 imx214_power_on(imx214->dev);
1306
1307 ret = imx214_identify_module(imx214);
1308 if (ret)
1309 goto error_power_off;
1310
1311 ret = imx214_ctrls_init(imx214);
1312 if (ret < 0)
1313 goto error_power_off;
1314
1315 imx214->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1316 imx214->pad.flags = MEDIA_PAD_FL_SOURCE;
1317 imx214->sd.dev = &client->dev;
1318 imx214->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1319
1320 ret = media_entity_pads_init(&imx214->sd.entity, 1, &imx214->pad);
1321 if (ret < 0) {
1322 dev_err_probe(dev, ret, "failed to init entity pads\n");
1323 goto free_ctrl;
1324 }
1325
1326 imx214->sd.state_lock = imx214->ctrls.lock;
1327 ret = v4l2_subdev_init_finalize(&imx214->sd);
1328 if (ret < 0) {
1329 dev_err_probe(dev, ret, "subdev init error\n");
1330 goto free_entity;
1331 }
1332
1333 pm_runtime_set_active(imx214->dev);
1334 pm_runtime_enable(imx214->dev);
1335
1336 ret = v4l2_async_register_subdev_sensor(&imx214->sd);
1337 if (ret < 0) {
1338 dev_err_probe(dev, ret,
1339 "failed to register sensor sub-device\n");
1340 goto error_subdev_cleanup;
1341 }
1342
1343 pm_runtime_idle(imx214->dev);
1344
1345 return 0;
1346
1347 error_subdev_cleanup:
1348 pm_runtime_disable(imx214->dev);
1349 pm_runtime_set_suspended(&client->dev);
1350 v4l2_subdev_cleanup(&imx214->sd);
1351
1352 free_entity:
1353 media_entity_cleanup(&imx214->sd.entity);
1354
1355 free_ctrl:
1356 v4l2_ctrl_handler_free(&imx214->ctrls);
1357
1358 error_power_off:
1359 imx214_power_off(imx214->dev);
1360
1361 return ret;
1362 }
1363
imx214_remove(struct i2c_client * client)1364 static void imx214_remove(struct i2c_client *client)
1365 {
1366 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1367 struct imx214 *imx214 = to_imx214(sd);
1368
1369 v4l2_async_unregister_subdev(&imx214->sd);
1370 v4l2_subdev_cleanup(sd);
1371 media_entity_cleanup(&imx214->sd.entity);
1372 v4l2_ctrl_handler_free(&imx214->ctrls);
1373 pm_runtime_disable(&client->dev);
1374 if (!pm_runtime_status_suspended(&client->dev)) {
1375 imx214_power_off(imx214->dev);
1376 pm_runtime_set_suspended(&client->dev);
1377 }
1378 }
1379
1380 static const struct of_device_id imx214_of_match[] = {
1381 { .compatible = "sony,imx214" },
1382 { }
1383 };
1384 MODULE_DEVICE_TABLE(of, imx214_of_match);
1385
1386 static const struct dev_pm_ops imx214_pm_ops = {
1387 SET_RUNTIME_PM_OPS(imx214_power_off, imx214_power_on, NULL)
1388 };
1389
1390 static struct i2c_driver imx214_i2c_driver = {
1391 .driver = {
1392 .of_match_table = imx214_of_match,
1393 .pm = &imx214_pm_ops,
1394 .name = "imx214",
1395 },
1396 .probe = imx214_probe,
1397 .remove = imx214_remove,
1398 };
1399
1400 module_i2c_driver(imx214_i2c_driver);
1401
1402 MODULE_DESCRIPTION("Sony IMX214 Camera driver");
1403 MODULE_AUTHOR("Ricardo Ribalda <ribalda@kernel.org>");
1404 MODULE_LICENSE("GPL v2");
1405