1 // SPDX-License-Identifier: GPL-2.0
2
3 #include <linux/delay.h>
4 #include <linux/device.h>
5 #include <linux/err.h>
6 #include <linux/errno.h>
7 #include <linux/gpio/consumer.h>
8 #include <linux/kernel.h>
9 #include <linux/mod_devicetable.h>
10 #include <linux/module.h>
11 #include <linux/property.h>
12 #include <linux/regulator/consumer.h>
13
14 #include <drm/drm_mipi_dsi.h>
15 #include <drm/drm_modes.h>
16 #include <drm/drm_panel.h>
17 #include <drm/drm_probe_helper.h>
18
19 #include <video/mipi_display.h>
20
21 struct panel_desc {
22 const struct drm_display_mode *display_mode;
23 unsigned long mode_flags;
24 enum mipi_dsi_pixel_format format;
25 unsigned int lanes;
26 void (*init_sequence)(struct mipi_dsi_multi_context *ctx);
27 };
28
29 struct ili9806e_panel {
30 struct drm_panel panel;
31 struct mipi_dsi_device *dsi;
32 struct gpio_desc *reset_gpio;
33 struct regulator_bulk_data supplies[2];
34 const struct panel_desc *desc;
35 enum drm_panel_orientation orientation;
36 };
37
38 static const char * const regulator_names[] = {
39 "vdd",
40 "vccio",
41 };
42
to_ili9806e_panel(struct drm_panel * panel)43 static inline struct ili9806e_panel *to_ili9806e_panel(struct drm_panel *panel)
44 {
45 return container_of(panel, struct ili9806e_panel, panel);
46 }
47
ili9806e_power_on(struct ili9806e_panel * ctx)48 static int ili9806e_power_on(struct ili9806e_panel *ctx)
49 {
50 struct mipi_dsi_device *dsi = ctx->dsi;
51 int ret;
52
53 gpiod_set_value(ctx->reset_gpio, 1);
54
55 ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
56 if (ret < 0) {
57 dev_err(&dsi->dev, "regulator bulk enable failed: %d\n", ret);
58 return ret;
59 }
60
61 usleep_range(10000, 20000);
62 gpiod_set_value(ctx->reset_gpio, 0);
63 usleep_range(10000, 20000);
64
65 return 0;
66 }
67
ili9806e_power_off(struct ili9806e_panel * ctx)68 static int ili9806e_power_off(struct ili9806e_panel *ctx)
69 {
70 struct mipi_dsi_device *dsi = ctx->dsi;
71 int ret;
72
73 gpiod_set_value(ctx->reset_gpio, 1);
74
75 ret = regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
76 if (ret)
77 dev_err(&dsi->dev, "regulator bulk disable failed: %d\n", ret);
78
79 return ret;
80 }
81
ili9806e_on(struct ili9806e_panel * ili9806e)82 static int ili9806e_on(struct ili9806e_panel *ili9806e)
83 {
84 struct mipi_dsi_multi_context ctx = { .dsi = ili9806e->dsi };
85
86 if (ili9806e->desc->init_sequence)
87 ili9806e->desc->init_sequence(&ctx);
88
89 mipi_dsi_dcs_exit_sleep_mode_multi(&ctx);
90 mipi_dsi_msleep(&ctx, 120);
91 mipi_dsi_dcs_set_display_on_multi(&ctx);
92
93 return ctx.accum_err;
94 }
95
ili9806e_off(struct ili9806e_panel * panel)96 static int ili9806e_off(struct ili9806e_panel *panel)
97 {
98 struct mipi_dsi_multi_context ctx = { .dsi = panel->dsi };
99
100 mipi_dsi_dcs_set_display_off_multi(&ctx);
101 mipi_dsi_dcs_enter_sleep_mode_multi(&ctx);
102 mipi_dsi_msleep(&ctx, 120);
103
104 return ctx.accum_err;
105 }
106
ili9806e_prepare(struct drm_panel * panel)107 static int ili9806e_prepare(struct drm_panel *panel)
108 {
109 struct ili9806e_panel *ctx = to_ili9806e_panel(panel);
110 int ret;
111
112 ret = ili9806e_power_on(ctx);
113 if (ret < 0)
114 return ret;
115
116 ret = ili9806e_on(ctx);
117 if (ret < 0) {
118 ili9806e_power_off(ctx);
119 return ret;
120 }
121
122 return 0;
123 }
124
ili9806e_unprepare(struct drm_panel * panel)125 static int ili9806e_unprepare(struct drm_panel *panel)
126 {
127 struct ili9806e_panel *ctx = to_ili9806e_panel(panel);
128 struct mipi_dsi_device *dsi = ctx->dsi;
129 int ret;
130
131 ili9806e_off(ctx);
132
133 ret = ili9806e_power_off(ctx);
134 if (ret < 0)
135 dev_err(&dsi->dev, "power off failed: %d\n", ret);
136
137 return ret;
138 }
139
ili9806e_get_modes(struct drm_panel * panel,struct drm_connector * connector)140 static int ili9806e_get_modes(struct drm_panel *panel,
141 struct drm_connector *connector)
142 {
143 struct ili9806e_panel *ctx = to_ili9806e_panel(panel);
144 const struct drm_display_mode *mode = ctx->desc->display_mode;
145
146 return drm_connector_helper_get_modes_fixed(connector, mode);
147 }
148
ili9806e_get_orientation(struct drm_panel * panel)149 static enum drm_panel_orientation ili9806e_get_orientation(struct drm_panel *panel)
150 {
151 struct ili9806e_panel *ctx = to_ili9806e_panel(panel);
152
153 return ctx->orientation;
154 }
155
156 static const struct drm_panel_funcs ili9806e_funcs = {
157 .prepare = ili9806e_prepare,
158 .unprepare = ili9806e_unprepare,
159 .get_modes = ili9806e_get_modes,
160 .get_orientation = ili9806e_get_orientation,
161 };
162
ili9806e_dsi_probe(struct mipi_dsi_device * dsi)163 static int ili9806e_dsi_probe(struct mipi_dsi_device *dsi)
164 {
165 struct device *dev = &dsi->dev;
166 struct ili9806e_panel *ctx;
167 int i, ret;
168
169 ctx = devm_drm_panel_alloc(dev, struct ili9806e_panel, panel, &ili9806e_funcs,
170 DRM_MODE_CONNECTOR_DSI);
171 if (IS_ERR(ctx))
172 return PTR_ERR(ctx);
173
174 ctx->desc = device_get_match_data(dev);
175
176 for (i = 0; i < ARRAY_SIZE(ctx->supplies); i++)
177 ctx->supplies[i].supply = regulator_names[i];
178
179 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ctx->supplies),
180 ctx->supplies);
181 if (ret < 0)
182 return ret;
183
184 ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
185 if (IS_ERR(ctx->reset_gpio))
186 return dev_err_probe(dev, PTR_ERR(ctx->reset_gpio),
187 "Failed to get reset-gpios\n");
188
189 mipi_dsi_set_drvdata(dsi, ctx);
190 ctx->dsi = dsi;
191
192 dsi->mode_flags = ctx->desc->mode_flags;
193 dsi->format = ctx->desc->format;
194 dsi->lanes = ctx->desc->lanes;
195
196 ret = of_drm_get_panel_orientation(dev->of_node, &ctx->orientation);
197 if (ret)
198 return dev_err_probe(dev, ret, "Failed to get orientation\n");
199
200 ret = drm_panel_of_backlight(&ctx->panel);
201 if (ret)
202 return dev_err_probe(dev, ret, "Failed to get backlight\n");
203
204 ctx->panel.prepare_prev_first = true;
205 drm_panel_add(&ctx->panel);
206
207 ret = mipi_dsi_attach(dsi);
208 if (ret < 0) {
209 dev_err_probe(dev, ret, "Failed to attach to DSI host\n");
210 drm_panel_remove(&ctx->panel);
211 return ret;
212 }
213
214 return 0;
215 }
216
ili9806e_dsi_remove(struct mipi_dsi_device * dsi)217 static void ili9806e_dsi_remove(struct mipi_dsi_device *dsi)
218 {
219 struct ili9806e_panel *ctx = mipi_dsi_get_drvdata(dsi);
220
221 mipi_dsi_detach(dsi);
222 drm_panel_remove(&ctx->panel);
223 }
224
com35h3p70ulc_init(struct mipi_dsi_multi_context * ctx)225 static void com35h3p70ulc_init(struct mipi_dsi_multi_context *ctx)
226 {
227 /* Switch to page 1 */
228 mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0xff, 0x98, 0x06, 0x04, 0x01);
229 /* Interface Settings */
230 mipi_dsi_dcs_write_seq_multi(ctx, 0x08, 0x18);
231 mipi_dsi_dcs_write_seq_multi(ctx, 0x21, 0x01);
232 /* Panel Settings */
233 mipi_dsi_dcs_write_seq_multi(ctx, 0x30, 0x03);
234 mipi_dsi_dcs_write_seq_multi(ctx, 0x31, 0x00);
235 mipi_dsi_dcs_write_seq_multi(ctx, 0x60, 0x0d);
236 mipi_dsi_dcs_write_seq_multi(ctx, 0x61, 0x08);
237 mipi_dsi_dcs_write_seq_multi(ctx, 0x62, 0x08);
238 mipi_dsi_dcs_write_seq_multi(ctx, 0x63, 0x09);
239 /* Power Control */
240 mipi_dsi_dcs_write_seq_multi(ctx, 0x40, 0x30);
241 mipi_dsi_dcs_write_seq_multi(ctx, 0x41, 0x44);
242 mipi_dsi_dcs_write_seq_multi(ctx, 0x42, 0x00);
243 mipi_dsi_dcs_write_seq_multi(ctx, 0x43, 0x89);
244 mipi_dsi_dcs_write_seq_multi(ctx, 0x44, 0x8e);
245 mipi_dsi_dcs_write_seq_multi(ctx, 0x45, 0xd9);
246 mipi_dsi_dcs_write_seq_multi(ctx, 0x46, 0x33);
247 mipi_dsi_dcs_write_seq_multi(ctx, 0x47, 0x33);
248 mipi_dsi_dcs_write_seq_multi(ctx, 0x50, 0x90);
249 mipi_dsi_dcs_write_seq_multi(ctx, 0x51, 0x90);
250 mipi_dsi_dcs_write_seq_multi(ctx, 0x56, 0x00);
251 /* Gamma Settings */
252 mipi_dsi_dcs_write_seq_multi(ctx, 0xa0, 0x00);
253 mipi_dsi_dcs_write_seq_multi(ctx, 0xa1, 0x0c);
254 mipi_dsi_dcs_write_seq_multi(ctx, 0xa2, 0x13);
255 mipi_dsi_dcs_write_seq_multi(ctx, 0xa3, 0x0f);
256 mipi_dsi_dcs_write_seq_multi(ctx, 0xa4, 0x0a);
257 mipi_dsi_dcs_write_seq_multi(ctx, 0xa5, 0x0d);
258 mipi_dsi_dcs_write_seq_multi(ctx, 0xa6, 0x0c);
259 mipi_dsi_dcs_write_seq_multi(ctx, 0xa7, 0x0b);
260 mipi_dsi_dcs_write_seq_multi(ctx, 0xa8, 0x01);
261 mipi_dsi_dcs_write_seq_multi(ctx, 0xa9, 0x06);
262 mipi_dsi_dcs_write_seq_multi(ctx, 0xaa, 0x15);
263 mipi_dsi_dcs_write_seq_multi(ctx, 0xab, 0x07);
264 mipi_dsi_dcs_write_seq_multi(ctx, 0xac, 0x12);
265 mipi_dsi_dcs_write_seq_multi(ctx, 0xad, 0x28);
266 mipi_dsi_dcs_write_seq_multi(ctx, 0xae, 0x20);
267 mipi_dsi_dcs_write_seq_multi(ctx, 0xaf, 0x14);
268 mipi_dsi_dcs_write_seq_multi(ctx, 0xc0, 0x00);
269 mipi_dsi_dcs_write_seq_multi(ctx, 0xc1, 0x0c);
270 mipi_dsi_dcs_write_seq_multi(ctx, 0xc2, 0x13);
271 mipi_dsi_dcs_write_seq_multi(ctx, 0xc3, 0x0f);
272 mipi_dsi_dcs_write_seq_multi(ctx, 0xc4, 0x09);
273 mipi_dsi_dcs_write_seq_multi(ctx, 0xc5, 0x0d);
274 mipi_dsi_dcs_write_seq_multi(ctx, 0xc6, 0x0c);
275 mipi_dsi_dcs_write_seq_multi(ctx, 0xc7, 0x0b);
276 mipi_dsi_dcs_write_seq_multi(ctx, 0xc8, 0x01);
277 mipi_dsi_dcs_write_seq_multi(ctx, 0xc9, 0x06);
278 mipi_dsi_dcs_write_seq_multi(ctx, 0xca, 0x14);
279 mipi_dsi_dcs_write_seq_multi(ctx, 0xcb, 0x07);
280 mipi_dsi_dcs_write_seq_multi(ctx, 0xcc, 0x0f);
281 mipi_dsi_dcs_write_seq_multi(ctx, 0xcd, 0x21);
282 mipi_dsi_dcs_write_seq_multi(ctx, 0xce, 0x17);
283 mipi_dsi_dcs_write_seq_multi(ctx, 0xcf, 0x0a);
284
285 /* Switch to page 7 */
286 mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0xff, 0x98, 0x06, 0x04, 0x07);
287 /* Power Control */
288 mipi_dsi_dcs_write_seq_multi(ctx, 0x06, 0x00);
289 mipi_dsi_dcs_write_seq_multi(ctx, 0x18, 0x1d);
290 mipi_dsi_dcs_write_seq_multi(ctx, 0x17, 0x32);
291
292 /* Switch to page 6 */
293 mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0xff, 0x98, 0x06, 0x04, 0x06);
294 /* GIP settings */
295 mipi_dsi_dcs_write_seq_multi(ctx, 0x00, 0x20);
296 mipi_dsi_dcs_write_seq_multi(ctx, 0x01, 0x02);
297 mipi_dsi_dcs_write_seq_multi(ctx, 0x02, 0x00);
298 mipi_dsi_dcs_write_seq_multi(ctx, 0x03, 0x02);
299 mipi_dsi_dcs_write_seq_multi(ctx, 0x04, 0x01);
300 mipi_dsi_dcs_write_seq_multi(ctx, 0x05, 0x01);
301 mipi_dsi_dcs_write_seq_multi(ctx, 0x06, 0x88);
302 mipi_dsi_dcs_write_seq_multi(ctx, 0x07, 0x04);
303 mipi_dsi_dcs_write_seq_multi(ctx, 0x08, 0x03);
304 mipi_dsi_dcs_write_seq_multi(ctx, 0x09, 0x80);
305 mipi_dsi_dcs_write_seq_multi(ctx, 0x0a, 0x00);
306 mipi_dsi_dcs_write_seq_multi(ctx, 0x0b, 0x00);
307 mipi_dsi_dcs_write_seq_multi(ctx, 0x0c, 0x01);
308 mipi_dsi_dcs_write_seq_multi(ctx, 0x0d, 0x01);
309 mipi_dsi_dcs_write_seq_multi(ctx, 0x0e, 0x00);
310 mipi_dsi_dcs_write_seq_multi(ctx, 0x0f, 0x00);
311 mipi_dsi_dcs_write_seq_multi(ctx, 0x10, 0x55);
312 mipi_dsi_dcs_write_seq_multi(ctx, 0x11, 0x50);
313 mipi_dsi_dcs_write_seq_multi(ctx, 0x12, 0x01);
314 mipi_dsi_dcs_write_seq_multi(ctx, 0x13, 0x00);
315 mipi_dsi_dcs_write_seq_multi(ctx, 0x14, 0x00);
316 mipi_dsi_dcs_write_seq_multi(ctx, 0x15, 0x43);
317 mipi_dsi_dcs_write_seq_multi(ctx, 0x16, 0x0b);
318 mipi_dsi_dcs_write_seq_multi(ctx, 0x17, 0x00);
319 mipi_dsi_dcs_write_seq_multi(ctx, 0x18, 0x00);
320 mipi_dsi_dcs_write_seq_multi(ctx, 0x19, 0x10);
321 mipi_dsi_dcs_write_seq_multi(ctx, 0x1a, 0x00);
322 mipi_dsi_dcs_write_seq_multi(ctx, 0x1b, 0x00);
323 mipi_dsi_dcs_write_seq_multi(ctx, 0x1c, 0x00);
324 mipi_dsi_dcs_write_seq_multi(ctx, 0x1d, 0x00);
325 mipi_dsi_dcs_write_seq_multi(ctx, 0x20, 0x01);
326 mipi_dsi_dcs_write_seq_multi(ctx, 0x21, 0x23);
327 mipi_dsi_dcs_write_seq_multi(ctx, 0x22, 0x45);
328 mipi_dsi_dcs_write_seq_multi(ctx, 0x23, 0x67);
329 mipi_dsi_dcs_write_seq_multi(ctx, 0x24, 0x01);
330 mipi_dsi_dcs_write_seq_multi(ctx, 0x25, 0x23);
331 mipi_dsi_dcs_write_seq_multi(ctx, 0x26, 0x45);
332 mipi_dsi_dcs_write_seq_multi(ctx, 0x27, 0x67);
333 mipi_dsi_dcs_write_seq_multi(ctx, 0x30, 0x02);
334 mipi_dsi_dcs_write_seq_multi(ctx, 0x31, 0x22);
335 mipi_dsi_dcs_write_seq_multi(ctx, 0x32, 0x22);
336 mipi_dsi_dcs_write_seq_multi(ctx, 0x33, 0x88);
337 mipi_dsi_dcs_write_seq_multi(ctx, 0x34, 0xaa);
338 mipi_dsi_dcs_write_seq_multi(ctx, 0x35, 0xbb);
339 mipi_dsi_dcs_write_seq_multi(ctx, 0x36, 0x66);
340 mipi_dsi_dcs_write_seq_multi(ctx, 0x37, 0x22);
341 mipi_dsi_dcs_write_seq_multi(ctx, 0x38, 0x22);
342 mipi_dsi_dcs_write_seq_multi(ctx, 0x39, 0x22);
343 mipi_dsi_dcs_write_seq_multi(ctx, 0x3a, 0x22);
344 mipi_dsi_dcs_write_seq_multi(ctx, 0x3b, 0x22);
345 mipi_dsi_dcs_write_seq_multi(ctx, 0x3c, 0x22);
346 mipi_dsi_dcs_write_seq_multi(ctx, 0x3d, 0x22);
347 mipi_dsi_dcs_write_seq_multi(ctx, 0x3e, 0x22);
348 mipi_dsi_dcs_write_seq_multi(ctx, 0x3f, 0x22);
349 mipi_dsi_dcs_write_seq_multi(ctx, 0x40, 0x22);
350 mipi_dsi_dcs_write_seq_multi(ctx, 0x53, 0x12);
351
352 /* Switch to page 0 */
353 mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0xff, 0x98, 0x06, 0x04, 0x00);
354 /* Interface Pixel format */
355 mipi_dsi_dcs_write_seq_multi(ctx, 0x3a, 0x60);
356 };
357
358 static const struct drm_display_mode com35h3p70ulc_default_mode = {
359 .clock = 22400,
360 .hdisplay = 480,
361 .hsync_start = 480 + 16,
362 .hsync_end = 480 + 16 + 16,
363 .htotal = 480 + 16 + 16 + 16,
364 .vdisplay = 640,
365 .vsync_start = 640 + 52,
366 .vsync_end = 640 + 52 + 4,
367 .vtotal = 640 + 52 + 4 + 16,
368 .width_mm = 53,
369 .height_mm = 71,
370 };
371
372 static const struct panel_desc com35h3p70ulc_desc = {
373 .init_sequence = com35h3p70ulc_init,
374 .display_mode = &com35h3p70ulc_default_mode,
375 .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
376 MIPI_DSI_MODE_LPM,
377 .format = MIPI_DSI_FMT_RGB888,
378 .lanes = 2,
379 };
380
dmt028vghmcmi_1d_init(struct mipi_dsi_multi_context * ctx)381 static void dmt028vghmcmi_1d_init(struct mipi_dsi_multi_context *ctx)
382 {
383 mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0xff, 0x98, 0x06, 0x04, 0x01);
384 mipi_dsi_dcs_write_seq_multi(ctx, 0x08, 0x10);
385 mipi_dsi_dcs_write_seq_multi(ctx, 0x21, 0x01);
386 mipi_dsi_dcs_write_seq_multi(ctx, 0x30, 0x03);
387 mipi_dsi_dcs_write_seq_multi(ctx, 0x31, 0x00);
388 mipi_dsi_dcs_write_seq_multi(ctx, 0x60, 0x06);
389 mipi_dsi_dcs_write_seq_multi(ctx, 0x61, 0x00);
390 mipi_dsi_dcs_write_seq_multi(ctx, 0x62, 0x07);
391 mipi_dsi_dcs_write_seq_multi(ctx, 0x63, 0x00);
392 mipi_dsi_dcs_write_seq_multi(ctx, 0x40, 0x16);
393 mipi_dsi_dcs_write_seq_multi(ctx, 0x41, 0x44);
394 mipi_dsi_dcs_write_seq_multi(ctx, 0x42, 0x00);
395 mipi_dsi_dcs_write_seq_multi(ctx, 0x43, 0x83);
396 mipi_dsi_dcs_write_seq_multi(ctx, 0x44, 0x89);
397 mipi_dsi_dcs_write_seq_multi(ctx, 0x45, 0x8a);
398 mipi_dsi_dcs_write_seq_multi(ctx, 0x46, 0x44);
399 mipi_dsi_dcs_write_seq_multi(ctx, 0x47, 0x44);
400 mipi_dsi_dcs_write_seq_multi(ctx, 0x50, 0x78);
401 mipi_dsi_dcs_write_seq_multi(ctx, 0x51, 0x78);
402 mipi_dsi_dcs_write_seq_multi(ctx, 0x52, 0x00);
403 mipi_dsi_dcs_write_seq_multi(ctx, 0x53, 0x6c);
404 mipi_dsi_dcs_write_seq_multi(ctx, 0x54, 0x00);
405 mipi_dsi_dcs_write_seq_multi(ctx, 0x55, 0x6c);
406 mipi_dsi_dcs_write_seq_multi(ctx, 0x56, 0x00);
407 /* Gamma settings */
408 mipi_dsi_dcs_write_seq_multi(ctx, 0xa0, 0x00);
409 mipi_dsi_dcs_write_seq_multi(ctx, 0xa1, 0x09);
410 mipi_dsi_dcs_write_seq_multi(ctx, 0xa2, 0x14);
411 mipi_dsi_dcs_write_seq_multi(ctx, 0xa3, 0x09);
412 mipi_dsi_dcs_write_seq_multi(ctx, 0xa4, 0x05);
413 mipi_dsi_dcs_write_seq_multi(ctx, 0xa5, 0x0a);
414 mipi_dsi_dcs_write_seq_multi(ctx, 0xa6, 0x07);
415 mipi_dsi_dcs_write_seq_multi(ctx, 0xa7, 0x07);
416 mipi_dsi_dcs_write_seq_multi(ctx, 0xa8, 0x08);
417 mipi_dsi_dcs_write_seq_multi(ctx, 0xa9, 0x0b);
418 mipi_dsi_dcs_write_seq_multi(ctx, 0xaa, 0x0c);
419 mipi_dsi_dcs_write_seq_multi(ctx, 0xab, 0x05);
420 mipi_dsi_dcs_write_seq_multi(ctx, 0xac, 0x0a);
421 mipi_dsi_dcs_write_seq_multi(ctx, 0xad, 0x19);
422 mipi_dsi_dcs_write_seq_multi(ctx, 0xae, 0x0b);
423 mipi_dsi_dcs_write_seq_multi(ctx, 0xaf, 0x00);
424
425 mipi_dsi_dcs_write_seq_multi(ctx, 0xc0, 0x00);
426 mipi_dsi_dcs_write_seq_multi(ctx, 0xc1, 0x0c);
427 mipi_dsi_dcs_write_seq_multi(ctx, 0xc2, 0x14);
428 mipi_dsi_dcs_write_seq_multi(ctx, 0xc3, 0x11);
429 mipi_dsi_dcs_write_seq_multi(ctx, 0xc4, 0x05);
430 mipi_dsi_dcs_write_seq_multi(ctx, 0xc5, 0x0c);
431 mipi_dsi_dcs_write_seq_multi(ctx, 0xc6, 0x08);
432 mipi_dsi_dcs_write_seq_multi(ctx, 0xc7, 0x03);
433 mipi_dsi_dcs_write_seq_multi(ctx, 0xc8, 0x06);
434 mipi_dsi_dcs_write_seq_multi(ctx, 0xc9, 0x0a);
435 mipi_dsi_dcs_write_seq_multi(ctx, 0xca, 0x10);
436 mipi_dsi_dcs_write_seq_multi(ctx, 0xcb, 0x05);
437 mipi_dsi_dcs_write_seq_multi(ctx, 0xcc, 0x0d);
438 mipi_dsi_dcs_write_seq_multi(ctx, 0xcd, 0x15);
439 mipi_dsi_dcs_write_seq_multi(ctx, 0xce, 0x13);
440 mipi_dsi_dcs_write_seq_multi(ctx, 0xcf, 0x00);
441
442 mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0xff, 0x98, 0x06, 0x04, 0x07);
443 mipi_dsi_dcs_write_seq_multi(ctx, 0x17, 0x22);
444 mipi_dsi_dcs_write_seq_multi(ctx, 0x18, 0x1d);
445 mipi_dsi_dcs_write_seq_multi(ctx, 0x02, 0x77);
446 mipi_dsi_dcs_write_seq_multi(ctx, 0xe1, 0x79);
447 mipi_dsi_dcs_write_seq_multi(ctx, 0x06, 0x13);
448
449 mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0xff, 0x98, 0x06, 0x04, 0x06);
450 /* GIP 0 */
451 mipi_dsi_dcs_write_seq_multi(ctx, 0x00, 0x21);
452 mipi_dsi_dcs_write_seq_multi(ctx, 0x01, 0x0a);
453 mipi_dsi_dcs_write_seq_multi(ctx, 0x02, 0x00);
454 mipi_dsi_dcs_write_seq_multi(ctx, 0x03, 0x05);
455 mipi_dsi_dcs_write_seq_multi(ctx, 0x04, 0x01);
456 mipi_dsi_dcs_write_seq_multi(ctx, 0x05, 0x01);
457 mipi_dsi_dcs_write_seq_multi(ctx, 0x06, 0x98);
458 mipi_dsi_dcs_write_seq_multi(ctx, 0x07, 0x06);
459 mipi_dsi_dcs_write_seq_multi(ctx, 0x08, 0x01);
460 mipi_dsi_dcs_write_seq_multi(ctx, 0x09, 0x00);
461 mipi_dsi_dcs_write_seq_multi(ctx, 0x0a, 0x00);
462 mipi_dsi_dcs_write_seq_multi(ctx, 0x0b, 0x00);
463 mipi_dsi_dcs_write_seq_multi(ctx, 0x0c, 0x01);
464 mipi_dsi_dcs_write_seq_multi(ctx, 0x0d, 0x01);
465 mipi_dsi_dcs_write_seq_multi(ctx, 0x0e, 0x00);
466 mipi_dsi_dcs_write_seq_multi(ctx, 0x0f, 0x00);
467 mipi_dsi_dcs_write_seq_multi(ctx, 0x10, 0xf7);
468 mipi_dsi_dcs_write_seq_multi(ctx, 0x11, 0xf0);
469 mipi_dsi_dcs_write_seq_multi(ctx, 0x12, 0x00);
470 mipi_dsi_dcs_write_seq_multi(ctx, 0x13, 0x00);
471 mipi_dsi_dcs_write_seq_multi(ctx, 0x14, 0x00);
472 mipi_dsi_dcs_write_seq_multi(ctx, 0x15, 0xc0);
473 mipi_dsi_dcs_write_seq_multi(ctx, 0x16, 0x08);
474 mipi_dsi_dcs_write_seq_multi(ctx, 0x17, 0x00);
475 mipi_dsi_dcs_write_seq_multi(ctx, 0x18, 0x00);
476 mipi_dsi_dcs_write_seq_multi(ctx, 0x19, 0x00);
477 mipi_dsi_dcs_write_seq_multi(ctx, 0x1a, 0x00);
478 mipi_dsi_dcs_write_seq_multi(ctx, 0x1b, 0x00);
479 mipi_dsi_dcs_write_seq_multi(ctx, 0x1c, 0x00);
480 mipi_dsi_dcs_write_seq_multi(ctx, 0x1d, 0x00);
481 /* GIP 1 */
482 mipi_dsi_dcs_write_seq_multi(ctx, 0x20, 0x01);
483 mipi_dsi_dcs_write_seq_multi(ctx, 0x21, 0x23);
484 mipi_dsi_dcs_write_seq_multi(ctx, 0x22, 0x44);
485 mipi_dsi_dcs_write_seq_multi(ctx, 0x23, 0x67);
486 mipi_dsi_dcs_write_seq_multi(ctx, 0x24, 0x01);
487 mipi_dsi_dcs_write_seq_multi(ctx, 0x25, 0x23);
488 mipi_dsi_dcs_write_seq_multi(ctx, 0x26, 0x45);
489 mipi_dsi_dcs_write_seq_multi(ctx, 0x27, 0x67);
490 /* GIP 2 */
491 mipi_dsi_dcs_write_seq_multi(ctx, 0x30, 0x01);
492 mipi_dsi_dcs_write_seq_multi(ctx, 0x31, 0x22);
493 mipi_dsi_dcs_write_seq_multi(ctx, 0x32, 0x22);
494 mipi_dsi_dcs_write_seq_multi(ctx, 0x33, 0xbc);
495 mipi_dsi_dcs_write_seq_multi(ctx, 0x34, 0xad);
496 mipi_dsi_dcs_write_seq_multi(ctx, 0x35, 0xda);
497 mipi_dsi_dcs_write_seq_multi(ctx, 0x36, 0xcb);
498 mipi_dsi_dcs_write_seq_multi(ctx, 0x37, 0x22);
499 mipi_dsi_dcs_write_seq_multi(ctx, 0x38, 0x55);
500 mipi_dsi_dcs_write_seq_multi(ctx, 0x39, 0x76);
501 mipi_dsi_dcs_write_seq_multi(ctx, 0x3a, 0x67);
502 mipi_dsi_dcs_write_seq_multi(ctx, 0x3b, 0x88);
503 mipi_dsi_dcs_write_seq_multi(ctx, 0x3c, 0x22);
504 mipi_dsi_dcs_write_seq_multi(ctx, 0x3d, 0x11);
505 mipi_dsi_dcs_write_seq_multi(ctx, 0x3e, 0x00);
506 mipi_dsi_dcs_write_seq_multi(ctx, 0x3f, 0x22);
507 mipi_dsi_dcs_write_seq_multi(ctx, 0x40, 0x22);
508
509 mipi_dsi_dcs_write_seq_multi(ctx, 0x52, 0x10);
510 mipi_dsi_dcs_write_seq_multi(ctx, 0x53, 0x10);
511 mipi_dsi_dcs_write_seq_multi(ctx, 0x54, 0x13);
512
513 mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0xff, 0x98, 0x06, 0x04, 0x00);
514 };
515
516 static const struct drm_display_mode dmt028vghmcmi_1d_default_mode = {
517 .clock = 22000,
518
519 .hdisplay = 480,
520 .hsync_start = 480 + 20,
521 .hsync_end = 480 + 20 + 4,
522 .htotal = 480 + 20 + 4 + 10,
523
524 .vdisplay = 640,
525 .vsync_start = 640 + 40,
526 .vsync_end = 640 + 40 + 4,
527 .vtotal = 640 + 40 + 4 + 20,
528
529 .width_mm = 53,
530 .height_mm = 79,
531
532 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
533 .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
534 };
535
536 static const struct panel_desc dmt028vghmcmi_1d_desc = {
537 .init_sequence = dmt028vghmcmi_1d_init,
538 .display_mode = &dmt028vghmcmi_1d_default_mode,
539 .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
540 MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,
541 .format = MIPI_DSI_FMT_RGB888,
542 .lanes = 2,
543 };
544
545 static const struct of_device_id ili9806e_of_match[] = {
546 { .compatible = "densitron,dmt028vghmcmi-1d", .data = &dmt028vghmcmi_1d_desc },
547 { .compatible = "ortustech,com35h3p70ulc", .data = &com35h3p70ulc_desc },
548 { }
549 };
550 MODULE_DEVICE_TABLE(of, ili9806e_of_match);
551
552 static struct mipi_dsi_driver ili9806e_dsi_driver = {
553 .driver = {
554 .name = "ili9806e-dsi",
555 .of_match_table = ili9806e_of_match,
556 },
557 .probe = ili9806e_dsi_probe,
558 .remove = ili9806e_dsi_remove,
559 };
560 module_mipi_dsi_driver(ili9806e_dsi_driver);
561
562 MODULE_AUTHOR("Gunnar Dibbern <gunnar.dibbern@lht.dlh.de>");
563 MODULE_AUTHOR("Michael Walle <mwalle@kernel.org>");
564 MODULE_DESCRIPTION("Ilitek ILI9806E Controller Driver");
565 MODULE_LICENSE("GPL");
566