1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Xilinx gpio driver for xps/axi_gpio IP.
4 *
5 * Copyright 2008 - 2013 Xilinx, Inc.
6 */
7
8 #include <linux/bitmap.h>
9 #include <linux/bitops.h>
10 #include <linux/clk.h>
11 #include <linux/errno.h>
12 #include <linux/gpio/driver.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/irq.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/property.h>
21 #include <linux/slab.h>
22
23 /* Register Offset Definitions */
24 #define XGPIO_DATA_OFFSET (0x0) /* Data register */
25 #define XGPIO_TRI_OFFSET (0x4) /* I/O direction register */
26
27 #define XGPIO_CHANNEL0_OFFSET 0x0
28 #define XGPIO_CHANNEL1_OFFSET 0x8
29
30 #define XGPIO_GIER_OFFSET 0x11c /* Global Interrupt Enable */
31 #define XGPIO_GIER_IE BIT(31)
32 #define XGPIO_IPISR_OFFSET 0x120 /* IP Interrupt Status */
33 #define XGPIO_IPIER_OFFSET 0x128 /* IP Interrupt Enable */
34
35 /* Read/Write access to the GPIO registers */
36 #if defined(CONFIG_ARCH_ZYNQ) || defined(CONFIG_X86)
37 # define xgpio_readreg(offset) readl(offset)
38 # define xgpio_writereg(offset, val) writel(val, offset)
39 #else
40 # define xgpio_readreg(offset) __raw_readl(offset)
41 # define xgpio_writereg(offset, val) __raw_writel(val, offset)
42 #endif
43
44 /**
45 * struct xgpio_instance - Stores information about GPIO device
46 * @gc: GPIO chip
47 * @regs: register block
48 * @map: GPIO pin mapping on hardware side
49 * @state: GPIO write state shadow register
50 * @last_irq_read: GPIO read state register from last interrupt
51 * @dir: GPIO direction shadow register
52 * @gpio_lock: Lock used for synchronization
53 * @irq: IRQ used by GPIO device
54 * @enable: GPIO IRQ enable/disable bitfield
55 * @rising_edge: GPIO IRQ rising edge enable/disable bitfield
56 * @falling_edge: GPIO IRQ falling edge enable/disable bitfield
57 * @clk: clock resource for this driver
58 */
59 struct xgpio_instance {
60 struct gpio_chip gc;
61 void __iomem *regs;
62 DECLARE_BITMAP(map, 64);
63 DECLARE_BITMAP(state, 64);
64 DECLARE_BITMAP(last_irq_read, 64);
65 DECLARE_BITMAP(dir, 64);
66 raw_spinlock_t gpio_lock; /* For serializing operations */
67 int irq;
68 DECLARE_BITMAP(enable, 64);
69 DECLARE_BITMAP(rising_edge, 64);
70 DECLARE_BITMAP(falling_edge, 64);
71 struct clk *clk;
72 };
73
xgpio_regoffset(struct xgpio_instance * chip,int ch)74 static inline int xgpio_regoffset(struct xgpio_instance *chip, int ch)
75 {
76 switch (ch) {
77 case 0:
78 return XGPIO_CHANNEL0_OFFSET;
79 case 1:
80 return XGPIO_CHANNEL1_OFFSET;
81 default:
82 return -EINVAL;
83 }
84 }
85
xgpio_read_ch(struct xgpio_instance * chip,int reg,int bit,unsigned long * a)86 static void xgpio_read_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a)
87 {
88 void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32);
89 unsigned long value = xgpio_readreg(addr);
90
91 bitmap_write(a, value, round_down(bit, 32), 32);
92 }
93
xgpio_write_ch(struct xgpio_instance * chip,int reg,int bit,unsigned long * a)94 static void xgpio_write_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a)
95 {
96 void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32);
97 unsigned long value = bitmap_read(a, round_down(bit, 32), 32);
98
99 xgpio_writereg(addr, value);
100 }
101
xgpio_read_ch_all(struct xgpio_instance * chip,int reg,unsigned long * a)102 static void xgpio_read_ch_all(struct xgpio_instance *chip, int reg, unsigned long *a)
103 {
104 unsigned long lastbit = find_nth_bit(chip->map, 64, chip->gc.ngpio - 1);
105 int bit;
106
107 for (bit = 0; bit <= lastbit ; bit += 32)
108 xgpio_read_ch(chip, reg, bit, a);
109 }
110
xgpio_write_ch_all(struct xgpio_instance * chip,int reg,unsigned long * a)111 static void xgpio_write_ch_all(struct xgpio_instance *chip, int reg, unsigned long *a)
112 {
113 unsigned long lastbit = find_nth_bit(chip->map, 64, chip->gc.ngpio - 1);
114 int bit;
115
116 for (bit = 0; bit <= lastbit ; bit += 32)
117 xgpio_write_ch(chip, reg, bit, a);
118 }
119
120 /**
121 * xgpio_get - Read the specified signal of the GPIO device.
122 * @gc: Pointer to gpio_chip device structure.
123 * @gpio: GPIO signal number.
124 *
125 * This function reads the specified signal of the GPIO device.
126 *
127 * Return:
128 * 0 if direction of GPIO signals is set as input otherwise it
129 * returns negative error value.
130 */
xgpio_get(struct gpio_chip * gc,unsigned int gpio)131 static int xgpio_get(struct gpio_chip *gc, unsigned int gpio)
132 {
133 struct xgpio_instance *chip = gpiochip_get_data(gc);
134 unsigned long bit = find_nth_bit(chip->map, 64, gpio);
135 DECLARE_BITMAP(state, 64);
136
137 xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, state);
138
139 return test_bit(bit, state);
140 }
141
142 /**
143 * xgpio_set - Write the specified signal of the GPIO device.
144 * @gc: Pointer to gpio_chip device structure.
145 * @gpio: GPIO signal number.
146 * @val: Value to be written to specified signal.
147 *
148 * This function writes the specified value in to the specified signal of the
149 * GPIO device.
150 */
xgpio_set(struct gpio_chip * gc,unsigned int gpio,int val)151 static int xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
152 {
153 unsigned long flags;
154 struct xgpio_instance *chip = gpiochip_get_data(gc);
155 unsigned long bit = find_nth_bit(chip->map, 64, gpio);
156
157 raw_spin_lock_irqsave(&chip->gpio_lock, flags);
158
159 /* Write to GPIO signal and set its direction to output */
160 __assign_bit(bit, chip->state, val);
161
162 xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, chip->state);
163
164 raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
165
166 return 0;
167 }
168
169 /**
170 * xgpio_set_multiple - Write the specified signals of the GPIO device.
171 * @gc: Pointer to gpio_chip device structure.
172 * @mask: Mask of the GPIOS to modify.
173 * @bits: Value to be wrote on each GPIO
174 *
175 * This function writes the specified values into the specified signals of the
176 * GPIO devices.
177 */
xgpio_set_multiple(struct gpio_chip * gc,unsigned long * mask,unsigned long * bits)178 static int xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
179 unsigned long *bits)
180 {
181 DECLARE_BITMAP(hw_mask, 64);
182 DECLARE_BITMAP(hw_bits, 64);
183 DECLARE_BITMAP(state, 64);
184 unsigned long flags;
185 struct xgpio_instance *chip = gpiochip_get_data(gc);
186
187 bitmap_scatter(hw_mask, mask, chip->map, 64);
188 bitmap_scatter(hw_bits, bits, chip->map, 64);
189
190 raw_spin_lock_irqsave(&chip->gpio_lock, flags);
191
192 bitmap_replace(state, chip->state, hw_bits, hw_mask, 64);
193
194 xgpio_write_ch_all(chip, XGPIO_DATA_OFFSET, state);
195
196 bitmap_copy(chip->state, state, 64);
197
198 raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
199
200 return 0;
201 }
202
203 /**
204 * xgpio_dir_in - Set the direction of the specified GPIO signal as input.
205 * @gc: Pointer to gpio_chip device structure.
206 * @gpio: GPIO signal number.
207 *
208 * Return:
209 * 0 - if direction of GPIO signals is set as input
210 * otherwise it returns negative error value.
211 */
xgpio_dir_in(struct gpio_chip * gc,unsigned int gpio)212 static int xgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
213 {
214 unsigned long flags;
215 struct xgpio_instance *chip = gpiochip_get_data(gc);
216 unsigned long bit = find_nth_bit(chip->map, 64, gpio);
217
218 raw_spin_lock_irqsave(&chip->gpio_lock, flags);
219
220 /* Set the GPIO bit in shadow register and set direction as input */
221 __set_bit(bit, chip->dir);
222 xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, chip->dir);
223
224 raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
225
226 return 0;
227 }
228
229 /**
230 * xgpio_dir_out - Set the direction of the specified GPIO signal as output.
231 * @gc: Pointer to gpio_chip device structure.
232 * @gpio: GPIO signal number.
233 * @val: Value to be written to specified signal.
234 *
235 * This function sets the direction of specified GPIO signal as output.
236 *
237 * Return:
238 * If all GPIO signals of GPIO chip is configured as input then it returns
239 * error otherwise it returns 0.
240 */
xgpio_dir_out(struct gpio_chip * gc,unsigned int gpio,int val)241 static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
242 {
243 unsigned long flags;
244 struct xgpio_instance *chip = gpiochip_get_data(gc);
245 unsigned long bit = find_nth_bit(chip->map, 64, gpio);
246
247 raw_spin_lock_irqsave(&chip->gpio_lock, flags);
248
249 /* Write state of GPIO signal */
250 __assign_bit(bit, chip->state, val);
251 xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, chip->state);
252
253 /* Clear the GPIO bit in shadow register and set direction as output */
254 __clear_bit(bit, chip->dir);
255 xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, chip->dir);
256
257 raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
258
259 return 0;
260 }
261
262 /**
263 * xgpio_save_regs - Set initial values of GPIO pins
264 * @chip: Pointer to GPIO instance
265 */
xgpio_save_regs(struct xgpio_instance * chip)266 static void xgpio_save_regs(struct xgpio_instance *chip)
267 {
268 xgpio_write_ch_all(chip, XGPIO_DATA_OFFSET, chip->state);
269 xgpio_write_ch_all(chip, XGPIO_TRI_OFFSET, chip->dir);
270 }
271
xgpio_request(struct gpio_chip * chip,unsigned int offset)272 static int xgpio_request(struct gpio_chip *chip, unsigned int offset)
273 {
274 int ret;
275
276 ret = pm_runtime_get_sync(chip->parent);
277 /*
278 * If the device is already active pm_runtime_get() will return 1 on
279 * success, but gpio_request still needs to return 0.
280 */
281 return ret < 0 ? ret : 0;
282 }
283
xgpio_free(struct gpio_chip * chip,unsigned int offset)284 static void xgpio_free(struct gpio_chip *chip, unsigned int offset)
285 {
286 pm_runtime_put(chip->parent);
287 }
288
xgpio_suspend(struct device * dev)289 static int __maybe_unused xgpio_suspend(struct device *dev)
290 {
291 struct xgpio_instance *gpio = dev_get_drvdata(dev);
292 struct irq_data *data = irq_get_irq_data(gpio->irq);
293
294 if (!data) {
295 dev_dbg(dev, "IRQ not connected\n");
296 return pm_runtime_force_suspend(dev);
297 }
298
299 if (!irqd_is_wakeup_set(data))
300 return pm_runtime_force_suspend(dev);
301
302 return 0;
303 }
304
305 /**
306 * xgpio_remove - Remove method for the GPIO device.
307 * @pdev: pointer to the platform device
308 *
309 * This function remove gpiochips and frees all the allocated resources.
310 *
311 * Return: 0 always
312 */
xgpio_remove(struct platform_device * pdev)313 static void xgpio_remove(struct platform_device *pdev)
314 {
315 pm_runtime_get_sync(&pdev->dev);
316 pm_runtime_put_noidle(&pdev->dev);
317 pm_runtime_disable(&pdev->dev);
318 }
319
320 /**
321 * xgpio_irq_ack - Acknowledge a child GPIO interrupt.
322 * @irq_data: per IRQ and chip data passed down to chip functions
323 * This currently does nothing, but irq_ack is unconditionally called by
324 * handle_edge_irq and therefore must be defined.
325 */
xgpio_irq_ack(struct irq_data * irq_data)326 static void xgpio_irq_ack(struct irq_data *irq_data)
327 {
328 }
329
xgpio_resume(struct device * dev)330 static int __maybe_unused xgpio_resume(struct device *dev)
331 {
332 struct xgpio_instance *gpio = dev_get_drvdata(dev);
333 struct irq_data *data = irq_get_irq_data(gpio->irq);
334
335 if (!data) {
336 dev_dbg(dev, "IRQ not connected\n");
337 return pm_runtime_force_resume(dev);
338 }
339
340 if (!irqd_is_wakeup_set(data))
341 return pm_runtime_force_resume(dev);
342
343 return 0;
344 }
345
xgpio_runtime_suspend(struct device * dev)346 static int __maybe_unused xgpio_runtime_suspend(struct device *dev)
347 {
348 struct xgpio_instance *gpio = dev_get_drvdata(dev);
349
350 clk_disable(gpio->clk);
351
352 return 0;
353 }
354
xgpio_runtime_resume(struct device * dev)355 static int __maybe_unused xgpio_runtime_resume(struct device *dev)
356 {
357 struct xgpio_instance *gpio = dev_get_drvdata(dev);
358
359 return clk_enable(gpio->clk);
360 }
361
362 static const struct dev_pm_ops xgpio_dev_pm_ops = {
363 SET_SYSTEM_SLEEP_PM_OPS(xgpio_suspend, xgpio_resume)
364 SET_RUNTIME_PM_OPS(xgpio_runtime_suspend,
365 xgpio_runtime_resume, NULL)
366 };
367
368 /**
369 * xgpio_irq_mask - Write the specified signal of the GPIO device.
370 * @irq_data: per IRQ and chip data passed down to chip functions
371 */
xgpio_irq_mask(struct irq_data * irq_data)372 static void xgpio_irq_mask(struct irq_data *irq_data)
373 {
374 unsigned long flags;
375 struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data);
376 int irq_offset = irqd_to_hwirq(irq_data);
377 unsigned long bit = find_nth_bit(chip->map, 64, irq_offset), enable;
378 u32 mask = BIT(bit / 32), temp;
379
380 raw_spin_lock_irqsave(&chip->gpio_lock, flags);
381
382 __clear_bit(bit, chip->enable);
383
384 enable = bitmap_read(chip->enable, round_down(bit, 32), 32);
385 if (enable == 0) {
386 /* Disable per channel interrupt */
387 temp = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET);
388 temp &= ~mask;
389 xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, temp);
390 }
391 raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
392
393 gpiochip_disable_irq(&chip->gc, irq_offset);
394 }
395
396 /**
397 * xgpio_irq_unmask - Write the specified signal of the GPIO device.
398 * @irq_data: per IRQ and chip data passed down to chip functions
399 */
xgpio_irq_unmask(struct irq_data * irq_data)400 static void xgpio_irq_unmask(struct irq_data *irq_data)
401 {
402 unsigned long flags;
403 struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data);
404 int irq_offset = irqd_to_hwirq(irq_data);
405 unsigned long bit = find_nth_bit(chip->map, 64, irq_offset), enable;
406 u32 mask = BIT(bit / 32), val;
407
408 gpiochip_enable_irq(&chip->gc, irq_offset);
409
410 raw_spin_lock_irqsave(&chip->gpio_lock, flags);
411
412 enable = bitmap_read(chip->enable, round_down(bit, 32), 32);
413 if (enable == 0) {
414 /* Clear any existing per-channel interrupts */
415 val = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET);
416 val &= mask;
417 xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, val);
418
419 /* Update GPIO IRQ read data before enabling interrupt*/
420 xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, chip->last_irq_read);
421
422 /* Enable per channel interrupt */
423 val = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET);
424 val |= mask;
425 xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, val);
426 }
427
428 __set_bit(bit, chip->enable);
429
430 raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
431 }
432
433 /**
434 * xgpio_set_irq_type - Write the specified signal of the GPIO device.
435 * @irq_data: Per IRQ and chip data passed down to chip functions
436 * @type: Interrupt type that is to be set for the gpio pin
437 *
438 * Return:
439 * 0 if interrupt type is supported otherwise -EINVAL
440 */
xgpio_set_irq_type(struct irq_data * irq_data,unsigned int type)441 static int xgpio_set_irq_type(struct irq_data *irq_data, unsigned int type)
442 {
443 struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data);
444 int irq_offset = irqd_to_hwirq(irq_data);
445 unsigned long bit = find_nth_bit(chip->map, 64, irq_offset);
446
447 /*
448 * The Xilinx GPIO hardware provides a single interrupt status
449 * indication for any state change in a given GPIO channel (bank).
450 * Therefore, only rising edge or falling edge triggers are
451 * supported.
452 */
453 switch (type & IRQ_TYPE_SENSE_MASK) {
454 case IRQ_TYPE_EDGE_BOTH:
455 __set_bit(bit, chip->rising_edge);
456 __set_bit(bit, chip->falling_edge);
457 break;
458 case IRQ_TYPE_EDGE_RISING:
459 __set_bit(bit, chip->rising_edge);
460 __clear_bit(bit, chip->falling_edge);
461 break;
462 case IRQ_TYPE_EDGE_FALLING:
463 __clear_bit(bit, chip->rising_edge);
464 __set_bit(bit, chip->falling_edge);
465 break;
466 default:
467 return -EINVAL;
468 }
469
470 irq_set_handler_locked(irq_data, handle_edge_irq);
471 return 0;
472 }
473
474 /**
475 * xgpio_irqhandler - Gpio interrupt service routine
476 * @desc: Pointer to interrupt description
477 */
xgpio_irqhandler(struct irq_desc * desc)478 static void xgpio_irqhandler(struct irq_desc *desc)
479 {
480 struct xgpio_instance *chip = irq_desc_get_handler_data(desc);
481 struct gpio_chip *gc = &chip->gc;
482 struct irq_chip *irqchip = irq_desc_get_chip(desc);
483 DECLARE_BITMAP(rising, 64);
484 DECLARE_BITMAP(falling, 64);
485 DECLARE_BITMAP(hw, 64);
486 DECLARE_BITMAP(sw, 64);
487 int irq_offset;
488 u32 status;
489
490 status = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET);
491 xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, status);
492
493 chained_irq_enter(irqchip, desc);
494
495 raw_spin_lock(&chip->gpio_lock);
496
497 xgpio_read_ch_all(chip, XGPIO_DATA_OFFSET, hw);
498
499 bitmap_complement(rising, chip->last_irq_read, 64);
500 bitmap_and(rising, rising, hw, 64);
501 bitmap_and(rising, rising, chip->enable, 64);
502 bitmap_and(rising, rising, chip->rising_edge, 64);
503
504 bitmap_complement(falling, hw, 64);
505 bitmap_and(falling, falling, chip->last_irq_read, 64);
506 bitmap_and(falling, falling, chip->enable, 64);
507 bitmap_and(falling, falling, chip->falling_edge, 64);
508
509 bitmap_copy(chip->last_irq_read, hw, 64);
510 bitmap_or(hw, rising, falling, 64);
511
512 raw_spin_unlock(&chip->gpio_lock);
513
514 dev_dbg(gc->parent, "IRQ rising %*pb falling %*pb\n", 64, rising, 64, falling);
515
516 bitmap_gather(sw, hw, chip->map, 64);
517 for_each_set_bit(irq_offset, sw, 64)
518 generic_handle_domain_irq(gc->irq.domain, irq_offset);
519
520 chained_irq_exit(irqchip, desc);
521 }
522
523 static const struct irq_chip xgpio_irq_chip = {
524 .name = "gpio-xilinx",
525 .irq_ack = xgpio_irq_ack,
526 .irq_mask = xgpio_irq_mask,
527 .irq_unmask = xgpio_irq_unmask,
528 .irq_set_type = xgpio_set_irq_type,
529 .flags = IRQCHIP_IMMUTABLE,
530 GPIOCHIP_IRQ_RESOURCE_HELPERS,
531 };
532
533 /**
534 * xgpio_probe - Probe method for the GPIO device.
535 * @pdev: pointer to the platform device
536 *
537 * Return:
538 * It returns 0, if the driver is bound to the GPIO device, or
539 * a negative value if there is an error.
540 */
xgpio_probe(struct platform_device * pdev)541 static int xgpio_probe(struct platform_device *pdev)
542 {
543 struct device *dev = &pdev->dev;
544 struct xgpio_instance *chip;
545 int status = 0;
546 u32 is_dual = 0;
547 u32 width[2];
548 u32 state[2];
549 u32 dir[2];
550 struct gpio_irq_chip *girq;
551 u32 temp;
552
553 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
554 if (!chip)
555 return -ENOMEM;
556
557 platform_set_drvdata(pdev, chip);
558
559 /* First, check if the device is dual-channel */
560 device_property_read_u32(dev, "xlnx,is-dual", &is_dual);
561
562 /* Setup defaults */
563 memset32(width, 0, ARRAY_SIZE(width));
564 memset32(state, 0, ARRAY_SIZE(state));
565 memset32(dir, 0xFFFFFFFF, ARRAY_SIZE(dir));
566
567 /* Update GPIO state shadow register with default value */
568 device_property_read_u32(dev, "xlnx,dout-default", &state[0]);
569 device_property_read_u32(dev, "xlnx,dout-default-2", &state[1]);
570
571 bitmap_from_arr32(chip->state, state, 64);
572
573 /* Update GPIO direction shadow register with default value */
574 device_property_read_u32(dev, "xlnx,tri-default", &dir[0]);
575 device_property_read_u32(dev, "xlnx,tri-default-2", &dir[1]);
576
577 bitmap_from_arr32(chip->dir, dir, 64);
578
579 /*
580 * Check device node and parent device node for device width
581 * and assume default width of 32
582 */
583 if (device_property_read_u32(dev, "xlnx,gpio-width", &width[0]))
584 width[0] = 32;
585
586 if (width[0] > 32)
587 return -EINVAL;
588
589 if (is_dual && device_property_read_u32(dev, "xlnx,gpio2-width", &width[1]))
590 width[1] = 32;
591
592 if (width[1] > 32)
593 return -EINVAL;
594
595 /* Setup hardware pin mapping */
596 bitmap_set(chip->map, 0, width[0]);
597 bitmap_set(chip->map, 32, width[1]);
598
599 raw_spin_lock_init(&chip->gpio_lock);
600
601 chip->gc.base = -1;
602 chip->gc.ngpio = bitmap_weight(chip->map, 64);
603 chip->gc.parent = dev;
604 chip->gc.direction_input = xgpio_dir_in;
605 chip->gc.direction_output = xgpio_dir_out;
606 chip->gc.get = xgpio_get;
607 chip->gc.set = xgpio_set;
608 chip->gc.request = xgpio_request;
609 chip->gc.free = xgpio_free;
610 chip->gc.set_multiple = xgpio_set_multiple;
611
612 chip->gc.label = dev_name(dev);
613
614 chip->regs = devm_platform_ioremap_resource(pdev, 0);
615 if (IS_ERR(chip->regs)) {
616 dev_err(dev, "failed to ioremap memory resource\n");
617 return PTR_ERR(chip->regs);
618 }
619
620 chip->clk = devm_clk_get_optional_enabled(dev, NULL);
621 if (IS_ERR(chip->clk))
622 return dev_err_probe(dev, PTR_ERR(chip->clk), "input clock not found.\n");
623
624 pm_runtime_get_noresume(dev);
625 pm_runtime_set_active(dev);
626 pm_runtime_enable(dev);
627
628 xgpio_save_regs(chip);
629
630 chip->irq = platform_get_irq_optional(pdev, 0);
631 if (chip->irq <= 0)
632 goto skip_irq;
633
634 /* Disable per-channel interrupts */
635 xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, 0);
636 /* Clear any existing per-channel interrupts */
637 temp = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET);
638 xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, temp);
639 /* Enable global interrupts */
640 xgpio_writereg(chip->regs + XGPIO_GIER_OFFSET, XGPIO_GIER_IE);
641
642 girq = &chip->gc.irq;
643 gpio_irq_chip_set_chip(girq, &xgpio_irq_chip);
644 girq->parent_handler = xgpio_irqhandler;
645 girq->num_parents = 1;
646 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
647 GFP_KERNEL);
648 if (!girq->parents) {
649 status = -ENOMEM;
650 goto err_pm_put;
651 }
652 girq->parents[0] = chip->irq;
653 girq->default_type = IRQ_TYPE_NONE;
654 girq->handler = handle_bad_irq;
655
656 skip_irq:
657 status = devm_gpiochip_add_data(dev, &chip->gc, chip);
658 if (status) {
659 dev_err(dev, "failed to add GPIO chip\n");
660 goto err_pm_put;
661 }
662
663 pm_runtime_put(dev);
664 return 0;
665
666 err_pm_put:
667 pm_runtime_disable(dev);
668 pm_runtime_put_noidle(dev);
669 return status;
670 }
671
672 static const struct of_device_id xgpio_of_match[] = {
673 { .compatible = "xlnx,xps-gpio-1.00.a", },
674 { /* end of list */ },
675 };
676
677 MODULE_DEVICE_TABLE(of, xgpio_of_match);
678
679 static struct platform_driver xgpio_plat_driver = {
680 .probe = xgpio_probe,
681 .remove = xgpio_remove,
682 .driver = {
683 .name = "gpio-xilinx",
684 .of_match_table = xgpio_of_match,
685 .pm = &xgpio_dev_pm_ops,
686 },
687 };
688
xgpio_init(void)689 static int __init xgpio_init(void)
690 {
691 return platform_driver_register(&xgpio_plat_driver);
692 }
693
694 subsys_initcall(xgpio_init);
695
xgpio_exit(void)696 static void __exit xgpio_exit(void)
697 {
698 platform_driver_unregister(&xgpio_plat_driver);
699 }
700 module_exit(xgpio_exit);
701
702 MODULE_AUTHOR("Xilinx, Inc.");
703 MODULE_DESCRIPTION("Xilinx GPIO driver");
704 MODULE_LICENSE("GPL");
705