1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * RDA Micro GPIO driver
4 *
5 * Copyright (C) 2012 RDA Micro Inc.
6 * Copyright (C) 2019 Manivannan Sadhasivam
7 */
8
9 #include <linux/bitops.h>
10 #include <linux/gpio/driver.h>
11 #include <linux/gpio/generic.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/spinlock.h>
16
17 #define RDA_GPIO_OEN_VAL 0x00
18 #define RDA_GPIO_OEN_SET_OUT 0x04
19 #define RDA_GPIO_OEN_SET_IN 0x08
20 #define RDA_GPIO_VAL 0x0c
21 #define RDA_GPIO_SET 0x10
22 #define RDA_GPIO_CLR 0x14
23 #define RDA_GPIO_INT_CTRL_SET 0x18
24 #define RDA_GPIO_INT_CTRL_CLR 0x1c
25 #define RDA_GPIO_INT_CLR 0x20
26 #define RDA_GPIO_INT_STATUS 0x24
27
28 #define RDA_GPIO_IRQ_RISE_SHIFT 0
29 #define RDA_GPIO_IRQ_FALL_SHIFT 8
30 #define RDA_GPIO_DEBOUCE_SHIFT 16
31 #define RDA_GPIO_LEVEL_SHIFT 24
32
33 #define RDA_GPIO_IRQ_MASK 0xff
34
35 /* Each bank consists of 32 GPIOs */
36 #define RDA_GPIO_BANK_NR 32
37
38 struct rda_gpio {
39 struct gpio_generic_chip chip;
40 void __iomem *base;
41 spinlock_t lock;
42 int irq;
43 };
44
rda_gpio_update(struct gpio_chip * chip,unsigned int offset,u16 reg,int val)45 static inline void rda_gpio_update(struct gpio_chip *chip, unsigned int offset,
46 u16 reg, int val)
47 {
48 struct rda_gpio *rda_gpio = gpiochip_get_data(chip);
49 void __iomem *base = rda_gpio->base;
50 unsigned long flags;
51 u32 tmp;
52
53 spin_lock_irqsave(&rda_gpio->lock, flags);
54 tmp = readl_relaxed(base + reg);
55
56 if (val)
57 tmp |= BIT(offset);
58 else
59 tmp &= ~BIT(offset);
60
61 writel_relaxed(tmp, base + reg);
62 spin_unlock_irqrestore(&rda_gpio->lock, flags);
63 }
64
rda_gpio_irq_mask(struct irq_data * data)65 static void rda_gpio_irq_mask(struct irq_data *data)
66 {
67 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
68 struct rda_gpio *rda_gpio = gpiochip_get_data(chip);
69 void __iomem *base = rda_gpio->base;
70 u32 offset = irqd_to_hwirq(data);
71 u32 value;
72
73 value = BIT(offset) << RDA_GPIO_IRQ_RISE_SHIFT;
74 value |= BIT(offset) << RDA_GPIO_IRQ_FALL_SHIFT;
75
76 writel_relaxed(value, base + RDA_GPIO_INT_CTRL_CLR);
77 gpiochip_disable_irq(chip, offset);
78 }
79
rda_gpio_irq_ack(struct irq_data * data)80 static void rda_gpio_irq_ack(struct irq_data *data)
81 {
82 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
83 u32 offset = irqd_to_hwirq(data);
84
85 rda_gpio_update(chip, offset, RDA_GPIO_INT_CLR, 1);
86 }
87
rda_gpio_set_irq(struct gpio_chip * chip,u32 offset,unsigned int flow_type)88 static int rda_gpio_set_irq(struct gpio_chip *chip, u32 offset,
89 unsigned int flow_type)
90 {
91 struct rda_gpio *rda_gpio = gpiochip_get_data(chip);
92 void __iomem *base = rda_gpio->base;
93 u32 value;
94
95 switch (flow_type) {
96 case IRQ_TYPE_EDGE_RISING:
97 /* Set rising edge trigger */
98 value = BIT(offset) << RDA_GPIO_IRQ_RISE_SHIFT;
99 writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET);
100
101 /* Switch to edge trigger interrupt */
102 value = BIT(offset) << RDA_GPIO_LEVEL_SHIFT;
103 writel_relaxed(value, base + RDA_GPIO_INT_CTRL_CLR);
104 break;
105
106 case IRQ_TYPE_EDGE_FALLING:
107 /* Set falling edge trigger */
108 value = BIT(offset) << RDA_GPIO_IRQ_FALL_SHIFT;
109 writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET);
110
111 /* Switch to edge trigger interrupt */
112 value = BIT(offset) << RDA_GPIO_LEVEL_SHIFT;
113 writel_relaxed(value, base + RDA_GPIO_INT_CTRL_CLR);
114 break;
115
116 case IRQ_TYPE_EDGE_BOTH:
117 /* Set both edge trigger */
118 value = BIT(offset) << RDA_GPIO_IRQ_RISE_SHIFT;
119 value |= BIT(offset) << RDA_GPIO_IRQ_FALL_SHIFT;
120 writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET);
121
122 /* Switch to edge trigger interrupt */
123 value = BIT(offset) << RDA_GPIO_LEVEL_SHIFT;
124 writel_relaxed(value, base + RDA_GPIO_INT_CTRL_CLR);
125 break;
126
127 case IRQ_TYPE_LEVEL_HIGH:
128 /* Set high level trigger */
129 value = BIT(offset) << RDA_GPIO_IRQ_RISE_SHIFT;
130
131 /* Switch to level trigger interrupt */
132 value |= BIT(offset) << RDA_GPIO_LEVEL_SHIFT;
133 writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET);
134 break;
135
136 case IRQ_TYPE_LEVEL_LOW:
137 /* Set low level trigger */
138 value = BIT(offset) << RDA_GPIO_IRQ_FALL_SHIFT;
139
140 /* Switch to level trigger interrupt */
141 value |= BIT(offset) << RDA_GPIO_LEVEL_SHIFT;
142 writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET);
143 break;
144
145 default:
146 return -EINVAL;
147 }
148
149 return 0;
150 }
151
rda_gpio_irq_unmask(struct irq_data * data)152 static void rda_gpio_irq_unmask(struct irq_data *data)
153 {
154 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
155 u32 offset = irqd_to_hwirq(data);
156 u32 trigger = irqd_get_trigger_type(data);
157
158 gpiochip_enable_irq(chip, offset);
159 rda_gpio_set_irq(chip, offset, trigger);
160 }
161
rda_gpio_irq_set_type(struct irq_data * data,unsigned int flow_type)162 static int rda_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
163 {
164 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
165 u32 offset = irqd_to_hwirq(data);
166 int ret;
167
168 ret = rda_gpio_set_irq(chip, offset, flow_type);
169 if (ret)
170 return ret;
171
172 if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
173 irq_set_handler_locked(data, handle_level_irq);
174 else if (flow_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
175 irq_set_handler_locked(data, handle_edge_irq);
176
177 return 0;
178 }
179
rda_gpio_irq_handler(struct irq_desc * desc)180 static void rda_gpio_irq_handler(struct irq_desc *desc)
181 {
182 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
183 struct irq_chip *ic = irq_desc_get_chip(desc);
184 struct rda_gpio *rda_gpio = gpiochip_get_data(chip);
185 unsigned long status;
186 u32 n;
187
188 chained_irq_enter(ic, desc);
189
190 status = readl_relaxed(rda_gpio->base + RDA_GPIO_INT_STATUS);
191 /* Only lower 8 bits are capable of generating interrupts */
192 status &= RDA_GPIO_IRQ_MASK;
193
194 for_each_set_bit(n, &status, RDA_GPIO_BANK_NR)
195 generic_handle_domain_irq(chip->irq.domain, n);
196
197 chained_irq_exit(ic, desc);
198 }
199
200 static const struct irq_chip rda_gpio_irq_chip = {
201 .name = "rda-gpio",
202 .irq_ack = rda_gpio_irq_ack,
203 .irq_mask = rda_gpio_irq_mask,
204 .irq_unmask = rda_gpio_irq_unmask,
205 .irq_set_type = rda_gpio_irq_set_type,
206 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE,
207 GPIOCHIP_IRQ_RESOURCE_HELPERS,
208 };
209
rda_gpio_probe(struct platform_device * pdev)210 static int rda_gpio_probe(struct platform_device *pdev)
211 {
212 struct gpio_generic_chip_config config;
213 struct device *dev = &pdev->dev;
214 struct gpio_irq_chip *girq;
215 struct rda_gpio *rda_gpio;
216 u32 ngpios;
217 int ret;
218
219 rda_gpio = devm_kzalloc(dev, sizeof(*rda_gpio), GFP_KERNEL);
220 if (!rda_gpio)
221 return -ENOMEM;
222
223 ret = device_property_read_u32(dev, "ngpios", &ngpios);
224 if (ret < 0)
225 return ret;
226
227 /*
228 * Not all ports have interrupt capability. For instance, on
229 * RDA8810PL, GPIOC doesn't support interrupt. So we must handle
230 * those also.
231 */
232 rda_gpio->irq = platform_get_irq(pdev, 0);
233
234 rda_gpio->base = devm_platform_ioremap_resource(pdev, 0);
235 if (IS_ERR(rda_gpio->base))
236 return PTR_ERR(rda_gpio->base);
237
238 spin_lock_init(&rda_gpio->lock);
239
240 config = (struct gpio_generic_chip_config) {
241 .dev = dev,
242 .sz = 4,
243 .dat = rda_gpio->base + RDA_GPIO_VAL,
244 .set = rda_gpio->base + RDA_GPIO_SET,
245 .clr = rda_gpio->base + RDA_GPIO_CLR,
246 .dirout = rda_gpio->base + RDA_GPIO_OEN_SET_OUT,
247 .dirin = rda_gpio->base + RDA_GPIO_OEN_SET_IN,
248 .flags = GPIO_GENERIC_READ_OUTPUT_REG_SET,
249 };
250
251 ret = gpio_generic_chip_init(&rda_gpio->chip, &config);
252 if (ret) {
253 dev_err(dev, "failed to initialize the generic GPIO chip\n");
254 return ret;
255 }
256
257 rda_gpio->chip.gc.label = dev_name(dev);
258 rda_gpio->chip.gc.ngpio = ngpios;
259 rda_gpio->chip.gc.base = -1;
260
261 if (rda_gpio->irq >= 0) {
262 girq = &rda_gpio->chip.gc.irq;
263 gpio_irq_chip_set_chip(girq, &rda_gpio_irq_chip);
264 girq->handler = handle_bad_irq;
265 girq->default_type = IRQ_TYPE_NONE;
266 girq->parent_handler = rda_gpio_irq_handler;
267 girq->parent_handler_data = rda_gpio;
268 girq->num_parents = 1;
269 girq->parents = devm_kcalloc(dev, 1,
270 sizeof(*girq->parents),
271 GFP_KERNEL);
272 if (!girq->parents)
273 return -ENOMEM;
274 girq->parents[0] = rda_gpio->irq;
275 }
276
277 platform_set_drvdata(pdev, rda_gpio);
278
279 return devm_gpiochip_add_data(dev, &rda_gpio->chip.gc, rda_gpio);
280 }
281
282 static const struct of_device_id rda_gpio_of_match[] = {
283 { .compatible = "rda,8810pl-gpio", },
284 { /* sentinel */ }
285 };
286 MODULE_DEVICE_TABLE(of, rda_gpio_of_match);
287
288 static struct platform_driver rda_gpio_driver = {
289 .probe = rda_gpio_probe,
290 .driver = {
291 .name = "rda-gpio",
292 .of_match_table = rda_gpio_of_match,
293 },
294 };
295
296 module_platform_driver_probe(rda_gpio_driver, rda_gpio_probe);
297
298 MODULE_DESCRIPTION("RDA Micro GPIO driver");
299 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
300