1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * GPIO driver for Marvell SoCs
4 *
5 * Copyright (C) 2012 Marvell
6 *
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 * Andrew Lunn <andrew@lunn.ch>
9 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
10 *
11 * This driver is a fairly straightforward GPIO driver for the
12 * complete family of Marvell EBU SoC platforms (Orion, Dove,
13 * Kirkwood, Discovery, Armada 370/XP). The only complexity of this
14 * driver is the different register layout that exists between the
15 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
16 * platforms (MV78200 from the Discovery family and the Armada
17 * XP). Therefore, this driver handles three variants of the GPIO
18 * block:
19 * - the basic variant, called "orion-gpio", with the simplest
20 * register set. Used on Orion, Dove, Kirkwoord, Armada 370 and
21 * non-SMP Discovery systems
22 * - the mv78200 variant for MV78200 Discovery systems. This variant
23 * turns the edge mask and level mask registers into CPU0 edge
24 * mask/level mask registers, and adds CPU1 edge mask/level mask
25 * registers.
26 * - the armadaxp variant for Armada XP systems. This variant keeps
27 * the normal cause/edge mask/level mask registers when the global
28 * interrupts are used, but adds per-CPU cause/edge mask/level mask
29 * registers n a separate memory area for the per-CPU GPIO
30 * interrupts.
31 */
32
33 #include <linux/bitops.h>
34 #include <linux/clk.h>
35 #include <linux/err.h>
36 #include <linux/gpio/driver.h>
37 #include <linux/gpio/consumer.h>
38 #include <linux/gpio/machine.h>
39 #include <linux/init.h>
40 #include <linux/io.h>
41 #include <linux/irq.h>
42 #include <linux/irqchip/chained_irq.h>
43 #include <linux/irqdomain.h>
44 #include <linux/mfd/syscon.h>
45 #include <linux/of.h>
46 #include <linux/pinctrl/consumer.h>
47 #include <linux/platform_device.h>
48 #include <linux/property.h>
49 #include <linux/pwm.h>
50 #include <linux/regmap.h>
51 #include <linux/slab.h>
52 #include <linux/string_choices.h>
53
54 /*
55 * GPIO unit register offsets.
56 */
57 #define GPIO_OUT_OFF 0x0000
58 #define GPIO_IO_CONF_OFF 0x0004
59 #define GPIO_BLINK_EN_OFF 0x0008
60 #define GPIO_IN_POL_OFF 0x000c
61 #define GPIO_DATA_IN_OFF 0x0010
62 #define GPIO_EDGE_CAUSE_OFF 0x0014
63 #define GPIO_EDGE_MASK_OFF 0x0018
64 #define GPIO_LEVEL_MASK_OFF 0x001c
65 #define GPIO_BLINK_CNT_SELECT_OFF 0x0020
66
67 /*
68 * PWM register offsets.
69 */
70 #define PWM_BLINK_ON_DURATION_OFF 0x0
71 #define PWM_BLINK_OFF_DURATION_OFF 0x4
72 #define PWM_BLINK_COUNTER_B_OFF 0x8
73
74 /* Armada 8k variant gpios register offsets */
75 #define AP80X_GPIO0_OFF_A8K 0x1040
76 #define CP11X_GPIO0_OFF_A8K 0x100
77 #define CP11X_GPIO1_OFF_A8K 0x140
78
79 /* The MV78200 has per-CPU registers for edge mask and level mask */
80 #define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18)
81 #define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C)
82
83 /*
84 * The Armada XP has per-CPU registers for interrupt cause, interrupt
85 * mask and interrupt level mask. Those are in percpu_regs range.
86 */
87 #define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4)
88 #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4)
89 #define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4)
90
91 #define MVEBU_GPIO_SOC_VARIANT_ORION 0x1
92 #define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2
93 #define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3
94 #define MVEBU_GPIO_SOC_VARIANT_A8K 0x4
95
96 #define MVEBU_MAX_GPIO_PER_BANK 32
97
98 struct mvebu_pwm {
99 struct regmap *regs;
100 u32 offset;
101 unsigned long clk_rate;
102 struct gpio_desc *gpiod;
103 spinlock_t lock;
104 struct mvebu_gpio_chip *mvchip;
105
106 /* Used to preserve GPIO/PWM registers across suspend/resume */
107 u32 blink_select;
108 u32 blink_on_duration;
109 u32 blink_off_duration;
110 };
111
112 struct mvebu_gpio_chip {
113 struct gpio_chip chip;
114 struct regmap *regs;
115 u32 offset;
116 struct regmap *percpu_regs;
117 int irqbase;
118 struct irq_domain *domain;
119 int soc_variant;
120
121 /* Used for PWM support */
122 struct clk *clk;
123 struct mvebu_pwm *mvpwm;
124
125 /* Used to preserve GPIO registers across suspend/resume */
126 u32 out_reg;
127 u32 io_conf_reg;
128 u32 blink_en_reg;
129 u32 in_pol_reg;
130 u32 edge_mask_regs[4];
131 u32 level_mask_regs[4];
132 };
133
134 /*
135 * Functions returning addresses of individual registers for a given
136 * GPIO controller.
137 */
138
mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip * mvchip,struct regmap ** map,unsigned int * offset)139 static void mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip,
140 struct regmap **map, unsigned int *offset)
141 {
142 int cpu;
143
144 switch (mvchip->soc_variant) {
145 case MVEBU_GPIO_SOC_VARIANT_ORION:
146 case MVEBU_GPIO_SOC_VARIANT_MV78200:
147 case MVEBU_GPIO_SOC_VARIANT_A8K:
148 *map = mvchip->regs;
149 *offset = GPIO_EDGE_CAUSE_OFF + mvchip->offset;
150 break;
151 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
152 cpu = smp_processor_id();
153 *map = mvchip->percpu_regs;
154 *offset = GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu);
155 break;
156 default:
157 BUG();
158 }
159 }
160
161 static u32
mvebu_gpio_read_edge_cause(struct mvebu_gpio_chip * mvchip)162 mvebu_gpio_read_edge_cause(struct mvebu_gpio_chip *mvchip)
163 {
164 struct regmap *map;
165 unsigned int offset;
166 u32 val;
167
168 mvebu_gpioreg_edge_cause(mvchip, &map, &offset);
169 regmap_read(map, offset, &val);
170
171 return val;
172 }
173
174 static void
mvebu_gpio_write_edge_cause(struct mvebu_gpio_chip * mvchip,u32 val)175 mvebu_gpio_write_edge_cause(struct mvebu_gpio_chip *mvchip, u32 val)
176 {
177 struct regmap *map;
178 unsigned int offset;
179
180 mvebu_gpioreg_edge_cause(mvchip, &map, &offset);
181 regmap_write(map, offset, val);
182 }
183
184 static inline void
mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip * mvchip,struct regmap ** map,unsigned int * offset)185 mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip,
186 struct regmap **map, unsigned int *offset)
187 {
188 int cpu;
189
190 switch (mvchip->soc_variant) {
191 case MVEBU_GPIO_SOC_VARIANT_ORION:
192 case MVEBU_GPIO_SOC_VARIANT_A8K:
193 *map = mvchip->regs;
194 *offset = GPIO_EDGE_MASK_OFF + mvchip->offset;
195 break;
196 case MVEBU_GPIO_SOC_VARIANT_MV78200:
197 cpu = smp_processor_id();
198 *map = mvchip->regs;
199 *offset = GPIO_EDGE_MASK_MV78200_OFF(cpu);
200 break;
201 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
202 cpu = smp_processor_id();
203 *map = mvchip->percpu_regs;
204 *offset = GPIO_EDGE_MASK_ARMADAXP_OFF(cpu);
205 break;
206 default:
207 BUG();
208 }
209 }
210
211 static u32
mvebu_gpio_read_edge_mask(struct mvebu_gpio_chip * mvchip)212 mvebu_gpio_read_edge_mask(struct mvebu_gpio_chip *mvchip)
213 {
214 struct regmap *map;
215 unsigned int offset;
216 u32 val;
217
218 mvebu_gpioreg_edge_mask(mvchip, &map, &offset);
219 regmap_read(map, offset, &val);
220
221 return val;
222 }
223
224 static void
mvebu_gpio_write_edge_mask(struct mvebu_gpio_chip * mvchip,u32 val)225 mvebu_gpio_write_edge_mask(struct mvebu_gpio_chip *mvchip, u32 val)
226 {
227 struct regmap *map;
228 unsigned int offset;
229
230 mvebu_gpioreg_edge_mask(mvchip, &map, &offset);
231 regmap_write(map, offset, val);
232 }
233
234 static void
mvebu_gpioreg_level_mask(struct mvebu_gpio_chip * mvchip,struct regmap ** map,unsigned int * offset)235 mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip,
236 struct regmap **map, unsigned int *offset)
237 {
238 int cpu;
239
240 switch (mvchip->soc_variant) {
241 case MVEBU_GPIO_SOC_VARIANT_ORION:
242 case MVEBU_GPIO_SOC_VARIANT_A8K:
243 *map = mvchip->regs;
244 *offset = GPIO_LEVEL_MASK_OFF + mvchip->offset;
245 break;
246 case MVEBU_GPIO_SOC_VARIANT_MV78200:
247 cpu = smp_processor_id();
248 *map = mvchip->regs;
249 *offset = GPIO_LEVEL_MASK_MV78200_OFF(cpu);
250 break;
251 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
252 cpu = smp_processor_id();
253 *map = mvchip->percpu_regs;
254 *offset = GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu);
255 break;
256 default:
257 BUG();
258 }
259 }
260
261 static u32
mvebu_gpio_read_level_mask(struct mvebu_gpio_chip * mvchip)262 mvebu_gpio_read_level_mask(struct mvebu_gpio_chip *mvchip)
263 {
264 struct regmap *map;
265 unsigned int offset;
266 u32 val;
267
268 mvebu_gpioreg_level_mask(mvchip, &map, &offset);
269 regmap_read(map, offset, &val);
270
271 return val;
272 }
273
274 static void
mvebu_gpio_write_level_mask(struct mvebu_gpio_chip * mvchip,u32 val)275 mvebu_gpio_write_level_mask(struct mvebu_gpio_chip *mvchip, u32 val)
276 {
277 struct regmap *map;
278 unsigned int offset;
279
280 mvebu_gpioreg_level_mask(mvchip, &map, &offset);
281 regmap_write(map, offset, val);
282 }
283
284 /*
285 * Functions returning offsets of individual registers for a given
286 * PWM controller.
287 */
mvebu_pwmreg_blink_on_duration(struct mvebu_pwm * mvpwm)288 static unsigned int mvebu_pwmreg_blink_on_duration(struct mvebu_pwm *mvpwm)
289 {
290 return mvpwm->offset + PWM_BLINK_ON_DURATION_OFF;
291 }
292
mvebu_pwmreg_blink_off_duration(struct mvebu_pwm * mvpwm)293 static unsigned int mvebu_pwmreg_blink_off_duration(struct mvebu_pwm *mvpwm)
294 {
295 return mvpwm->offset + PWM_BLINK_OFF_DURATION_OFF;
296 }
297
298 /*
299 * Functions implementing the gpio_chip methods
300 */
mvebu_gpio_set(struct gpio_chip * chip,unsigned int pin,int value)301 static int mvebu_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
302 {
303 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
304
305 return regmap_update_bits(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
306 BIT(pin), value ? BIT(pin) : 0);
307 }
308
mvebu_gpio_get(struct gpio_chip * chip,unsigned int pin)309 static int mvebu_gpio_get(struct gpio_chip *chip, unsigned int pin)
310 {
311 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
312 u32 u;
313
314 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
315
316 if (u & BIT(pin)) {
317 u32 data_in, in_pol;
318
319 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset,
320 &data_in);
321 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
322 &in_pol);
323 u = data_in ^ in_pol;
324 } else {
325 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &u);
326 }
327
328 return (u >> pin) & 1;
329 }
330
mvebu_gpio_blink(struct gpio_chip * chip,unsigned int pin,int value)331 static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned int pin,
332 int value)
333 {
334 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
335
336 regmap_update_bits(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
337 BIT(pin), value ? BIT(pin) : 0);
338 }
339
mvebu_gpio_direction_input(struct gpio_chip * chip,unsigned int pin)340 static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned int pin)
341 {
342 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
343 int ret;
344
345 /*
346 * Check with the pinctrl driver whether this pin is usable as
347 * an input GPIO
348 */
349 ret = pinctrl_gpio_direction_input(chip, pin);
350 if (ret)
351 return ret;
352
353 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
354 BIT(pin), BIT(pin));
355
356 return 0;
357 }
358
mvebu_gpio_direction_output(struct gpio_chip * chip,unsigned int pin,int value)359 static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned int pin,
360 int value)
361 {
362 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
363 int ret;
364
365 /*
366 * Check with the pinctrl driver whether this pin is usable as
367 * an output GPIO
368 */
369 ret = pinctrl_gpio_direction_output(chip, pin);
370 if (ret)
371 return ret;
372
373 mvebu_gpio_blink(chip, pin, 0);
374 mvebu_gpio_set(chip, pin, value);
375
376 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
377 BIT(pin), 0);
378
379 return 0;
380 }
381
mvebu_gpio_get_direction(struct gpio_chip * chip,unsigned int pin)382 static int mvebu_gpio_get_direction(struct gpio_chip *chip, unsigned int pin)
383 {
384 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
385 u32 u;
386
387 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
388
389 if (u & BIT(pin))
390 return GPIO_LINE_DIRECTION_IN;
391
392 return GPIO_LINE_DIRECTION_OUT;
393 }
394
mvebu_gpio_to_irq(struct gpio_chip * chip,unsigned int pin)395 static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned int pin)
396 {
397 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
398
399 return irq_create_mapping(mvchip->domain, pin);
400 }
401
402 /*
403 * Functions implementing the irq_chip methods
404 */
mvebu_gpio_irq_ack(struct irq_data * d)405 static void mvebu_gpio_irq_ack(struct irq_data *d)
406 {
407 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
408 struct mvebu_gpio_chip *mvchip = gc->private;
409 u32 mask = d->mask;
410
411 guard(raw_spinlock)(&gc->lock);
412 mvebu_gpio_write_edge_cause(mvchip, ~mask);
413 }
414
mvebu_gpio_edge_irq_mask(struct irq_data * d)415 static void mvebu_gpio_edge_irq_mask(struct irq_data *d)
416 {
417 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
418 struct mvebu_gpio_chip *mvchip = gc->private;
419 struct irq_chip_type *ct = irq_data_get_chip_type(d);
420 u32 mask = d->mask;
421
422 guard(raw_spinlock)(&gc->lock);
423 ct->mask_cache_priv &= ~mask;
424 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv);
425 }
426
mvebu_gpio_edge_irq_unmask(struct irq_data * d)427 static void mvebu_gpio_edge_irq_unmask(struct irq_data *d)
428 {
429 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
430 struct mvebu_gpio_chip *mvchip = gc->private;
431 struct irq_chip_type *ct = irq_data_get_chip_type(d);
432 u32 mask = d->mask;
433
434 guard(raw_spinlock)(&gc->lock);
435 mvebu_gpio_write_edge_cause(mvchip, ~mask);
436 ct->mask_cache_priv |= mask;
437 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv);
438 }
439
mvebu_gpio_level_irq_mask(struct irq_data * d)440 static void mvebu_gpio_level_irq_mask(struct irq_data *d)
441 {
442 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
443 struct mvebu_gpio_chip *mvchip = gc->private;
444 struct irq_chip_type *ct = irq_data_get_chip_type(d);
445 u32 mask = d->mask;
446
447 guard(raw_spinlock)(&gc->lock);
448 ct->mask_cache_priv &= ~mask;
449 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv);
450 }
451
mvebu_gpio_level_irq_unmask(struct irq_data * d)452 static void mvebu_gpio_level_irq_unmask(struct irq_data *d)
453 {
454 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
455 struct mvebu_gpio_chip *mvchip = gc->private;
456 struct irq_chip_type *ct = irq_data_get_chip_type(d);
457 u32 mask = d->mask;
458
459 guard(raw_spinlock)(&gc->lock);
460 ct->mask_cache_priv |= mask;
461 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv);
462 }
463
464 /*****************************************************************************
465 * MVEBU GPIO IRQ
466 *
467 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
468 * value of the line or the opposite value.
469 *
470 * Level IRQ handlers: DATA_IN is used directly as cause register.
471 * Interrupt are masked by LEVEL_MASK registers.
472 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
473 * Interrupt are masked by EDGE_MASK registers.
474 * Both-edge handlers: Similar to regular Edge handlers, but also swaps
475 * the polarity to catch the next line transaction.
476 * This is a race condition that might not perfectly
477 * work on some use cases.
478 *
479 * Every eight GPIO lines are grouped (OR'ed) before going up to main
480 * cause register.
481 *
482 * EDGE cause mask
483 * data-in /--------| |-----| |----\
484 * -----| |----- ---- to main cause reg
485 * X \----------------| |----/
486 * polarity LEVEL mask
487 *
488 ****************************************************************************/
489
mvebu_gpio_irq_set_type(struct irq_data * d,unsigned int type)490 static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type)
491 {
492 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
493 struct irq_chip_type *ct = irq_data_get_chip_type(d);
494 struct mvebu_gpio_chip *mvchip = gc->private;
495 int pin;
496 u32 u;
497
498 pin = d->hwirq;
499
500 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
501 if ((u & BIT(pin)) == 0)
502 return -EINVAL;
503
504 type &= IRQ_TYPE_SENSE_MASK;
505 if (type == IRQ_TYPE_NONE)
506 return -EINVAL;
507
508 /* Check if we need to change chip and handler */
509 if (!(ct->type & type))
510 if (irq_setup_alt_chip(d, type))
511 return -EINVAL;
512
513 /*
514 * Configure interrupt polarity.
515 */
516 switch (type) {
517 case IRQ_TYPE_EDGE_RISING:
518 case IRQ_TYPE_LEVEL_HIGH:
519 regmap_update_bits(mvchip->regs,
520 GPIO_IN_POL_OFF + mvchip->offset,
521 BIT(pin), 0);
522 break;
523 case IRQ_TYPE_EDGE_FALLING:
524 case IRQ_TYPE_LEVEL_LOW:
525 regmap_update_bits(mvchip->regs,
526 GPIO_IN_POL_OFF + mvchip->offset,
527 BIT(pin), BIT(pin));
528 break;
529 case IRQ_TYPE_EDGE_BOTH: {
530 u32 data_in, in_pol, val;
531
532 regmap_read(mvchip->regs,
533 GPIO_IN_POL_OFF + mvchip->offset, &in_pol);
534 regmap_read(mvchip->regs,
535 GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
536
537 /*
538 * set initial polarity based on current input level
539 */
540 if ((data_in ^ in_pol) & BIT(pin))
541 val = BIT(pin); /* falling */
542 else
543 val = 0; /* raising */
544
545 regmap_update_bits(mvchip->regs,
546 GPIO_IN_POL_OFF + mvchip->offset,
547 BIT(pin), val);
548 break;
549 }
550 }
551 return 0;
552 }
553
mvebu_gpio_irq_handler(struct irq_desc * desc)554 static void mvebu_gpio_irq_handler(struct irq_desc *desc)
555 {
556 struct mvebu_gpio_chip *mvchip = irq_desc_get_handler_data(desc);
557 struct irq_chip *chip = irq_desc_get_chip(desc);
558 u32 cause, type, data_in, level_mask, edge_cause, edge_mask;
559 int i;
560
561 if (mvchip == NULL)
562 return;
563
564 chained_irq_enter(chip, desc);
565
566 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
567 level_mask = mvebu_gpio_read_level_mask(mvchip);
568 edge_cause = mvebu_gpio_read_edge_cause(mvchip);
569 edge_mask = mvebu_gpio_read_edge_mask(mvchip);
570
571 cause = (data_in & level_mask) | (edge_cause & edge_mask);
572
573 for (i = 0; i < mvchip->chip.ngpio; i++) {
574 int irq;
575
576 irq = irq_find_mapping(mvchip->domain, i);
577
578 if (!(cause & BIT(i)))
579 continue;
580
581 type = irq_get_trigger_type(irq);
582 if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
583 /* Swap polarity (race with GPIO line) */
584 u32 polarity;
585
586 regmap_read(mvchip->regs,
587 GPIO_IN_POL_OFF + mvchip->offset,
588 &polarity);
589 polarity ^= BIT(i);
590 regmap_write(mvchip->regs,
591 GPIO_IN_POL_OFF + mvchip->offset,
592 polarity);
593 }
594
595 generic_handle_irq(irq);
596 }
597
598 chained_irq_exit(chip, desc);
599 }
600
601 static const struct regmap_config mvebu_gpio_regmap_config = {
602 .reg_bits = 32,
603 .reg_stride = 4,
604 .val_bits = 32,
605 };
606
607 /*
608 * Functions implementing the pwm_chip methods
609 */
to_mvebu_pwm(struct pwm_chip * chip)610 static struct mvebu_pwm *to_mvebu_pwm(struct pwm_chip *chip)
611 {
612 return pwmchip_get_drvdata(chip);
613 }
614
mvebu_pwm_request(struct pwm_chip * chip,struct pwm_device * pwm)615 static int mvebu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
616 {
617 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
618 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
619 struct gpio_desc *desc;
620 unsigned long flags;
621 int ret = 0;
622
623 spin_lock_irqsave(&mvpwm->lock, flags);
624
625 if (mvpwm->gpiod) {
626 ret = -EBUSY;
627 } else {
628 desc = gpiochip_request_own_desc(&mvchip->chip,
629 pwm->hwpwm, "mvebu-pwm",
630 GPIO_ACTIVE_HIGH,
631 GPIOD_OUT_LOW);
632 if (IS_ERR(desc)) {
633 ret = PTR_ERR(desc);
634 goto out;
635 }
636
637 mvpwm->gpiod = desc;
638 }
639 out:
640 spin_unlock_irqrestore(&mvpwm->lock, flags);
641 return ret;
642 }
643
mvebu_pwm_free(struct pwm_chip * chip,struct pwm_device * pwm)644 static void mvebu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
645 {
646 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
647 unsigned long flags;
648
649 spin_lock_irqsave(&mvpwm->lock, flags);
650 gpiochip_free_own_desc(mvpwm->gpiod);
651 mvpwm->gpiod = NULL;
652 spin_unlock_irqrestore(&mvpwm->lock, flags);
653 }
654
mvebu_pwm_get_state(struct pwm_chip * chip,struct pwm_device * pwm,struct pwm_state * state)655 static int mvebu_pwm_get_state(struct pwm_chip *chip,
656 struct pwm_device *pwm,
657 struct pwm_state *state)
658 {
659
660 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
661 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
662 unsigned long long val;
663 unsigned long flags;
664 u32 u;
665
666 spin_lock_irqsave(&mvpwm->lock, flags);
667
668 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), &u);
669 /* Hardware treats zero as 2^32. See mvebu_pwm_apply(). */
670 if (u > 0)
671 val = u;
672 else
673 val = UINT_MAX + 1ULL;
674 state->duty_cycle = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC,
675 mvpwm->clk_rate);
676
677 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), &u);
678 /* period = on + off duration */
679 if (u > 0)
680 val += u;
681 else
682 val += UINT_MAX + 1ULL;
683 state->period = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC, mvpwm->clk_rate);
684
685 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &u);
686 if (u)
687 state->enabled = true;
688 else
689 state->enabled = false;
690
691 spin_unlock_irqrestore(&mvpwm->lock, flags);
692
693 return 0;
694 }
695
mvebu_pwm_apply(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)696 static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
697 const struct pwm_state *state)
698 {
699 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
700 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
701 unsigned long long val;
702 unsigned long flags;
703 unsigned int on, off;
704
705 if (state->polarity != PWM_POLARITY_NORMAL)
706 return -EINVAL;
707
708 val = (unsigned long long) mvpwm->clk_rate * state->duty_cycle;
709 do_div(val, NSEC_PER_SEC);
710 if (val > UINT_MAX + 1ULL)
711 return -EINVAL;
712 /*
713 * Zero on/off values don't work as expected. Experimentation shows
714 * that zero value is treated as 2^32. This behavior is not documented.
715 */
716 if (val == UINT_MAX + 1ULL)
717 on = 0;
718 else if (val)
719 on = val;
720 else
721 on = 1;
722
723 val = (unsigned long long) mvpwm->clk_rate * state->period;
724 do_div(val, NSEC_PER_SEC);
725 val -= on;
726 if (val > UINT_MAX + 1ULL)
727 return -EINVAL;
728 if (val == UINT_MAX + 1ULL)
729 off = 0;
730 else if (val)
731 off = val;
732 else
733 off = 1;
734
735 spin_lock_irqsave(&mvpwm->lock, flags);
736
737 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), on);
738 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), off);
739 if (state->enabled)
740 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 1);
741 else
742 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 0);
743
744 spin_unlock_irqrestore(&mvpwm->lock, flags);
745
746 return 0;
747 }
748
749 static const struct pwm_ops mvebu_pwm_ops = {
750 .request = mvebu_pwm_request,
751 .free = mvebu_pwm_free,
752 .get_state = mvebu_pwm_get_state,
753 .apply = mvebu_pwm_apply,
754 };
755
mvebu_pwm_suspend(struct mvebu_gpio_chip * mvchip)756 static void __maybe_unused mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip)
757 {
758 struct mvebu_pwm *mvpwm = mvchip->mvpwm;
759
760 regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
761 &mvpwm->blink_select);
762 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm),
763 &mvpwm->blink_on_duration);
764 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm),
765 &mvpwm->blink_off_duration);
766 }
767
mvebu_pwm_resume(struct mvebu_gpio_chip * mvchip)768 static void __maybe_unused mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip)
769 {
770 struct mvebu_pwm *mvpwm = mvchip->mvpwm;
771
772 regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
773 mvpwm->blink_select);
774 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm),
775 mvpwm->blink_on_duration);
776 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm),
777 mvpwm->blink_off_duration);
778 }
779
mvebu_pwm_probe(struct platform_device * pdev,struct mvebu_gpio_chip * mvchip,int id)780 static int mvebu_pwm_probe(struct platform_device *pdev,
781 struct mvebu_gpio_chip *mvchip,
782 int id)
783 {
784 struct device *dev = &pdev->dev;
785 struct mvebu_pwm *mvpwm;
786 struct pwm_chip *chip;
787 void __iomem *base;
788 u32 offset;
789 u32 set;
790
791 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) {
792 int ret = device_property_read_u32(dev, "marvell,pwm-offset",
793 &offset);
794 if (ret < 0)
795 return 0;
796 } else {
797 /*
798 * There are only two sets of PWM configuration registers for
799 * all the GPIO lines on those SoCs which this driver reserves
800 * for the first two GPIO chips. So if the resource is missing
801 * we can't treat it as an error.
802 */
803 if (!platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm"))
804 return 0;
805 offset = 0;
806 }
807
808 if (IS_ERR(mvchip->clk))
809 return PTR_ERR(mvchip->clk);
810
811 chip = devm_pwmchip_alloc(dev, mvchip->chip.ngpio, sizeof(*mvpwm));
812 if (IS_ERR(chip))
813 return PTR_ERR(chip);
814 mvpwm = to_mvebu_pwm(chip);
815
816 mvchip->mvpwm = mvpwm;
817 mvpwm->mvchip = mvchip;
818 mvpwm->offset = offset;
819
820 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) {
821 mvpwm->regs = mvchip->regs;
822
823 switch (mvchip->offset) {
824 case AP80X_GPIO0_OFF_A8K:
825 case CP11X_GPIO0_OFF_A8K:
826 /* Blink counter A */
827 set = 0;
828 break;
829 case CP11X_GPIO1_OFF_A8K:
830 /* Blink counter B */
831 set = U32_MAX;
832 mvpwm->offset += PWM_BLINK_COUNTER_B_OFF;
833 break;
834 default:
835 return -EINVAL;
836 }
837 } else {
838 base = devm_platform_ioremap_resource_byname(pdev, "pwm");
839 if (IS_ERR(base))
840 return PTR_ERR(base);
841
842 mvpwm->regs = devm_regmap_init_mmio(&pdev->dev, base,
843 &mvebu_gpio_regmap_config);
844 if (IS_ERR(mvpwm->regs))
845 return PTR_ERR(mvpwm->regs);
846
847 /*
848 * Use set A for lines of GPIO chip with id 0, B for GPIO chip
849 * with id 1. Don't allow further GPIO chips to be used for PWM.
850 */
851 if (id == 0)
852 set = 0;
853 else if (id == 1)
854 set = U32_MAX;
855 else
856 return -EINVAL;
857 }
858
859 regmap_write(mvchip->regs,
860 GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, set);
861
862 mvpwm->clk_rate = clk_get_rate(mvchip->clk);
863 if (!mvpwm->clk_rate) {
864 dev_err(dev, "failed to get clock rate\n");
865 return -EINVAL;
866 }
867
868 chip->ops = &mvebu_pwm_ops;
869
870 spin_lock_init(&mvpwm->lock);
871
872 return devm_pwmchip_add(dev, chip);
873 }
874
875 #ifdef CONFIG_DEBUG_FS
876 #include <linux/seq_file.h>
877
mvebu_gpio_dbg_show(struct seq_file * s,struct gpio_chip * chip)878 static void mvebu_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
879 {
880 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
881 u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk;
882 const char *label;
883 int i;
884
885 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &out);
886 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &io_conf);
887 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &blink);
888 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, &in_pol);
889 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
890 cause = mvebu_gpio_read_edge_cause(mvchip);
891 edg_msk = mvebu_gpio_read_edge_mask(mvchip);
892 lvl_msk = mvebu_gpio_read_level_mask(mvchip);
893
894 for_each_requested_gpio(chip, i, label) {
895 u32 msk;
896 bool is_out;
897
898 msk = BIT(i);
899 is_out = !(io_conf & msk);
900
901 seq_printf(s, " gpio-%-3d (%-20.20s)", i, label);
902
903 if (is_out) {
904 seq_printf(s, " out %s %s\n",
905 str_hi_lo(out & msk),
906 blink & msk ? "(blink )" : "");
907 continue;
908 }
909
910 seq_printf(s, " in %s (act %s) - IRQ",
911 str_hi_lo((data_in ^ in_pol) & msk),
912 str_lo_hi(in_pol & msk));
913 if (!((edg_msk | lvl_msk) & msk)) {
914 seq_puts(s, " disabled\n");
915 continue;
916 }
917 if (edg_msk & msk)
918 seq_puts(s, " edge ");
919 if (lvl_msk & msk)
920 seq_puts(s, " level");
921 seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear ");
922 }
923 }
924 #else
925 #define mvebu_gpio_dbg_show NULL
926 #endif
927
928 static const struct of_device_id mvebu_gpio_of_match[] = {
929 {
930 .compatible = "marvell,orion-gpio",
931 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
932 },
933 {
934 .compatible = "marvell,mv78200-gpio",
935 .data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200,
936 },
937 {
938 .compatible = "marvell,armadaxp-gpio",
939 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP,
940 },
941 {
942 .compatible = "marvell,armada-370-gpio",
943 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
944 },
945 {
946 .compatible = "marvell,armada-8k-gpio",
947 .data = (void *) MVEBU_GPIO_SOC_VARIANT_A8K,
948 },
949 {
950 /* sentinel */
951 },
952 };
953
mvebu_gpio_suspend(struct platform_device * pdev,pm_message_t state)954 static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state)
955 {
956 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
957 int i;
958
959 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
960 &mvchip->out_reg);
961 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
962 &mvchip->io_conf_reg);
963 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
964 &mvchip->blink_en_reg);
965 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
966 &mvchip->in_pol_reg);
967
968 switch (mvchip->soc_variant) {
969 case MVEBU_GPIO_SOC_VARIANT_ORION:
970 case MVEBU_GPIO_SOC_VARIANT_A8K:
971 regmap_read(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset,
972 &mvchip->edge_mask_regs[0]);
973 regmap_read(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset,
974 &mvchip->level_mask_regs[0]);
975 break;
976 case MVEBU_GPIO_SOC_VARIANT_MV78200:
977 for (i = 0; i < 2; i++) {
978 regmap_read(mvchip->regs,
979 GPIO_EDGE_MASK_MV78200_OFF(i),
980 &mvchip->edge_mask_regs[i]);
981 regmap_read(mvchip->regs,
982 GPIO_LEVEL_MASK_MV78200_OFF(i),
983 &mvchip->level_mask_regs[i]);
984 }
985 break;
986 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
987 for (i = 0; i < 4; i++) {
988 regmap_read(mvchip->regs,
989 GPIO_EDGE_MASK_ARMADAXP_OFF(i),
990 &mvchip->edge_mask_regs[i]);
991 regmap_read(mvchip->regs,
992 GPIO_LEVEL_MASK_ARMADAXP_OFF(i),
993 &mvchip->level_mask_regs[i]);
994 }
995 break;
996 default:
997 BUG();
998 }
999
1000 if (IS_REACHABLE(CONFIG_PWM))
1001 mvebu_pwm_suspend(mvchip);
1002
1003 return 0;
1004 }
1005
mvebu_gpio_resume(struct platform_device * pdev)1006 static int mvebu_gpio_resume(struct platform_device *pdev)
1007 {
1008 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
1009 int i;
1010
1011 regmap_write(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
1012 mvchip->out_reg);
1013 regmap_write(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
1014 mvchip->io_conf_reg);
1015 regmap_write(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
1016 mvchip->blink_en_reg);
1017 regmap_write(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
1018 mvchip->in_pol_reg);
1019
1020 switch (mvchip->soc_variant) {
1021 case MVEBU_GPIO_SOC_VARIANT_ORION:
1022 case MVEBU_GPIO_SOC_VARIANT_A8K:
1023 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset,
1024 mvchip->edge_mask_regs[0]);
1025 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset,
1026 mvchip->level_mask_regs[0]);
1027 break;
1028 case MVEBU_GPIO_SOC_VARIANT_MV78200:
1029 for (i = 0; i < 2; i++) {
1030 regmap_write(mvchip->regs,
1031 GPIO_EDGE_MASK_MV78200_OFF(i),
1032 mvchip->edge_mask_regs[i]);
1033 regmap_write(mvchip->regs,
1034 GPIO_LEVEL_MASK_MV78200_OFF(i),
1035 mvchip->level_mask_regs[i]);
1036 }
1037 break;
1038 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
1039 for (i = 0; i < 4; i++) {
1040 regmap_write(mvchip->regs,
1041 GPIO_EDGE_MASK_ARMADAXP_OFF(i),
1042 mvchip->edge_mask_regs[i]);
1043 regmap_write(mvchip->regs,
1044 GPIO_LEVEL_MASK_ARMADAXP_OFF(i),
1045 mvchip->level_mask_regs[i]);
1046 }
1047 break;
1048 default:
1049 BUG();
1050 }
1051
1052 if (IS_REACHABLE(CONFIG_PWM))
1053 mvebu_pwm_resume(mvchip);
1054
1055 return 0;
1056 }
1057
mvebu_gpio_probe_raw(struct platform_device * pdev,struct mvebu_gpio_chip * mvchip)1058 static int mvebu_gpio_probe_raw(struct platform_device *pdev,
1059 struct mvebu_gpio_chip *mvchip)
1060 {
1061 void __iomem *base;
1062
1063 base = devm_platform_ioremap_resource(pdev, 0);
1064 if (IS_ERR(base))
1065 return PTR_ERR(base);
1066
1067 mvchip->regs = devm_regmap_init_mmio(&pdev->dev, base,
1068 &mvebu_gpio_regmap_config);
1069 if (IS_ERR(mvchip->regs))
1070 return PTR_ERR(mvchip->regs);
1071
1072 /*
1073 * For the legacy SoCs, the regmap directly maps to the GPIO
1074 * registers, so no offset is needed.
1075 */
1076 mvchip->offset = 0;
1077
1078 /*
1079 * The Armada XP has a second range of registers for the
1080 * per-CPU registers
1081 */
1082 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) {
1083 base = devm_platform_ioremap_resource(pdev, 1);
1084 if (IS_ERR(base))
1085 return PTR_ERR(base);
1086
1087 mvchip->percpu_regs =
1088 devm_regmap_init_mmio(&pdev->dev, base,
1089 &mvebu_gpio_regmap_config);
1090 if (IS_ERR(mvchip->percpu_regs))
1091 return PTR_ERR(mvchip->percpu_regs);
1092 }
1093
1094 return 0;
1095 }
1096
mvebu_gpio_probe_syscon(struct platform_device * pdev,struct mvebu_gpio_chip * mvchip)1097 static int mvebu_gpio_probe_syscon(struct platform_device *pdev,
1098 struct mvebu_gpio_chip *mvchip)
1099 {
1100 mvchip->regs = syscon_node_to_regmap(pdev->dev.parent->of_node);
1101 if (IS_ERR(mvchip->regs))
1102 return PTR_ERR(mvchip->regs);
1103
1104 if (device_property_read_u32(&pdev->dev, "offset", &mvchip->offset))
1105 return -EINVAL;
1106
1107 return 0;
1108 }
1109
mvebu_gpio_remove_irq_domain(void * data)1110 static void mvebu_gpio_remove_irq_domain(void *data)
1111 {
1112 struct irq_domain *domain = data;
1113
1114 irq_domain_remove(domain);
1115 }
1116
mvebu_gpio_probe(struct platform_device * pdev)1117 static int mvebu_gpio_probe(struct platform_device *pdev)
1118 {
1119 struct mvebu_gpio_chip *mvchip;
1120 struct device_node *np = pdev->dev.of_node;
1121 struct irq_chip_generic *gc;
1122 struct irq_chip_type *ct;
1123 unsigned int ngpios;
1124 bool have_irqs;
1125 int soc_variant;
1126 int i, cpu, id;
1127 int err;
1128
1129 soc_variant = (unsigned long)device_get_match_data(&pdev->dev);
1130
1131 /* Some gpio controllers do not provide irq support */
1132 err = platform_irq_count(pdev);
1133 if (err < 0)
1134 return err;
1135
1136 have_irqs = err != 0;
1137
1138 mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip),
1139 GFP_KERNEL);
1140 if (!mvchip)
1141 return -ENOMEM;
1142
1143 platform_set_drvdata(pdev, mvchip);
1144
1145 if (device_property_read_u32(&pdev->dev, "ngpios", &ngpios)) {
1146 dev_err(&pdev->dev, "Missing ngpios OF property\n");
1147 return -ENODEV;
1148 }
1149
1150 id = of_alias_get_id(pdev->dev.of_node, "gpio");
1151 if (id < 0) {
1152 dev_err(&pdev->dev, "Couldn't get OF id\n");
1153 return id;
1154 }
1155
1156 mvchip->clk = devm_clk_get(&pdev->dev, NULL);
1157 /* Not all SoCs require a clock.*/
1158 if (!IS_ERR(mvchip->clk))
1159 clk_prepare_enable(mvchip->clk);
1160
1161 mvchip->soc_variant = soc_variant;
1162 mvchip->chip.label = dev_name(&pdev->dev);
1163 mvchip->chip.parent = &pdev->dev;
1164 mvchip->chip.request = gpiochip_generic_request;
1165 mvchip->chip.free = gpiochip_generic_free;
1166 mvchip->chip.get_direction = mvebu_gpio_get_direction;
1167 mvchip->chip.direction_input = mvebu_gpio_direction_input;
1168 mvchip->chip.get = mvebu_gpio_get;
1169 mvchip->chip.direction_output = mvebu_gpio_direction_output;
1170 mvchip->chip.set = mvebu_gpio_set;
1171 if (have_irqs)
1172 mvchip->chip.to_irq = mvebu_gpio_to_irq;
1173 mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK;
1174 mvchip->chip.ngpio = ngpios;
1175 mvchip->chip.can_sleep = false;
1176 mvchip->chip.dbg_show = mvebu_gpio_dbg_show;
1177
1178 if (soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K)
1179 err = mvebu_gpio_probe_syscon(pdev, mvchip);
1180 else
1181 err = mvebu_gpio_probe_raw(pdev, mvchip);
1182
1183 if (err)
1184 return err;
1185
1186 /*
1187 * Mask and clear GPIO interrupts.
1188 */
1189 switch (soc_variant) {
1190 case MVEBU_GPIO_SOC_VARIANT_ORION:
1191 case MVEBU_GPIO_SOC_VARIANT_A8K:
1192 regmap_write(mvchip->regs,
1193 GPIO_EDGE_CAUSE_OFF + mvchip->offset, 0);
1194 regmap_write(mvchip->regs,
1195 GPIO_EDGE_MASK_OFF + mvchip->offset, 0);
1196 regmap_write(mvchip->regs,
1197 GPIO_LEVEL_MASK_OFF + mvchip->offset, 0);
1198 break;
1199 case MVEBU_GPIO_SOC_VARIANT_MV78200:
1200 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
1201 for (cpu = 0; cpu < 2; cpu++) {
1202 regmap_write(mvchip->regs,
1203 GPIO_EDGE_MASK_MV78200_OFF(cpu), 0);
1204 regmap_write(mvchip->regs,
1205 GPIO_LEVEL_MASK_MV78200_OFF(cpu), 0);
1206 }
1207 break;
1208 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
1209 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
1210 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF, 0);
1211 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF, 0);
1212 for (cpu = 0; cpu < 4; cpu++) {
1213 regmap_write(mvchip->percpu_regs,
1214 GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu), 0);
1215 regmap_write(mvchip->percpu_regs,
1216 GPIO_EDGE_MASK_ARMADAXP_OFF(cpu), 0);
1217 regmap_write(mvchip->percpu_regs,
1218 GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu), 0);
1219 }
1220 break;
1221 default:
1222 BUG();
1223 }
1224
1225 devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip);
1226
1227 /* Some MVEBU SoCs have simple PWM support for GPIO lines */
1228 if (IS_REACHABLE(CONFIG_PWM)) {
1229 err = mvebu_pwm_probe(pdev, mvchip, id);
1230 if (err)
1231 return err;
1232 }
1233
1234 /* Some gpio controllers do not provide irq support */
1235 if (!have_irqs)
1236 return 0;
1237
1238 mvchip->domain = irq_domain_create_linear(dev_fwnode(&pdev->dev), ngpios,
1239 &irq_generic_chip_ops, NULL);
1240 if (!mvchip->domain) {
1241 dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n",
1242 mvchip->chip.label);
1243 return -ENODEV;
1244 }
1245
1246 err = devm_add_action_or_reset(&pdev->dev, mvebu_gpio_remove_irq_domain,
1247 mvchip->domain);
1248 if (err)
1249 return err;
1250
1251 err = irq_alloc_domain_generic_chips(
1252 mvchip->domain, ngpios, 2, np->name, handle_level_irq,
1253 IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, 0);
1254 if (err) {
1255 dev_err(&pdev->dev, "couldn't allocate irq chips %s (DT).\n",
1256 mvchip->chip.label);
1257 return err;
1258 }
1259
1260 /*
1261 * NOTE: The common accessors cannot be used because of the percpu
1262 * access to the mask registers
1263 */
1264 gc = irq_get_domain_generic_chip(mvchip->domain, 0);
1265 gc->private = mvchip;
1266 ct = &gc->chip_types[0];
1267 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
1268 ct->chip.irq_mask = mvebu_gpio_level_irq_mask;
1269 ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask;
1270 ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
1271 ct->chip.name = mvchip->chip.label;
1272
1273 ct = &gc->chip_types[1];
1274 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
1275 ct->chip.irq_ack = mvebu_gpio_irq_ack;
1276 ct->chip.irq_mask = mvebu_gpio_edge_irq_mask;
1277 ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask;
1278 ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
1279 ct->handler = handle_edge_irq;
1280 ct->chip.name = mvchip->chip.label;
1281
1282 /*
1283 * Setup the interrupt handlers. Each chip can have up to 4
1284 * interrupt handlers, with each handler dealing with 8 GPIO
1285 * pins.
1286 */
1287 for (i = 0; i < 4; i++) {
1288 int irq = platform_get_irq_optional(pdev, i);
1289
1290 if (irq < 0)
1291 continue;
1292 irq_set_chained_handler_and_data(irq, mvebu_gpio_irq_handler,
1293 mvchip);
1294 }
1295
1296 return 0;
1297 }
1298
1299 static struct platform_driver mvebu_gpio_driver = {
1300 .driver = {
1301 .name = "mvebu-gpio",
1302 .of_match_table = mvebu_gpio_of_match,
1303 },
1304 .probe = mvebu_gpio_probe,
1305 .suspend = mvebu_gpio_suspend,
1306 .resume = mvebu_gpio_resume,
1307 };
1308 builtin_platform_driver(mvebu_gpio_driver);
1309