1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2011 Jamie Iles
4 *
5 * All enquiries to support@picochip.com
6 */
7 #include <linux/acpi.h>
8 #include <linux/clk.h>
9 #include <linux/err.h>
10 #include <linux/gpio/driver.h>
11 #include <linux/gpio/generic.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/io.h>
15 #include <linux/ioport.h>
16 #include <linux/irq.h>
17 #include <linux/mod_devicetable.h>
18 #include <linux/module.h>
19 #include <linux/platform_device.h>
20 #include <linux/property.h>
21 #include <linux/reset.h>
22 #include <linux/slab.h>
23 #include <linux/spinlock.h>
24
25 #include "gpiolib-acpi.h"
26
27 #define GPIO_SWPORTA_DR 0x00
28 #define GPIO_SWPORTA_DDR 0x04
29 #define GPIO_SWPORTB_DR 0x0c
30 #define GPIO_SWPORTB_DDR 0x10
31 #define GPIO_SWPORTC_DR 0x18
32 #define GPIO_SWPORTC_DDR 0x1c
33 #define GPIO_SWPORTD_DR 0x24
34 #define GPIO_SWPORTD_DDR 0x28
35 #define GPIO_INTEN 0x30
36 #define GPIO_INTMASK 0x34
37 #define GPIO_INTTYPE_LEVEL 0x38
38 #define GPIO_INT_POLARITY 0x3c
39 #define GPIO_INTSTATUS 0x40
40 #define GPIO_PORTA_DEBOUNCE 0x48
41 #define GPIO_PORTA_EOI 0x4c
42 #define GPIO_EXT_PORTA 0x50
43 #define GPIO_EXT_PORTB 0x54
44 #define GPIO_EXT_PORTC 0x58
45 #define GPIO_EXT_PORTD 0x5c
46
47 #define DWAPB_DRIVER_NAME "gpio-dwapb"
48 #define DWAPB_MAX_PORTS 4
49 #define DWAPB_MAX_GPIOS 32
50
51 #define GPIO_EXT_PORT_STRIDE 0x04 /* register stride 32 bits */
52 #define GPIO_SWPORT_DR_STRIDE 0x0c /* register stride 3*32 bits */
53 #define GPIO_SWPORT_DDR_STRIDE 0x0c /* register stride 3*32 bits */
54
55 #define GPIO_REG_OFFSET_V1 0
56 #define GPIO_REG_OFFSET_V2 1
57 #define GPIO_REG_OFFSET_MASK BIT(0)
58
59 #define GPIO_INTMASK_V2 0x44
60 #define GPIO_INTTYPE_LEVEL_V2 0x34
61 #define GPIO_INT_POLARITY_V2 0x38
62 #define GPIO_INTSTATUS_V2 0x3c
63 #define GPIO_PORTA_EOI_V2 0x40
64
65 #define DWAPB_NR_CLOCKS 2
66
67 struct dwapb_gpio;
68
69 struct dwapb_port_property {
70 struct fwnode_handle *fwnode;
71 unsigned int idx;
72 unsigned int ngpio;
73 unsigned int gpio_base;
74 int irq[DWAPB_MAX_GPIOS];
75 };
76
77 struct dwapb_platform_data {
78 struct dwapb_port_property *properties;
79 unsigned int nports;
80 };
81
82 #ifdef CONFIG_PM_SLEEP
83 /* Store GPIO context across system-wide suspend/resume transitions */
84 struct dwapb_context {
85 u32 data;
86 u32 dir;
87 u32 ext;
88 u32 int_en;
89 u32 int_mask;
90 u32 int_type;
91 u32 int_pol;
92 u32 int_deb;
93 u32 wake_en;
94 };
95 #endif
96
97 struct dwapb_gpio_port_irqchip {
98 unsigned int nr_irqs;
99 unsigned int irq[DWAPB_MAX_GPIOS];
100 };
101
102 struct dwapb_gpio_port {
103 struct gpio_generic_chip chip;
104 struct dwapb_gpio_port_irqchip *pirq;
105 struct dwapb_gpio *gpio;
106 #ifdef CONFIG_PM_SLEEP
107 struct dwapb_context *ctx;
108 #endif
109 unsigned int idx;
110 };
111
to_dwapb_gpio(struct gpio_chip * gc)112 static inline struct dwapb_gpio *to_dwapb_gpio(struct gpio_chip *gc)
113 {
114 return container_of(to_gpio_generic_chip(gc),
115 struct dwapb_gpio_port, chip)->gpio;
116 }
117
118 struct dwapb_gpio {
119 struct device *dev;
120 void __iomem *regs;
121 struct dwapb_gpio_port *ports;
122 unsigned int nr_ports;
123 unsigned int flags;
124 struct reset_control *rst;
125 struct clk_bulk_data clks[DWAPB_NR_CLOCKS];
126 };
127
gpio_reg_v2_convert(unsigned int offset)128 static inline u32 gpio_reg_v2_convert(unsigned int offset)
129 {
130 switch (offset) {
131 case GPIO_INTMASK:
132 return GPIO_INTMASK_V2;
133 case GPIO_INTTYPE_LEVEL:
134 return GPIO_INTTYPE_LEVEL_V2;
135 case GPIO_INT_POLARITY:
136 return GPIO_INT_POLARITY_V2;
137 case GPIO_INTSTATUS:
138 return GPIO_INTSTATUS_V2;
139 case GPIO_PORTA_EOI:
140 return GPIO_PORTA_EOI_V2;
141 }
142
143 return offset;
144 }
145
gpio_reg_convert(struct dwapb_gpio * gpio,unsigned int offset)146 static inline u32 gpio_reg_convert(struct dwapb_gpio *gpio, unsigned int offset)
147 {
148 if ((gpio->flags & GPIO_REG_OFFSET_MASK) == GPIO_REG_OFFSET_V2)
149 return gpio_reg_v2_convert(offset);
150
151 return offset;
152 }
153
dwapb_read(struct dwapb_gpio * gpio,unsigned int offset)154 static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
155 {
156 struct gpio_generic_chip *chip = &gpio->ports[0].chip;
157 void __iomem *reg_base = gpio->regs;
158
159 return gpio_generic_read_reg(chip, reg_base + gpio_reg_convert(gpio, offset));
160 }
161
dwapb_write(struct dwapb_gpio * gpio,unsigned int offset,u32 val)162 static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
163 u32 val)
164 {
165 struct gpio_generic_chip *chip = &gpio->ports[0].chip;
166 void __iomem *reg_base = gpio->regs;
167
168 gpio_generic_write_reg(chip, reg_base + gpio_reg_convert(gpio, offset), val);
169 }
170
dwapb_offs_to_port(struct dwapb_gpio * gpio,unsigned int offs)171 static struct dwapb_gpio_port *dwapb_offs_to_port(struct dwapb_gpio *gpio, unsigned int offs)
172 {
173 struct dwapb_gpio_port *port;
174 int i;
175
176 for (i = 0; i < gpio->nr_ports; i++) {
177 port = &gpio->ports[i];
178 if (port->idx == offs / DWAPB_MAX_GPIOS)
179 return port;
180 }
181
182 return NULL;
183 }
184
dwapb_toggle_trigger(struct dwapb_gpio * gpio,unsigned int offs)185 static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
186 {
187 struct dwapb_gpio_port *port = dwapb_offs_to_port(gpio, offs);
188 struct gpio_chip *gc;
189 u32 pol;
190 int val;
191
192 if (!port)
193 return;
194 gc = &port->chip.gc;
195
196 pol = dwapb_read(gpio, GPIO_INT_POLARITY);
197 /* Just read the current value right out of the data register */
198 val = gc->get(gc, offs % DWAPB_MAX_GPIOS);
199 if (val)
200 pol &= ~BIT(offs);
201 else
202 pol |= BIT(offs);
203
204 dwapb_write(gpio, GPIO_INT_POLARITY, pol);
205 }
206
dwapb_do_irq(struct dwapb_gpio * gpio)207 static u32 dwapb_do_irq(struct dwapb_gpio *gpio)
208 {
209 struct gpio_generic_chip *gen_gc = &gpio->ports[0].chip;
210 unsigned long irq_status;
211 irq_hw_number_t hwirq;
212
213 irq_status = dwapb_read(gpio, GPIO_INTSTATUS);
214 for_each_set_bit(hwirq, &irq_status, DWAPB_MAX_GPIOS) {
215 int gpio_irq = irq_find_mapping(gen_gc->gc.irq.domain, hwirq);
216 u32 irq_type = irq_get_trigger_type(gpio_irq);
217
218 generic_handle_irq(gpio_irq);
219
220 if ((irq_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
221 dwapb_toggle_trigger(gpio, hwirq);
222 }
223
224 return irq_status;
225 }
226
dwapb_irq_handler(struct irq_desc * desc)227 static void dwapb_irq_handler(struct irq_desc *desc)
228 {
229 struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc);
230 struct irq_chip *chip = irq_desc_get_chip(desc);
231
232 chained_irq_enter(chip, desc);
233 dwapb_do_irq(gpio);
234 chained_irq_exit(chip, desc);
235 }
236
dwapb_irq_handler_mfd(int irq,void * dev_id)237 static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id)
238 {
239 return IRQ_RETVAL(dwapb_do_irq(dev_id));
240 }
241
dwapb_irq_ack(struct irq_data * d)242 static void dwapb_irq_ack(struct irq_data *d)
243 {
244 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
245 struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc);
246 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
247 u32 val = BIT(irqd_to_hwirq(d));
248
249 guard(gpio_generic_lock_irqsave)(gen_gc);
250
251 dwapb_write(gpio, GPIO_PORTA_EOI, val);
252 }
253
dwapb_irq_mask(struct irq_data * d)254 static void dwapb_irq_mask(struct irq_data *d)
255 {
256 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
257 struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc);
258 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
259 irq_hw_number_t hwirq = irqd_to_hwirq(d);
260 u32 val;
261
262 scoped_guard(gpio_generic_lock_irqsave, gen_gc) {
263 val = dwapb_read(gpio, GPIO_INTMASK) | BIT(hwirq);
264 dwapb_write(gpio, GPIO_INTMASK, val);
265 }
266
267 gpiochip_disable_irq(gc, hwirq);
268 }
269
dwapb_irq_unmask(struct irq_data * d)270 static void dwapb_irq_unmask(struct irq_data *d)
271 {
272 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
273 struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc);
274 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
275 irq_hw_number_t hwirq = irqd_to_hwirq(d);
276 u32 val;
277
278 gpiochip_enable_irq(gc, hwirq);
279
280 guard(gpio_generic_lock_irqsave)(gen_gc);
281
282 val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(hwirq);
283 dwapb_write(gpio, GPIO_INTMASK, val);
284 }
285
dwapb_irq_enable(struct irq_data * d)286 static void dwapb_irq_enable(struct irq_data *d)
287 {
288 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
289 struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc);
290 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
291 irq_hw_number_t hwirq = irqd_to_hwirq(d);
292 u32 val;
293
294 guard(gpio_generic_lock_irqsave)(gen_gc);
295
296 val = dwapb_read(gpio, GPIO_INTEN) | BIT(hwirq);
297 dwapb_write(gpio, GPIO_INTEN, val);
298 val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(hwirq);
299 dwapb_write(gpio, GPIO_INTMASK, val);
300 }
301
dwapb_irq_disable(struct irq_data * d)302 static void dwapb_irq_disable(struct irq_data *d)
303 {
304 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
305 struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc);
306 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
307 irq_hw_number_t hwirq = irqd_to_hwirq(d);
308 u32 val;
309
310 guard(gpio_generic_lock_irqsave)(gen_gc);
311
312 val = dwapb_read(gpio, GPIO_INTMASK) | BIT(hwirq);
313 dwapb_write(gpio, GPIO_INTMASK, val);
314 val = dwapb_read(gpio, GPIO_INTEN) & ~BIT(hwirq);
315 dwapb_write(gpio, GPIO_INTEN, val);
316 }
317
dwapb_irq_set_type(struct irq_data * d,u32 type)318 static int dwapb_irq_set_type(struct irq_data *d, u32 type)
319 {
320 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
321 struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc);
322 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
323 irq_hw_number_t bit = irqd_to_hwirq(d);
324 unsigned long level, polarity;
325
326 guard(gpio_generic_lock_irqsave)(gen_gc);
327
328 level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
329 polarity = dwapb_read(gpio, GPIO_INT_POLARITY);
330
331 switch (type) {
332 case IRQ_TYPE_EDGE_BOTH:
333 level |= BIT(bit);
334 dwapb_toggle_trigger(gpio, bit);
335 break;
336 case IRQ_TYPE_EDGE_RISING:
337 level |= BIT(bit);
338 polarity |= BIT(bit);
339 break;
340 case IRQ_TYPE_EDGE_FALLING:
341 level |= BIT(bit);
342 polarity &= ~BIT(bit);
343 break;
344 case IRQ_TYPE_LEVEL_HIGH:
345 level &= ~BIT(bit);
346 polarity |= BIT(bit);
347 break;
348 case IRQ_TYPE_LEVEL_LOW:
349 level &= ~BIT(bit);
350 polarity &= ~BIT(bit);
351 break;
352 }
353
354 if (type & IRQ_TYPE_LEVEL_MASK)
355 irq_set_handler_locked(d, handle_level_irq);
356 else if (type & IRQ_TYPE_EDGE_BOTH)
357 irq_set_handler_locked(d, handle_edge_irq);
358
359 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
360 if (type != IRQ_TYPE_EDGE_BOTH)
361 dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
362
363 return 0;
364 }
365
366 #ifdef CONFIG_PM_SLEEP
dwapb_irq_set_wake(struct irq_data * d,unsigned int enable)367 static int dwapb_irq_set_wake(struct irq_data *d, unsigned int enable)
368 {
369 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
370 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
371 struct dwapb_context *ctx = gpio->ports[0].ctx;
372 irq_hw_number_t bit = irqd_to_hwirq(d);
373
374 if (enable)
375 ctx->wake_en |= BIT(bit);
376 else
377 ctx->wake_en &= ~BIT(bit);
378
379 return 0;
380 }
381 #else
382 #define dwapb_irq_set_wake NULL
383 #endif
384
385 static const struct irq_chip dwapb_irq_chip = {
386 .name = DWAPB_DRIVER_NAME,
387 .irq_ack = dwapb_irq_ack,
388 .irq_mask = dwapb_irq_mask,
389 .irq_unmask = dwapb_irq_unmask,
390 .irq_set_type = dwapb_irq_set_type,
391 .irq_enable = dwapb_irq_enable,
392 .irq_disable = dwapb_irq_disable,
393 .irq_set_wake = dwapb_irq_set_wake,
394 .flags = IRQCHIP_IMMUTABLE,
395 GPIOCHIP_IRQ_RESOURCE_HELPERS,
396 };
397
dwapb_gpio_set_debounce(struct gpio_chip * gc,unsigned offset,unsigned debounce)398 static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
399 unsigned offset, unsigned debounce)
400 {
401 struct dwapb_gpio_port *port = gpiochip_get_data(gc);
402 struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc);
403 struct dwapb_gpio *gpio = port->gpio;
404 unsigned long val_deb;
405 unsigned long mask = BIT(offset);
406
407 guard(gpio_generic_lock_irqsave)(gen_gc);
408
409 val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
410 if (debounce)
411 val_deb |= mask;
412 else
413 val_deb &= ~mask;
414 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb);
415
416 return 0;
417 }
418
dwapb_gpio_set_config(struct gpio_chip * gc,unsigned offset,unsigned long config)419 static int dwapb_gpio_set_config(struct gpio_chip *gc, unsigned offset,
420 unsigned long config)
421 {
422 u32 debounce;
423
424 if (pinconf_to_config_param(config) == PIN_CONFIG_INPUT_DEBOUNCE) {
425 debounce = pinconf_to_config_argument(config);
426 return dwapb_gpio_set_debounce(gc, offset, debounce);
427 }
428
429 return gpiochip_generic_config(gc, offset, config);
430 }
431
dwapb_convert_irqs(struct dwapb_gpio_port_irqchip * pirq,struct dwapb_port_property * pp)432 static int dwapb_convert_irqs(struct dwapb_gpio_port_irqchip *pirq,
433 struct dwapb_port_property *pp)
434 {
435 int i;
436
437 /* Group all available IRQs into an array of parental IRQs. */
438 for (i = 0; i < pp->ngpio; ++i) {
439 if (!pp->irq[i])
440 continue;
441
442 pirq->irq[pirq->nr_irqs++] = pp->irq[i];
443 }
444
445 return pirq->nr_irqs ? 0 : -ENOENT;
446 }
447
dwapb_configure_irqs(struct dwapb_gpio * gpio,struct dwapb_gpio_port * port,struct dwapb_port_property * pp)448 static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
449 struct dwapb_gpio_port *port,
450 struct dwapb_port_property *pp)
451 {
452 struct dwapb_gpio_port_irqchip *pirq;
453 struct gpio_chip *gc = &port->chip.gc;
454 struct gpio_irq_chip *girq;
455 int err;
456
457 pirq = devm_kzalloc(gpio->dev, sizeof(*pirq), GFP_KERNEL);
458 if (!pirq)
459 return;
460
461 if (dwapb_convert_irqs(pirq, pp)) {
462 dev_warn(gpio->dev, "no IRQ for port%d\n", pp->idx);
463 goto err_kfree_pirq;
464 }
465
466 girq = &gc->irq;
467 girq->handler = handle_bad_irq;
468 girq->default_type = IRQ_TYPE_NONE;
469
470 port->pirq = pirq;
471
472 /*
473 * Intel ACPI-based platforms mostly have the DesignWare APB GPIO
474 * IRQ lane shared between several devices. In that case the parental
475 * IRQ has to be handled in the shared way so to be properly delivered
476 * to all the connected devices.
477 */
478 if (has_acpi_companion(gpio->dev)) {
479 girq->num_parents = 0;
480 girq->parents = NULL;
481 girq->parent_handler = NULL;
482
483 err = devm_request_irq(gpio->dev, pp->irq[0],
484 dwapb_irq_handler_mfd,
485 IRQF_SHARED, DWAPB_DRIVER_NAME, gpio);
486 if (err) {
487 dev_err(gpio->dev, "error requesting IRQ\n");
488 goto err_kfree_pirq;
489 }
490 } else {
491 girq->num_parents = pirq->nr_irqs;
492 girq->parents = pirq->irq;
493 girq->parent_handler_data = gpio;
494 girq->parent_handler = dwapb_irq_handler;
495 }
496
497 gpio_irq_chip_set_chip(girq, &dwapb_irq_chip);
498
499 return;
500
501 err_kfree_pirq:
502 devm_kfree(gpio->dev, pirq);
503 }
504
dwapb_gpio_add_port(struct dwapb_gpio * gpio,struct dwapb_port_property * pp,unsigned int offs)505 static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
506 struct dwapb_port_property *pp,
507 unsigned int offs)
508 {
509 struct gpio_generic_chip_config config;
510 struct dwapb_gpio_port *port;
511 void __iomem *dat, *set, *dirout;
512 int err;
513
514 port = &gpio->ports[offs];
515 port->gpio = gpio;
516 port->idx = pp->idx;
517
518 #ifdef CONFIG_PM_SLEEP
519 port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL);
520 if (!port->ctx)
521 return -ENOMEM;
522 #endif
523
524 dat = gpio->regs + GPIO_EXT_PORTA + pp->idx * GPIO_EXT_PORT_STRIDE;
525 set = gpio->regs + GPIO_SWPORTA_DR + pp->idx * GPIO_SWPORT_DR_STRIDE;
526 dirout = gpio->regs + GPIO_SWPORTA_DDR + pp->idx * GPIO_SWPORT_DDR_STRIDE;
527
528 config = (struct gpio_generic_chip_config) {
529 .dev = gpio->dev,
530 .sz = 4,
531 .dat = dat,
532 .set = set,
533 .dirout = dirout,
534 };
535
536 /* This registers 32 GPIO lines per port */
537 err = gpio_generic_chip_init(&port->chip, &config);
538 if (err) {
539 dev_err(gpio->dev, "failed to init gpio chip for port%d\n",
540 port->idx);
541 return err;
542 }
543
544 port->chip.gc.fwnode = pp->fwnode;
545 port->chip.gc.ngpio = pp->ngpio;
546 port->chip.gc.base = pp->gpio_base;
547 port->chip.gc.request = gpiochip_generic_request;
548 port->chip.gc.free = gpiochip_generic_free;
549
550 /* Only port A support debounce */
551 if (pp->idx == 0)
552 port->chip.gc.set_config = dwapb_gpio_set_config;
553 else
554 port->chip.gc.set_config = gpiochip_generic_config;
555
556 /* Only port A can provide interrupts in all configurations of the IP */
557 if (pp->idx == 0)
558 dwapb_configure_irqs(gpio, port, pp);
559
560 err = devm_gpiochip_add_data(gpio->dev, &port->chip.gc, port);
561 if (err) {
562 dev_err(gpio->dev, "failed to register gpiochip for port%d\n",
563 port->idx);
564 return err;
565 }
566
567 return 0;
568 }
569
dwapb_get_irq(struct device * dev,struct fwnode_handle * fwnode,struct dwapb_port_property * pp)570 static void dwapb_get_irq(struct device *dev, struct fwnode_handle *fwnode,
571 struct dwapb_port_property *pp)
572 {
573 int irq, j;
574
575 for (j = 0; j < pp->ngpio; j++) {
576 if (has_acpi_companion(dev))
577 irq = platform_get_irq_optional(to_platform_device(dev), j);
578 else
579 irq = fwnode_irq_get(fwnode, j);
580 if (irq > 0)
581 pp->irq[j] = irq;
582 }
583 }
584
dwapb_gpio_get_pdata(struct device * dev)585 static struct dwapb_platform_data *dwapb_gpio_get_pdata(struct device *dev)
586 {
587 struct dwapb_platform_data *pdata;
588 struct dwapb_port_property *pp;
589 int nports;
590 int i;
591
592 nports = device_get_child_node_count(dev);
593 if (nports == 0)
594 return ERR_PTR(-ENODEV);
595
596 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
597 if (!pdata)
598 return ERR_PTR(-ENOMEM);
599
600 pdata->properties = devm_kcalloc(dev, nports, sizeof(*pp), GFP_KERNEL);
601 if (!pdata->properties)
602 return ERR_PTR(-ENOMEM);
603
604 pdata->nports = nports;
605
606 i = 0;
607 device_for_each_child_node_scoped(dev, fwnode) {
608 pp = &pdata->properties[i++];
609 pp->fwnode = fwnode;
610
611 if (fwnode_property_read_u32(fwnode, "reg", &pp->idx) ||
612 pp->idx >= DWAPB_MAX_PORTS) {
613 dev_err(dev,
614 "missing/invalid port index for port%d\n", i);
615 return ERR_PTR(-EINVAL);
616 }
617
618 if (fwnode_property_read_u32(fwnode, "ngpios", &pp->ngpio) &&
619 fwnode_property_read_u32(fwnode, "snps,nr-gpios", &pp->ngpio)) {
620 dev_info(dev,
621 "failed to get number of gpios for port%d\n",
622 i);
623 pp->ngpio = DWAPB_MAX_GPIOS;
624 }
625
626 pp->gpio_base = -1;
627
628 /* For internal use only, new platforms mustn't exercise this */
629 if (is_software_node(fwnode))
630 fwnode_property_read_u32(fwnode, "gpio-base", &pp->gpio_base);
631
632 /*
633 * Only port A can provide interrupts in all configurations of
634 * the IP.
635 */
636 if (pp->idx == 0)
637 dwapb_get_irq(dev, fwnode, pp);
638 }
639
640 return pdata;
641 }
642
dwapb_assert_reset(void * data)643 static void dwapb_assert_reset(void *data)
644 {
645 struct dwapb_gpio *gpio = data;
646
647 reset_control_assert(gpio->rst);
648 }
649
dwapb_get_reset(struct dwapb_gpio * gpio)650 static int dwapb_get_reset(struct dwapb_gpio *gpio)
651 {
652 int err;
653
654 gpio->rst = devm_reset_control_get_optional_shared(gpio->dev, NULL);
655 if (IS_ERR(gpio->rst))
656 return dev_err_probe(gpio->dev, PTR_ERR(gpio->rst),
657 "Cannot get reset descriptor\n");
658
659 err = reset_control_deassert(gpio->rst);
660 if (err) {
661 dev_err(gpio->dev, "Cannot deassert reset lane\n");
662 return err;
663 }
664
665 return devm_add_action_or_reset(gpio->dev, dwapb_assert_reset, gpio);
666 }
667
dwapb_disable_clks(void * data)668 static void dwapb_disable_clks(void *data)
669 {
670 struct dwapb_gpio *gpio = data;
671
672 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
673 }
674
dwapb_get_clks(struct dwapb_gpio * gpio)675 static int dwapb_get_clks(struct dwapb_gpio *gpio)
676 {
677 int err;
678
679 /* Optional bus and debounce clocks */
680 gpio->clks[0].id = "bus";
681 gpio->clks[1].id = "db";
682 err = devm_clk_bulk_get_optional(gpio->dev, DWAPB_NR_CLOCKS,
683 gpio->clks);
684 if (err)
685 return dev_err_probe(gpio->dev, err,
686 "Cannot get APB/Debounce clocks\n");
687
688 err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);
689 if (err) {
690 dev_err(gpio->dev, "Cannot enable APB/Debounce clocks\n");
691 return err;
692 }
693
694 return devm_add_action_or_reset(gpio->dev, dwapb_disable_clks, gpio);
695 }
696
697 static const struct of_device_id dwapb_of_match[] = {
698 { .compatible = "snps,dw-apb-gpio", .data = (void *)GPIO_REG_OFFSET_V1},
699 { .compatible = "apm,xgene-gpio-v2", .data = (void *)GPIO_REG_OFFSET_V2},
700 { /* Sentinel */ }
701 };
702 MODULE_DEVICE_TABLE(of, dwapb_of_match);
703
704 static const struct acpi_device_id dwapb_acpi_match[] = {
705 {"HISI0181", GPIO_REG_OFFSET_V1},
706 {"APMC0D07", GPIO_REG_OFFSET_V1},
707 {"APMC0D81", GPIO_REG_OFFSET_V2},
708 {"FUJI200A", GPIO_REG_OFFSET_V1},
709 { }
710 };
711 MODULE_DEVICE_TABLE(acpi, dwapb_acpi_match);
712
dwapb_gpio_probe(struct platform_device * pdev)713 static int dwapb_gpio_probe(struct platform_device *pdev)
714 {
715 unsigned int i;
716 struct dwapb_gpio *gpio;
717 int err;
718 struct dwapb_platform_data *pdata;
719 struct device *dev = &pdev->dev;
720
721 pdata = dwapb_gpio_get_pdata(dev);
722 if (IS_ERR(pdata))
723 return PTR_ERR(pdata);
724
725 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
726 if (!gpio)
727 return -ENOMEM;
728
729 gpio->dev = &pdev->dev;
730 gpio->nr_ports = pdata->nports;
731
732 err = dwapb_get_reset(gpio);
733 if (err)
734 return err;
735
736 gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports,
737 sizeof(*gpio->ports), GFP_KERNEL);
738 if (!gpio->ports)
739 return -ENOMEM;
740
741 gpio->regs = devm_platform_ioremap_resource(pdev, 0);
742 if (IS_ERR(gpio->regs))
743 return PTR_ERR(gpio->regs);
744
745 err = dwapb_get_clks(gpio);
746 if (err)
747 return err;
748
749 gpio->flags = (uintptr_t)device_get_match_data(dev);
750
751 for (i = 0; i < gpio->nr_ports; i++) {
752 err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i);
753 if (err)
754 return err;
755 }
756
757 platform_set_drvdata(pdev, gpio);
758
759 return 0;
760 }
761
762 #ifdef CONFIG_PM_SLEEP
dwapb_gpio_suspend(struct device * dev)763 static int dwapb_gpio_suspend(struct device *dev)
764 {
765 struct dwapb_gpio *gpio = dev_get_drvdata(dev);
766 struct gpio_generic_chip *gen_gc = &gpio->ports[0].chip;
767 int i;
768
769 scoped_guard(gpio_generic_lock_irqsave, gen_gc) {
770 for (i = 0; i < gpio->nr_ports; i++) {
771 unsigned int offset;
772 unsigned int idx = gpio->ports[i].idx;
773 struct dwapb_context *ctx = gpio->ports[i].ctx;
774
775 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
776 ctx->dir = dwapb_read(gpio, offset);
777
778 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
779 ctx->data = dwapb_read(gpio, offset);
780
781 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
782 ctx->ext = dwapb_read(gpio, offset);
783
784 /* Only port A can provide interrupts */
785 if (idx == 0) {
786 ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK);
787 ctx->int_en = dwapb_read(gpio, GPIO_INTEN);
788 ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY);
789 ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
790 ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
791
792 /* Mask out interrupts */
793 dwapb_write(gpio, GPIO_INTMASK, ~ctx->wake_en);
794 }
795 }
796 }
797
798 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
799
800 return 0;
801 }
802
dwapb_gpio_resume(struct device * dev)803 static int dwapb_gpio_resume(struct device *dev)
804 {
805 struct dwapb_gpio *gpio = dev_get_drvdata(dev);
806 struct gpio_chip *gc = &gpio->ports[0].chip.gc;
807 struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc);
808 int i, err;
809
810 err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);
811 if (err) {
812 dev_err(gpio->dev, "Cannot reenable APB/Debounce clocks\n");
813 return err;
814 }
815
816 guard(gpio_generic_lock_irqsave)(gen_gc);
817
818 for (i = 0; i < gpio->nr_ports; i++) {
819 unsigned int offset;
820 unsigned int idx = gpio->ports[i].idx;
821 struct dwapb_context *ctx = gpio->ports[i].ctx;
822
823 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
824 dwapb_write(gpio, offset, ctx->data);
825
826 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
827 dwapb_write(gpio, offset, ctx->dir);
828
829 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
830 dwapb_write(gpio, offset, ctx->ext);
831
832 /* Only port A can provide interrupts */
833 if (idx == 0) {
834 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type);
835 dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol);
836 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb);
837 dwapb_write(gpio, GPIO_INTEN, ctx->int_en);
838 dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask);
839
840 /* Clear out spurious interrupts */
841 dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);
842 }
843 }
844
845 return 0;
846 }
847 #endif
848
849 static SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops, dwapb_gpio_suspend,
850 dwapb_gpio_resume);
851
852 static struct platform_driver dwapb_gpio_driver = {
853 .driver = {
854 .name = DWAPB_DRIVER_NAME,
855 .pm = &dwapb_gpio_pm_ops,
856 .of_match_table = dwapb_of_match,
857 .acpi_match_table = dwapb_acpi_match,
858 },
859 .probe = dwapb_gpio_probe,
860 };
861
862 module_platform_driver(dwapb_gpio_driver);
863
864 MODULE_LICENSE("GPL");
865 MODULE_AUTHOR("Jamie Iles");
866 MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver");
867 MODULE_ALIAS("platform:" DWAPB_DRIVER_NAME);
868