1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Xilinx ZynqMP SHA Driver.
4 * Copyright (c) 2022 Xilinx Inc.
5 */
6 #include <crypto/internal/hash.h>
7 #include <crypto/sha3.h>
8 #include <linux/cacheflush.h>
9 #include <linux/cleanup.h>
10 #include <linux/device.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/err.h>
13 #include <linux/firmware/xlnx-zynqmp.h>
14 #include <linux/io.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/platform_device.h>
19
20 #define ZYNQMP_DMA_BIT_MASK 32U
21 #define ZYNQMP_DMA_ALLOC_FIXED_SIZE 0x1000U
22
23 enum zynqmp_sha_op {
24 ZYNQMP_SHA3_INIT = 1,
25 ZYNQMP_SHA3_UPDATE = 2,
26 ZYNQMP_SHA3_FINAL = 4,
27 };
28
29 struct zynqmp_sha_drv_ctx {
30 struct shash_alg sha3_384;
31 struct device *dev;
32 };
33
34 struct zynqmp_sha_tfm_ctx {
35 struct device *dev;
36 struct crypto_shash *fbk_tfm;
37 };
38
39 static dma_addr_t update_dma_addr, final_dma_addr;
40 static char *ubuf, *fbuf;
41
42 static DEFINE_SPINLOCK(zynqmp_sha_lock);
43
zynqmp_sha_init_tfm(struct crypto_shash * hash)44 static int zynqmp_sha_init_tfm(struct crypto_shash *hash)
45 {
46 const char *fallback_driver_name = crypto_shash_alg_name(hash);
47 struct zynqmp_sha_tfm_ctx *tfm_ctx = crypto_shash_ctx(hash);
48 struct shash_alg *alg = crypto_shash_alg(hash);
49 struct crypto_shash *fallback_tfm;
50 struct zynqmp_sha_drv_ctx *drv_ctx;
51
52 drv_ctx = container_of(alg, struct zynqmp_sha_drv_ctx, sha3_384);
53 tfm_ctx->dev = drv_ctx->dev;
54
55 /* Allocate a fallback and abort if it failed. */
56 fallback_tfm = crypto_alloc_shash(fallback_driver_name, 0,
57 CRYPTO_ALG_NEED_FALLBACK);
58 if (IS_ERR(fallback_tfm))
59 return PTR_ERR(fallback_tfm);
60
61 if (crypto_shash_descsize(hash) <
62 crypto_shash_statesize(tfm_ctx->fbk_tfm)) {
63 crypto_free_shash(fallback_tfm);
64 return -EINVAL;
65 }
66
67 tfm_ctx->fbk_tfm = fallback_tfm;
68
69 return 0;
70 }
71
zynqmp_sha_exit_tfm(struct crypto_shash * hash)72 static void zynqmp_sha_exit_tfm(struct crypto_shash *hash)
73 {
74 struct zynqmp_sha_tfm_ctx *tfm_ctx = crypto_shash_ctx(hash);
75
76 crypto_free_shash(tfm_ctx->fbk_tfm);
77 }
78
zynqmp_sha_continue(struct shash_desc * desc,struct shash_desc * fbdesc,int err)79 static int zynqmp_sha_continue(struct shash_desc *desc,
80 struct shash_desc *fbdesc, int err)
81 {
82 err = err ?: crypto_shash_export(fbdesc, shash_desc_ctx(desc));
83 shash_desc_zero(fbdesc);
84 return err;
85 }
86
zynqmp_sha_init(struct shash_desc * desc)87 static int zynqmp_sha_init(struct shash_desc *desc)
88 {
89 struct zynqmp_sha_tfm_ctx *tctx = crypto_shash_ctx(desc->tfm);
90 struct crypto_shash *fbtfm = tctx->fbk_tfm;
91 SHASH_DESC_ON_STACK(fbdesc, fbtfm);
92 int err;
93
94 fbdesc->tfm = fbtfm;
95 err = crypto_shash_init(fbdesc);
96 return zynqmp_sha_continue(desc, fbdesc, err);
97 }
98
zynqmp_sha_update(struct shash_desc * desc,const u8 * data,unsigned int length)99 static int zynqmp_sha_update(struct shash_desc *desc, const u8 *data, unsigned int length)
100 {
101 struct zynqmp_sha_tfm_ctx *tctx = crypto_shash_ctx(desc->tfm);
102 struct crypto_shash *fbtfm = tctx->fbk_tfm;
103 SHASH_DESC_ON_STACK(fbdesc, fbtfm);
104 int err;
105
106 fbdesc->tfm = fbtfm;
107 err = crypto_shash_import(fbdesc, shash_desc_ctx(desc)) ?:
108 crypto_shash_update(fbdesc, data, length);
109 return zynqmp_sha_continue(desc, fbdesc, err);
110 }
111
zynqmp_sha_finup(struct shash_desc * desc,const u8 * data,unsigned int length,u8 * out)112 static int zynqmp_sha_finup(struct shash_desc *desc, const u8 *data, unsigned int length, u8 *out)
113 {
114 struct zynqmp_sha_tfm_ctx *tctx = crypto_shash_ctx(desc->tfm);
115 struct crypto_shash *fbtfm = tctx->fbk_tfm;
116 SHASH_DESC_ON_STACK(fbdesc, fbtfm);
117
118 fbdesc->tfm = fbtfm;
119 return crypto_shash_import(fbdesc, shash_desc_ctx(desc)) ?:
120 crypto_shash_finup(fbdesc, data, length, out);
121 }
122
__zynqmp_sha_digest(struct shash_desc * desc,const u8 * data,unsigned int len,u8 * out)123 static int __zynqmp_sha_digest(struct shash_desc *desc, const u8 *data,
124 unsigned int len, u8 *out)
125 {
126 unsigned int remaining_len = len;
127 int update_size;
128 int ret;
129
130 ret = zynqmp_pm_sha_hash(0, 0, ZYNQMP_SHA3_INIT);
131 if (ret)
132 return ret;
133
134 while (remaining_len != 0) {
135 memzero_explicit(ubuf, ZYNQMP_DMA_ALLOC_FIXED_SIZE);
136 if (remaining_len >= ZYNQMP_DMA_ALLOC_FIXED_SIZE) {
137 update_size = ZYNQMP_DMA_ALLOC_FIXED_SIZE;
138 remaining_len -= ZYNQMP_DMA_ALLOC_FIXED_SIZE;
139 } else {
140 update_size = remaining_len;
141 remaining_len = 0;
142 }
143 memcpy(ubuf, data, update_size);
144 flush_icache_range((unsigned long)ubuf, (unsigned long)ubuf + update_size);
145 ret = zynqmp_pm_sha_hash(update_dma_addr, update_size, ZYNQMP_SHA3_UPDATE);
146 if (ret)
147 return ret;
148
149 data += update_size;
150 }
151
152 ret = zynqmp_pm_sha_hash(final_dma_addr, SHA3_384_DIGEST_SIZE, ZYNQMP_SHA3_FINAL);
153 memcpy(out, fbuf, SHA3_384_DIGEST_SIZE);
154 memzero_explicit(fbuf, SHA3_384_DIGEST_SIZE);
155
156 return ret;
157 }
158
zynqmp_sha_digest(struct shash_desc * desc,const u8 * data,unsigned int len,u8 * out)159 static int zynqmp_sha_digest(struct shash_desc *desc, const u8 *data, unsigned int len, u8 *out)
160 {
161 scoped_guard(spinlock_bh, &zynqmp_sha_lock)
162 return __zynqmp_sha_digest(desc, data, len, out);
163 }
164
165 static struct zynqmp_sha_drv_ctx sha3_drv_ctx = {
166 .sha3_384 = {
167 .init = zynqmp_sha_init,
168 .update = zynqmp_sha_update,
169 .finup = zynqmp_sha_finup,
170 .digest = zynqmp_sha_digest,
171 .init_tfm = zynqmp_sha_init_tfm,
172 .exit_tfm = zynqmp_sha_exit_tfm,
173 .descsize = SHA3_384_EXPORT_SIZE,
174 .digestsize = SHA3_384_DIGEST_SIZE,
175 .base = {
176 .cra_name = "sha3-384",
177 .cra_driver_name = "zynqmp-sha3-384",
178 .cra_priority = 300,
179 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
180 CRYPTO_ALG_NEED_FALLBACK,
181 .cra_blocksize = SHA3_384_BLOCK_SIZE,
182 .cra_ctxsize = sizeof(struct zynqmp_sha_tfm_ctx),
183 .cra_module = THIS_MODULE,
184 }
185 }
186 };
187
zynqmp_sha_probe(struct platform_device * pdev)188 static int zynqmp_sha_probe(struct platform_device *pdev)
189 {
190 struct device *dev = &pdev->dev;
191 int err;
192 u32 v;
193
194 /* Verify the hardware is present */
195 err = zynqmp_pm_get_api_version(&v);
196 if (err)
197 return err;
198
199
200 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(ZYNQMP_DMA_BIT_MASK));
201 if (err < 0) {
202 dev_err(dev, "No usable DMA configuration\n");
203 return err;
204 }
205
206 err = crypto_register_shash(&sha3_drv_ctx.sha3_384);
207 if (err < 0) {
208 dev_err(dev, "Failed to register shash alg.\n");
209 return err;
210 }
211
212 sha3_drv_ctx.dev = dev;
213 platform_set_drvdata(pdev, &sha3_drv_ctx);
214
215 ubuf = dma_alloc_coherent(dev, ZYNQMP_DMA_ALLOC_FIXED_SIZE, &update_dma_addr, GFP_KERNEL);
216 if (!ubuf) {
217 err = -ENOMEM;
218 goto err_shash;
219 }
220
221 fbuf = dma_alloc_coherent(dev, SHA3_384_DIGEST_SIZE, &final_dma_addr, GFP_KERNEL);
222 if (!fbuf) {
223 err = -ENOMEM;
224 goto err_mem;
225 }
226
227 return 0;
228
229 err_mem:
230 dma_free_coherent(sha3_drv_ctx.dev, ZYNQMP_DMA_ALLOC_FIXED_SIZE, ubuf, update_dma_addr);
231
232 err_shash:
233 crypto_unregister_shash(&sha3_drv_ctx.sha3_384);
234
235 return err;
236 }
237
zynqmp_sha_remove(struct platform_device * pdev)238 static void zynqmp_sha_remove(struct platform_device *pdev)
239 {
240 sha3_drv_ctx.dev = platform_get_drvdata(pdev);
241
242 dma_free_coherent(sha3_drv_ctx.dev, ZYNQMP_DMA_ALLOC_FIXED_SIZE, ubuf, update_dma_addr);
243 dma_free_coherent(sha3_drv_ctx.dev, SHA3_384_DIGEST_SIZE, fbuf, final_dma_addr);
244 crypto_unregister_shash(&sha3_drv_ctx.sha3_384);
245 }
246
247 static struct platform_driver zynqmp_sha_driver = {
248 .probe = zynqmp_sha_probe,
249 .remove = zynqmp_sha_remove,
250 .driver = {
251 .name = "zynqmp-sha3-384",
252 },
253 };
254
255 module_platform_driver(zynqmp_sha_driver);
256 MODULE_DESCRIPTION("ZynqMP SHA3 hardware acceleration support.");
257 MODULE_LICENSE("GPL v2");
258 MODULE_AUTHOR("Harsha <harsha.harsha@xilinx.com>");
259