1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
4 */
5
6 /*
7 * In Certain QCOM SoCs like apq8096 and msm8996 that have KRYO processors,
8 * the CPU frequency subset and voltage value of each OPP varies
9 * based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables
10 * defines the voltage and frequency value based on the msm-id in SMEM
11 * and speedbin blown in the efuse combination.
12 * The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC
13 * to provide the OPP framework with required information.
14 * This is used to determine the voltage and frequency value for each OPP of
15 * operating-points-v2 table when it is parsed by the OPP framework.
16 */
17
18 #include <linux/cpu.h>
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/nvmem-consumer.h>
24 #include <linux/of.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm.h>
27 #include <linux/pm_domain.h>
28 #include <linux/pm_opp.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/slab.h>
31 #include <linux/soc/qcom/smem.h>
32
33 #include <dt-bindings/arm/qcom,ids.h>
34
35 enum ipq806x_versions {
36 IPQ8062_VERSION = 0,
37 IPQ8064_VERSION,
38 IPQ8065_VERSION,
39 };
40
41 #define IPQ6000_VERSION BIT(2)
42
43 enum ipq8074_versions {
44 IPQ8074_HAWKEYE_VERSION = 0,
45 IPQ8074_ACORN_VERSION,
46 };
47
48 struct qcom_cpufreq_drv;
49
50 struct qcom_cpufreq_match_data {
51 int (*get_version)(struct device *cpu_dev,
52 struct nvmem_cell *speedbin_nvmem,
53 char **pvs_name,
54 struct qcom_cpufreq_drv *drv);
55 const char **pd_names;
56 unsigned int num_pd_names;
57 };
58
59 struct qcom_cpufreq_drv_cpu {
60 int opp_token;
61 struct dev_pm_domain_list *pd_list;
62 };
63
64 struct qcom_cpufreq_drv {
65 u32 versions;
66 const struct qcom_cpufreq_match_data *data;
67 struct qcom_cpufreq_drv_cpu cpus[];
68 };
69
70 static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev;
71
qcom_cpufreq_simple_get_version(struct device * cpu_dev,struct nvmem_cell * speedbin_nvmem,char ** pvs_name,struct qcom_cpufreq_drv * drv)72 static int qcom_cpufreq_simple_get_version(struct device *cpu_dev,
73 struct nvmem_cell *speedbin_nvmem,
74 char **pvs_name,
75 struct qcom_cpufreq_drv *drv)
76 {
77 u8 *speedbin;
78
79 *pvs_name = NULL;
80 speedbin = nvmem_cell_read(speedbin_nvmem, NULL);
81 if (IS_ERR(speedbin))
82 return PTR_ERR(speedbin);
83
84 dev_dbg(cpu_dev, "speedbin: %d\n", *speedbin);
85 drv->versions = 1 << *speedbin;
86 kfree(speedbin);
87 return 0;
88 }
89
get_krait_bin_format_a(struct device * cpu_dev,int * speed,int * pvs,u8 * buf)90 static void get_krait_bin_format_a(struct device *cpu_dev,
91 int *speed, int *pvs,
92 u8 *buf)
93 {
94 u32 pte_efuse;
95
96 pte_efuse = *((u32 *)buf);
97
98 *speed = pte_efuse & 0xf;
99 if (*speed == 0xf)
100 *speed = (pte_efuse >> 4) & 0xf;
101
102 if (*speed == 0xf) {
103 *speed = 0;
104 dev_warn(cpu_dev, "Speed bin: Defaulting to %d\n", *speed);
105 } else {
106 dev_dbg(cpu_dev, "Speed bin: %d\n", *speed);
107 }
108
109 *pvs = (pte_efuse >> 10) & 0x7;
110 if (*pvs == 0x7)
111 *pvs = (pte_efuse >> 13) & 0x7;
112
113 if (*pvs == 0x7) {
114 *pvs = 0;
115 dev_warn(cpu_dev, "PVS bin: Defaulting to %d\n", *pvs);
116 } else {
117 dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs);
118 }
119 }
120
get_krait_bin_format_b(struct device * cpu_dev,int * speed,int * pvs,int * pvs_ver,u8 * buf)121 static void get_krait_bin_format_b(struct device *cpu_dev,
122 int *speed, int *pvs, int *pvs_ver,
123 u8 *buf)
124 {
125 u32 pte_efuse, redundant_sel;
126
127 pte_efuse = *((u32 *)buf);
128 redundant_sel = (pte_efuse >> 24) & 0x7;
129
130 *pvs_ver = (pte_efuse >> 4) & 0x3;
131
132 switch (redundant_sel) {
133 case 1:
134 *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
135 *speed = (pte_efuse >> 27) & 0xf;
136 break;
137 case 2:
138 *pvs = (pte_efuse >> 27) & 0xf;
139 *speed = pte_efuse & 0x7;
140 break;
141 default:
142 /* 4 bits of PVS are in efuse register bits 31, 8-6. */
143 *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
144 *speed = pte_efuse & 0x7;
145 }
146
147 /* Check SPEED_BIN_BLOW_STATUS */
148 if (pte_efuse & BIT(3)) {
149 dev_dbg(cpu_dev, "Speed bin: %d\n", *speed);
150 } else {
151 dev_warn(cpu_dev, "Speed bin not set. Defaulting to 0!\n");
152 *speed = 0;
153 }
154
155 /* Check PVS_BLOW_STATUS */
156 pte_efuse = *(((u32 *)buf) + 1);
157 pte_efuse &= BIT(21);
158 if (pte_efuse) {
159 dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs);
160 } else {
161 dev_warn(cpu_dev, "PVS bin not set. Defaulting to 0!\n");
162 *pvs = 0;
163 }
164
165 dev_dbg(cpu_dev, "PVS version: %d\n", *pvs_ver);
166 }
167
qcom_cpufreq_kryo_name_version(struct device * cpu_dev,struct nvmem_cell * speedbin_nvmem,char ** pvs_name,struct qcom_cpufreq_drv * drv)168 static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
169 struct nvmem_cell *speedbin_nvmem,
170 char **pvs_name,
171 struct qcom_cpufreq_drv *drv)
172 {
173 size_t len;
174 u32 msm_id;
175 u8 *speedbin;
176 int ret;
177 *pvs_name = NULL;
178
179 ret = qcom_smem_get_soc_id(&msm_id);
180 if (ret)
181 return ret;
182
183 speedbin = nvmem_cell_read(speedbin_nvmem, &len);
184 if (IS_ERR(speedbin))
185 return PTR_ERR(speedbin);
186
187 switch (msm_id) {
188 case QCOM_ID_MSM8996:
189 case QCOM_ID_APQ8096:
190 case QCOM_ID_IPQ5332:
191 case QCOM_ID_IPQ5322:
192 case QCOM_ID_IPQ5312:
193 case QCOM_ID_IPQ5302:
194 case QCOM_ID_IPQ5300:
195 case QCOM_ID_IPQ5321:
196 case QCOM_ID_IPQ9514:
197 case QCOM_ID_IPQ9550:
198 case QCOM_ID_IPQ9554:
199 case QCOM_ID_IPQ9570:
200 case QCOM_ID_IPQ9574:
201 drv->versions = 1 << (unsigned int)(*speedbin);
202 break;
203 case QCOM_ID_IPQ5424:
204 case QCOM_ID_IPQ5404:
205 drv->versions = (*speedbin == 0x3b) ? BIT(1) : BIT(0);
206 break;
207 case QCOM_ID_MSM8996SG:
208 case QCOM_ID_APQ8096SG:
209 drv->versions = 1 << ((unsigned int)(*speedbin) + 4);
210 break;
211 default:
212 BUG();
213 break;
214 }
215
216 kfree(speedbin);
217 return 0;
218 }
219
qcom_cpufreq_krait_name_version(struct device * cpu_dev,struct nvmem_cell * speedbin_nvmem,char ** pvs_name,struct qcom_cpufreq_drv * drv)220 static int qcom_cpufreq_krait_name_version(struct device *cpu_dev,
221 struct nvmem_cell *speedbin_nvmem,
222 char **pvs_name,
223 struct qcom_cpufreq_drv *drv)
224 {
225 int speed = 0, pvs = 0, pvs_ver = 0;
226 u8 *speedbin;
227 size_t len;
228 int ret = 0;
229
230 speedbin = nvmem_cell_read(speedbin_nvmem, &len);
231
232 if (IS_ERR(speedbin))
233 return PTR_ERR(speedbin);
234
235 switch (len) {
236 case 4:
237 get_krait_bin_format_a(cpu_dev, &speed, &pvs, speedbin);
238 break;
239 case 8:
240 get_krait_bin_format_b(cpu_dev, &speed, &pvs, &pvs_ver,
241 speedbin);
242 break;
243 default:
244 dev_err(cpu_dev, "Unable to read nvmem data. Defaulting to 0!\n");
245 ret = -ENODEV;
246 goto len_error;
247 }
248
249 snprintf(*pvs_name, sizeof("speedXX-pvsXX-vXX"), "speed%d-pvs%d-v%d",
250 speed, pvs, pvs_ver);
251
252 drv->versions = (1 << speed);
253
254 len_error:
255 kfree(speedbin);
256 return ret;
257 }
258
qcom_cpufreq_ipq8064_name_version(struct device * cpu_dev,struct nvmem_cell * speedbin_nvmem,char ** pvs_name,struct qcom_cpufreq_drv * drv)259 static int qcom_cpufreq_ipq8064_name_version(struct device *cpu_dev,
260 struct nvmem_cell *speedbin_nvmem,
261 char **pvs_name,
262 struct qcom_cpufreq_drv *drv)
263 {
264 int speed = 0, pvs = 0;
265 int msm_id, ret = 0;
266 u8 *speedbin;
267 size_t len;
268
269 speedbin = nvmem_cell_read(speedbin_nvmem, &len);
270 if (IS_ERR(speedbin))
271 return PTR_ERR(speedbin);
272
273 if (len != 4) {
274 dev_err(cpu_dev, "Unable to read nvmem data. Defaulting to 0!\n");
275 ret = -ENODEV;
276 goto exit;
277 }
278
279 get_krait_bin_format_a(cpu_dev, &speed, &pvs, speedbin);
280
281 ret = qcom_smem_get_soc_id(&msm_id);
282 if (ret)
283 goto exit;
284
285 switch (msm_id) {
286 case QCOM_ID_IPQ8062:
287 drv->versions = BIT(IPQ8062_VERSION);
288 break;
289 case QCOM_ID_IPQ8064:
290 case QCOM_ID_IPQ8066:
291 case QCOM_ID_IPQ8068:
292 drv->versions = BIT(IPQ8064_VERSION);
293 break;
294 case QCOM_ID_IPQ8065:
295 case QCOM_ID_IPQ8069:
296 drv->versions = BIT(IPQ8065_VERSION);
297 break;
298 default:
299 dev_err(cpu_dev,
300 "SoC ID %u is not part of IPQ8064 family, limiting to 1.0GHz!\n",
301 msm_id);
302 drv->versions = BIT(IPQ8062_VERSION);
303 break;
304 }
305
306 /* IPQ8064 speed is never fused. Only pvs values are fused. */
307 snprintf(*pvs_name, sizeof("speed0-pvsXX"), "speed0-pvs%d", pvs);
308
309 exit:
310 kfree(speedbin);
311 return ret;
312 }
313
qcom_cpufreq_ipq6018_name_version(struct device * cpu_dev,struct nvmem_cell * speedbin_nvmem,char ** pvs_name,struct qcom_cpufreq_drv * drv)314 static int qcom_cpufreq_ipq6018_name_version(struct device *cpu_dev,
315 struct nvmem_cell *speedbin_nvmem,
316 char **pvs_name,
317 struct qcom_cpufreq_drv *drv)
318 {
319 u32 msm_id;
320 int ret;
321 u8 *speedbin;
322 *pvs_name = NULL;
323
324 ret = qcom_smem_get_soc_id(&msm_id);
325 if (ret)
326 return ret;
327
328 speedbin = nvmem_cell_read(speedbin_nvmem, NULL);
329 if (IS_ERR(speedbin))
330 return PTR_ERR(speedbin);
331
332 switch (msm_id) {
333 case QCOM_ID_IPQ6005:
334 case QCOM_ID_IPQ6010:
335 case QCOM_ID_IPQ6018:
336 case QCOM_ID_IPQ6028:
337 /* Fuse Value Freq BIT to set
338 * ---------------------------------
339 * 2’b0 No Limit BIT(0)
340 * 2’b1 1.5 GHz BIT(1)
341 */
342 drv->versions = 1 << (unsigned int)(*speedbin);
343 break;
344 case QCOM_ID_IPQ6000:
345 /*
346 * IPQ6018 family only has one bit to advertise the CPU
347 * speed-bin, but that is not enough for IPQ6000 which
348 * is only rated up to 1.2GHz.
349 * So for IPQ6000 manually set BIT(2) based on SMEM ID.
350 */
351 drv->versions = IPQ6000_VERSION;
352 break;
353 default:
354 dev_err(cpu_dev,
355 "SoC ID %u is not part of IPQ6018 family, limiting to 1.2GHz!\n",
356 msm_id);
357 drv->versions = IPQ6000_VERSION;
358 break;
359 }
360
361 kfree(speedbin);
362 return 0;
363 }
364
qcom_cpufreq_ipq8074_name_version(struct device * cpu_dev,struct nvmem_cell * speedbin_nvmem,char ** pvs_name,struct qcom_cpufreq_drv * drv)365 static int qcom_cpufreq_ipq8074_name_version(struct device *cpu_dev,
366 struct nvmem_cell *speedbin_nvmem,
367 char **pvs_name,
368 struct qcom_cpufreq_drv *drv)
369 {
370 u32 msm_id;
371 int ret;
372 *pvs_name = NULL;
373
374 ret = qcom_smem_get_soc_id(&msm_id);
375 if (ret)
376 return ret;
377
378 switch (msm_id) {
379 case QCOM_ID_IPQ8070A:
380 case QCOM_ID_IPQ8071A:
381 case QCOM_ID_IPQ8172:
382 case QCOM_ID_IPQ8173:
383 case QCOM_ID_IPQ8174:
384 drv->versions = BIT(IPQ8074_ACORN_VERSION);
385 break;
386 case QCOM_ID_IPQ8072A:
387 case QCOM_ID_IPQ8074A:
388 case QCOM_ID_IPQ8076A:
389 case QCOM_ID_IPQ8078A:
390 drv->versions = BIT(IPQ8074_HAWKEYE_VERSION);
391 break;
392 default:
393 dev_err(cpu_dev,
394 "SoC ID %u is not part of IPQ8074 family, limiting to 1.4GHz!\n",
395 msm_id);
396 drv->versions = BIT(IPQ8074_ACORN_VERSION);
397 break;
398 }
399
400 return 0;
401 }
402
403 static const struct qcom_cpufreq_match_data match_data_kryo = {
404 .get_version = qcom_cpufreq_kryo_name_version,
405 };
406
407 static const struct qcom_cpufreq_match_data match_data_krait = {
408 .get_version = qcom_cpufreq_krait_name_version,
409 };
410
411 static const struct qcom_cpufreq_match_data match_data_msm8909 = {
412 .get_version = qcom_cpufreq_simple_get_version,
413 .pd_names = (const char *[]) { "perf" },
414 .num_pd_names = 1,
415 };
416
417 static const struct qcom_cpufreq_match_data match_data_qcs404 = {
418 .pd_names = (const char *[]) { "cpr" },
419 .num_pd_names = 1,
420 };
421
422 static const struct qcom_cpufreq_match_data match_data_ipq6018 = {
423 .get_version = qcom_cpufreq_ipq6018_name_version,
424 };
425
426 static const struct qcom_cpufreq_match_data match_data_ipq8064 = {
427 .get_version = qcom_cpufreq_ipq8064_name_version,
428 };
429
430 static const struct qcom_cpufreq_match_data match_data_ipq8074 = {
431 .get_version = qcom_cpufreq_ipq8074_name_version,
432 };
433
qcom_cpufreq_suspend_pd_devs(struct qcom_cpufreq_drv * drv,unsigned int cpu)434 static void qcom_cpufreq_suspend_pd_devs(struct qcom_cpufreq_drv *drv, unsigned int cpu)
435 {
436 struct dev_pm_domain_list *pd_list = drv->cpus[cpu].pd_list;
437 int i;
438
439 if (!pd_list)
440 return;
441
442 for (i = 0; i < pd_list->num_pds; i++)
443 device_set_awake_path(pd_list->pd_devs[i]);
444 }
445
qcom_cpufreq_probe(struct platform_device * pdev)446 static int qcom_cpufreq_probe(struct platform_device *pdev)
447 {
448 struct qcom_cpufreq_drv *drv;
449 struct nvmem_cell *speedbin_nvmem;
450 struct device *cpu_dev;
451 char pvs_name_buffer[] = "speedXX-pvsXX-vXX";
452 char *pvs_name = pvs_name_buffer;
453 unsigned cpu;
454 const struct of_device_id *match;
455 int ret;
456
457 cpu_dev = get_cpu_device(0);
458 if (!cpu_dev)
459 return -ENODEV;
460
461 struct device_node *np __free(device_node) =
462 dev_pm_opp_of_get_opp_desc_node(cpu_dev);
463 if (!np)
464 return -ENOENT;
465
466 ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu") ||
467 of_device_is_compatible(np, "operating-points-v2-krait-cpu");
468 if (!ret)
469 return -ENOENT;
470
471 drv = devm_kzalloc(&pdev->dev, struct_size(drv, cpus, num_possible_cpus()),
472 GFP_KERNEL);
473 if (!drv)
474 return -ENOMEM;
475
476 match = pdev->dev.platform_data;
477 drv->data = match->data;
478 if (!drv->data)
479 return -ENODEV;
480
481 if (drv->data->get_version) {
482 speedbin_nvmem = of_nvmem_cell_get(np, NULL);
483 if (IS_ERR(speedbin_nvmem))
484 return dev_err_probe(cpu_dev, PTR_ERR(speedbin_nvmem),
485 "Could not get nvmem cell\n");
486
487 ret = drv->data->get_version(cpu_dev,
488 speedbin_nvmem, &pvs_name, drv);
489 if (ret) {
490 nvmem_cell_put(speedbin_nvmem);
491 return ret;
492 }
493 nvmem_cell_put(speedbin_nvmem);
494 }
495
496 for_each_present_cpu(cpu) {
497 struct dev_pm_opp_config config = {
498 .supported_hw = NULL,
499 };
500
501 cpu_dev = get_cpu_device(cpu);
502 if (NULL == cpu_dev) {
503 ret = -ENODEV;
504 goto free_opp;
505 }
506
507 if (drv->data->get_version) {
508 config.supported_hw = &drv->versions;
509 config.supported_hw_count = 1;
510
511 if (pvs_name)
512 config.prop_name = pvs_name;
513 }
514
515 if (config.supported_hw) {
516 drv->cpus[cpu].opp_token = dev_pm_opp_set_config(cpu_dev, &config);
517 if (drv->cpus[cpu].opp_token < 0) {
518 ret = drv->cpus[cpu].opp_token;
519 dev_err(cpu_dev, "Failed to set OPP config\n");
520 goto free_opp;
521 }
522 }
523
524 if (drv->data->pd_names) {
525 struct dev_pm_domain_attach_data attach_data = {
526 .pd_names = drv->data->pd_names,
527 .num_pd_names = drv->data->num_pd_names,
528 .pd_flags = PD_FLAG_DEV_LINK_ON |
529 PD_FLAG_REQUIRED_OPP,
530 };
531
532 ret = dev_pm_domain_attach_list(cpu_dev, &attach_data,
533 &drv->cpus[cpu].pd_list);
534 if (ret < 0)
535 goto free_opp;
536 }
537 }
538
539 cpufreq_dt_pdev = platform_device_register_simple("cpufreq-dt", -1,
540 NULL, 0);
541 if (!IS_ERR(cpufreq_dt_pdev)) {
542 platform_set_drvdata(pdev, drv);
543 return 0;
544 }
545
546 ret = PTR_ERR(cpufreq_dt_pdev);
547 dev_err(cpu_dev, "Failed to register platform device\n");
548
549 free_opp:
550 for_each_present_cpu(cpu) {
551 dev_pm_domain_detach_list(drv->cpus[cpu].pd_list);
552 dev_pm_opp_clear_config(drv->cpus[cpu].opp_token);
553 }
554 return ret;
555 }
556
qcom_cpufreq_remove(struct platform_device * pdev)557 static void qcom_cpufreq_remove(struct platform_device *pdev)
558 {
559 struct qcom_cpufreq_drv *drv = platform_get_drvdata(pdev);
560 unsigned int cpu;
561
562 platform_device_unregister(cpufreq_dt_pdev);
563
564 for_each_present_cpu(cpu) {
565 dev_pm_domain_detach_list(drv->cpus[cpu].pd_list);
566 dev_pm_opp_clear_config(drv->cpus[cpu].opp_token);
567 }
568 }
569
qcom_cpufreq_suspend(struct device * dev)570 static int qcom_cpufreq_suspend(struct device *dev)
571 {
572 struct qcom_cpufreq_drv *drv = dev_get_drvdata(dev);
573 unsigned int cpu;
574
575 for_each_present_cpu(cpu)
576 qcom_cpufreq_suspend_pd_devs(drv, cpu);
577
578 return 0;
579 }
580
581 static DEFINE_SIMPLE_DEV_PM_OPS(qcom_cpufreq_pm_ops, qcom_cpufreq_suspend, NULL);
582
583 static struct platform_driver qcom_cpufreq_driver = {
584 .probe = qcom_cpufreq_probe,
585 .remove = qcom_cpufreq_remove,
586 .driver = {
587 .name = "qcom-cpufreq-nvmem",
588 .pm = pm_sleep_ptr(&qcom_cpufreq_pm_ops),
589 },
590 };
591
592 static const struct of_device_id qcom_cpufreq_match_list[] __initconst __maybe_unused = {
593 { .compatible = "qcom,apq8096", .data = &match_data_kryo },
594 { .compatible = "qcom,msm8909", .data = &match_data_msm8909 },
595 { .compatible = "qcom,msm8996", .data = &match_data_kryo },
596 { .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
597 { .compatible = "qcom,ipq5332", .data = &match_data_kryo },
598 { .compatible = "qcom,ipq5424", .data = &match_data_kryo },
599 { .compatible = "qcom,ipq6018", .data = &match_data_ipq6018 },
600 { .compatible = "qcom,ipq8064", .data = &match_data_ipq8064 },
601 { .compatible = "qcom,ipq8074", .data = &match_data_ipq8074 },
602 { .compatible = "qcom,apq8064", .data = &match_data_krait },
603 { .compatible = "qcom,ipq9574", .data = &match_data_kryo },
604 { .compatible = "qcom,msm8974", .data = &match_data_krait },
605 { .compatible = "qcom,msm8960", .data = &match_data_krait },
606 {},
607 };
608 MODULE_DEVICE_TABLE(of, qcom_cpufreq_match_list);
609
610 /*
611 * Since the driver depends on smem and nvmem drivers, which may
612 * return EPROBE_DEFER, all the real activity is done in the probe,
613 * which may be defered as well. The init here is only registering
614 * the driver and the platform device.
615 */
qcom_cpufreq_init(void)616 static int __init qcom_cpufreq_init(void)
617 {
618 struct device_node *np __free(device_node) = of_find_node_by_path("/");
619 const struct of_device_id *match;
620 int ret;
621
622 if (!np)
623 return -ENODEV;
624
625 match = of_match_node(qcom_cpufreq_match_list, np);
626 if (!match)
627 return -ENODEV;
628
629 ret = platform_driver_register(&qcom_cpufreq_driver);
630 if (unlikely(ret < 0))
631 return ret;
632
633 cpufreq_pdev = platform_device_register_data(NULL, "qcom-cpufreq-nvmem",
634 -1, match, sizeof(*match));
635 ret = PTR_ERR_OR_ZERO(cpufreq_pdev);
636 if (0 == ret)
637 return 0;
638
639 platform_driver_unregister(&qcom_cpufreq_driver);
640 return ret;
641 }
642 module_init(qcom_cpufreq_init);
643
qcom_cpufreq_exit(void)644 static void __exit qcom_cpufreq_exit(void)
645 {
646 platform_device_unregister(cpufreq_pdev);
647 platform_driver_unregister(&qcom_cpufreq_driver);
648 }
649 module_exit(qcom_cpufreq_exit);
650
651 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. CPUfreq driver");
652 MODULE_LICENSE("GPL v2");
653