1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2003 Marcel Moolenaar
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include "opt_acpi.h"
30 #include "opt_platform.h"
31 #include "opt_uart.h"
32
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/bus.h>
36 #include <sys/conf.h>
37 #include <sys/kernel.h>
38 #include <sys/sysctl.h>
39 #include <machine/bus.h>
40
41 #ifdef FDT
42 #include <dev/fdt/fdt_common.h>
43 #include <dev/ofw/ofw_bus.h>
44 #include <dev/ofw/ofw_bus_subr.h>
45 #endif
46
47 #include <dev/uart/uart.h>
48 #include <dev/uart/uart_cpu.h>
49 #ifdef FDT
50 #include <dev/uart/uart_cpu_fdt.h>
51 #endif
52 #include <dev/uart/uart_bus.h>
53 #include <dev/uart/uart_dev_ns8250.h>
54 #include <dev/uart/uart_ppstypes.h>
55 #ifdef DEV_ACPI
56 #include <dev/uart/uart_cpu_acpi.h>
57 #include <contrib/dev/acpica/include/acpi.h>
58 #endif
59
60 #include <dev/ic/ns16550.h>
61
62 #include "uart_if.h"
63
64 #define DEFAULT_RCLK 1843200
65
66 /*
67 * Set the default baudrate tolerance to 3.0%.
68 *
69 * Some embedded boards have odd reference clocks (eg 25MHz)
70 * and we need to handle higher variances in the target baud rate.
71 */
72 #ifndef UART_DEV_TOLERANCE_PCT
73 #define UART_DEV_TOLERANCE_PCT 30
74 #endif /* UART_DEV_TOLERANCE_PCT */
75
76 static int broken_txfifo = 0;
77 SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RWTUN,
78 &broken_txfifo, 0, "UART FIFO has QEMU emulation bug");
79
80 static int uart_noise_threshold = 0;
81 SYSCTL_INT(_hw, OID_AUTO, uart_noise_threshold, CTLFLAG_RWTUN,
82 &uart_noise_threshold, 0,
83 "Number of UART RX interrupts where TX is not ready, before data is discarded");
84
85 /*
86 * To use early printf on x86, add the following to your kernel config:
87 *
88 * options UART_NS8250_EARLY_PORT=0x3f8
89 * options EARLY_PRINTF=ns8250
90 */
91 #if CHECK_EARLY_PRINTF(ns8250)
92 #if (defined(__amd64__) || defined(__i386__))
93 static void
uart_ns8250_early_putc(int c)94 uart_ns8250_early_putc(int c)
95 {
96 u_int stat = UART_NS8250_EARLY_PORT + REG_LSR;
97 u_int tx = UART_NS8250_EARLY_PORT + REG_DATA;
98 int limit = 10000; /* 10ms is plenty of time */
99
100 while ((inb(stat) & LSR_THRE) == 0 && --limit > 0)
101 continue;
102 outb(tx, c);
103 }
104 #elif (defined(__arm__) || defined(__aarch64__))
105 #ifndef UART_NS8250_EARLY_REG_IO_WIDTH
106 #error Option 'UART_NS8250_EARLY_REG_IO_WIDTH' is missing.
107 #endif
108 #ifndef UART_NS8250_EARLY_REG_SHIFT
109 #error Option 'UART_NS8250_EARLY_REG_SHIFT' is missing.
110 #endif
111
112 #if UART_NS8250_EARLY_REG_IO_WIDTH == 1
113 #define T uint8_t
114 #elif UART_NS8250_EARLY_REG_IO_WIDTH == 2
115 #define T uint16_t
116 #elif UART_NS8250_EARLY_REG_IO_WIDTH == 4
117 #define T uint32_t
118
119 #else
120 #error Invalid/unsupported UART_NS8250_EARLY_REG_IO_WIDTH value
121 #endif
122
123 #include <machine/machdep.h>
124
125 static void
uart_ns8250_early_putc(int c)126 uart_ns8250_early_putc(int c)
127 {
128 volatile T *stat;
129 volatile T *tx;
130
131 stat = (T *)(socdev_va + (REG_LSR << UART_NS8250_EARLY_REG_SHIFT));
132 tx = (T *)(socdev_va + (REG_DATA << UART_NS8250_EARLY_REG_SHIFT));
133
134 while ((*stat & LSR_THRE) == 0)
135 continue;
136 *tx = c & 0xff;
137 }
138 #else
139 #error ns8250 early putc is not implemented for current architecture
140 #endif
141 early_putc_t *early_putc = uart_ns8250_early_putc;
142 #undef DTYPE
143 #endif /* EARLY_PRINTF */
144
145 /*
146 * Clear pending interrupts. THRE is cleared by reading IIR. Data
147 * that may have been received gets lost here.
148 */
149 static void
ns8250_clrint(struct uart_bas * bas)150 ns8250_clrint(struct uart_bas *bas)
151 {
152 uint8_t iir, lsr;
153
154 iir = uart_getreg(bas, REG_IIR);
155 while ((iir & IIR_NOPEND) == 0) {
156 iir &= IIR_IMASK;
157 if (iir == IIR_RLS) {
158 lsr = uart_getreg(bas, REG_LSR);
159 if (lsr & (LSR_BI|LSR_FE|LSR_PE))
160 (void)uart_getreg(bas, REG_DATA);
161 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT)
162 (void)uart_getreg(bas, REG_DATA);
163 else if (iir == IIR_MLSC)
164 (void)uart_getreg(bas, REG_MSR);
165 uart_barrier(bas);
166 iir = uart_getreg(bas, REG_IIR);
167 }
168 }
169
170 static uint32_t
ns8250_get_divisor(struct uart_bas * bas)171 ns8250_get_divisor(struct uart_bas *bas)
172 {
173 uint32_t divisor;
174 uint8_t lcr;
175
176 lcr = uart_getreg(bas, REG_LCR);
177 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
178 uart_barrier(bas);
179 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8);
180 uart_barrier(bas);
181 uart_setreg(bas, REG_LCR, lcr);
182 uart_barrier(bas);
183
184 return (divisor);
185 }
186
187 static int
ns8250_delay(struct uart_bas * bas)188 ns8250_delay(struct uart_bas *bas)
189 {
190 int divisor;
191
192 divisor = ns8250_get_divisor(bas);
193
194 /* 1/10th the time to transmit 1 character (estimate). */
195 if (divisor <= 134)
196 return (16000000 * divisor / bas->rclk);
197 return (16000 * divisor / (bas->rclk / 1000));
198 }
199
200 static int
ns8250_divisor(int rclk,int baudrate)201 ns8250_divisor(int rclk, int baudrate)
202 {
203 int actual_baud, divisor;
204 int error;
205
206 if (baudrate == 0)
207 return (0);
208
209 divisor = (rclk / (baudrate << 3) + 1) >> 1;
210 if (divisor == 0 || divisor >= 65536)
211 return (0);
212 actual_baud = rclk / (divisor << 4);
213
214 /* 10 times error in percent: */
215 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) / 2;
216
217 /* enforce maximum error tolerance: */
218 if (error < -UART_DEV_TOLERANCE_PCT || error > UART_DEV_TOLERANCE_PCT)
219 return (0);
220
221 return (divisor);
222 }
223
224 static int
ns8250_drain(struct uart_bas * bas,int what)225 ns8250_drain(struct uart_bas *bas, int what)
226 {
227 int delay, limit;
228
229 delay = ns8250_delay(bas);
230
231 if (what & UART_DRAIN_TRANSMITTER) {
232 /*
233 * Pick an arbitrary high limit to avoid getting stuck in
234 * an infinite loop when the hardware is broken. Make the
235 * limit high enough to handle large FIFOs.
236 */
237 limit = 10*1024;
238 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
239 DELAY(delay);
240 if (limit == 0) {
241 /* printf("uart: ns8250: transmitter appears stuck... "); */
242 return (EIO);
243 }
244 }
245
246 if (what & UART_DRAIN_RECEIVER) {
247 /*
248 * Pick an arbitrary high limit to avoid getting stuck in
249 * an infinite loop when the hardware is broken. Make the
250 * limit high enough to handle large FIFOs and integrated
251 * UARTs. The HP rx2600 for example has 3 UARTs on the
252 * management board that tend to get a lot of data send
253 * to it when the UART is first activated. Assume that we
254 * have finished draining if LSR_RXRDY is not asserted both
255 * prior to and after a DELAY; but as long as LSR_RXRDY is
256 * asserted, read (and discard) characters as quickly as
257 * possible.
258 */
259 limit=10*4096;
260 while (limit && (uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) {
261 do {
262 (void)uart_getreg(bas, REG_DATA);
263 uart_barrier(bas);
264 } while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit);
265 uart_barrier(bas);
266 DELAY(delay << 2);
267 }
268 if (limit == 0) {
269 /* printf("uart: ns8250: receiver appears broken... "); */
270 return (EIO);
271 }
272 }
273
274 return (0);
275 }
276
277 /*
278 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be
279 * drained. WARNING: this function clobbers the FIFO setting!
280 */
281 static void
ns8250_flush(struct uart_bas * bas,int what)282 ns8250_flush(struct uart_bas *bas, int what)
283 {
284 uint8_t fcr;
285 uint8_t lsr;
286 int drain = 0;
287
288 fcr = FCR_ENABLE;
289 if (what & UART_FLUSH_TRANSMITTER)
290 fcr |= FCR_XMT_RST;
291 if (what & UART_FLUSH_RECEIVER)
292 fcr |= FCR_RCV_RST;
293 uart_setreg(bas, REG_FCR, fcr);
294 uart_barrier(bas);
295
296 /*
297 * Detect and work around emulated UARTs which don't implement the
298 * FCR register; on these systems we need to drain the FIFO since
299 * the flush we request doesn't happen. One such system is the
300 * Firecracker VMM, aka. the rust-vmm/vm-superio emulation code:
301 * https://github.com/rust-vmm/vm-superio/issues/83
302 */
303 lsr = uart_getreg(bas, REG_LSR);
304 if (((lsr & LSR_THRE) == 0) && (what & UART_FLUSH_TRANSMITTER))
305 drain |= UART_DRAIN_TRANSMITTER;
306 if ((lsr & LSR_RXRDY) && (what & UART_FLUSH_RECEIVER))
307 drain |= UART_DRAIN_RECEIVER;
308 if (drain != 0) {
309 printf("uart: ns8250: UART FCR is broken (%#x)\n", drain);
310 ns8250_drain(bas, drain);
311 }
312 }
313
314 static int
ns8250_param(struct uart_bas * bas,int baudrate,int databits,int stopbits,int parity)315 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
316 int parity)
317 {
318 int divisor;
319 uint8_t lcr;
320
321 /* Don't change settings when running on Hyper-V */
322 if (vm_guest == VM_GUEST_HV)
323 return (0);
324
325 lcr = 0;
326 if (databits >= 8)
327 lcr |= LCR_8BITS;
328 else if (databits == 7)
329 lcr |= LCR_7BITS;
330 else if (databits == 6)
331 lcr |= LCR_6BITS;
332 else
333 lcr |= LCR_5BITS;
334 if (stopbits > 1)
335 lcr |= LCR_STOPB;
336 lcr |= parity << 3;
337
338 /* Set baudrate if we know a rclk and both are not 0. */
339 if (baudrate > 0 && bas->rclk > 0) {
340 divisor = ns8250_divisor(bas->rclk, baudrate);
341 if (divisor == 0)
342 return (EINVAL);
343 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
344 uart_barrier(bas);
345 uart_setreg(bas, REG_DLL, divisor & 0xff);
346 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff);
347 uart_barrier(bas);
348 }
349
350 /* Set LCR and clear DLAB. */
351 uart_setreg(bas, REG_LCR, lcr);
352 uart_barrier(bas);
353 return (0);
354 }
355
356 /*
357 * Low-level UART interface.
358 */
359 static int ns8250_probe(struct uart_bas *bas);
360 static void ns8250_init(struct uart_bas *bas, int, int, int, int);
361 static void ns8250_term(struct uart_bas *bas);
362 static void ns8250_putc(struct uart_bas *bas, int);
363 static int ns8250_rxready(struct uart_bas *bas);
364 static int ns8250_getc(struct uart_bas *bas, struct mtx *);
365
366 struct uart_ops uart_ns8250_ops = {
367 .probe = ns8250_probe,
368 .init = ns8250_init,
369 .term = ns8250_term,
370 .putc = ns8250_putc,
371 .rxready = ns8250_rxready,
372 .getc = ns8250_getc,
373 };
374
375 static int
ns8250_probe(struct uart_bas * bas)376 ns8250_probe(struct uart_bas *bas)
377 {
378 u_char val;
379
380 /* Check known 0 bits that don't depend on DLAB. */
381 val = uart_getreg(bas, REG_IIR);
382 if (val & 0x30)
383 return (ENXIO);
384 /*
385 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699
386 * chip, but otherwise doesn't seem to have a function. In
387 * other words, uart(4) works regardless. Ignore that bit so
388 * the probe succeeds.
389 */
390 val = uart_getreg(bas, REG_MCR);
391 if (val & 0xa0)
392 return (ENXIO);
393
394 return (0);
395 }
396
397 static void
ns8250_init(struct uart_bas * bas,int baudrate,int databits,int stopbits,int parity)398 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
399 int parity)
400 {
401 u_char ier;
402
403 /* Disable all interrupt sources. */
404 /*
405 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA
406 * UARTs split the receive time-out interrupt bit out separately as
407 * 0x10. This gets handled by ier_mask and ier_rxbits below.
408 */
409 ier = uart_getreg(bas, REG_IER) & 0xe0;
410 uart_setreg(bas, REG_IER, ier);
411 uart_barrier(bas);
412
413 /*
414 * Loader tells us to infer the rclk when it sets xo to 0 in
415 * hw.uart.console. We know the baudrate was set by the firmware, so
416 * calculate rclk from baudrate and the divisor register. If 'div' is
417 * actually 0, the resulting 0 value will have us fall back to other
418 * rclk methods.
419 */
420 if (bas->rclk_guess && bas->rclk == 0 && baudrate != 0) {
421 uint32_t div;
422
423 div = ns8250_get_divisor(bas);
424 bas->rclk = baudrate * div * 16;
425 }
426
427 /*
428 * Pick a default because we just don't know. This likely needs future
429 * refinement, but that's hard outside of consoles to know what to use.
430 * But defer as long as possible if there's no defined baud rate.
431 */
432 if (bas->rclk == 0 && baudrate != 0)
433 bas->rclk = DEFAULT_RCLK;
434
435 ns8250_param(bas, baudrate, databits, stopbits, parity);
436
437 /* Disable the FIFO (if present). */
438 uart_setreg(bas, REG_FCR, 0);
439 uart_barrier(bas);
440
441 /* Set RTS & DTR. */
442 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR);
443 uart_barrier(bas);
444
445 ns8250_clrint(bas);
446 }
447
448 static void
ns8250_term(struct uart_bas * bas)449 ns8250_term(struct uart_bas *bas)
450 {
451
452 /* Clear RTS & DTR. */
453 uart_setreg(bas, REG_MCR, MCR_IE);
454 uart_barrier(bas);
455 }
456
457 static void
ns8250_putc(struct uart_bas * bas,int c)458 ns8250_putc(struct uart_bas *bas, int c)
459 {
460 int limit;
461
462 if (vm_guest != VM_GUEST_HV) {
463 limit = 250000;
464 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit)
465 DELAY(4);
466 }
467 uart_setreg(bas, REG_DATA, c);
468 uart_barrier(bas);
469 }
470
471 static int
ns8250_rxready(struct uart_bas * bas)472 ns8250_rxready(struct uart_bas *bas)
473 {
474
475 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0);
476 }
477
478 static int
ns8250_getc(struct uart_bas * bas,struct mtx * hwmtx)479 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx)
480 {
481 int c;
482
483 uart_lock(hwmtx);
484
485 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) {
486 uart_unlock(hwmtx);
487 DELAY(4);
488 uart_lock(hwmtx);
489 }
490
491 c = uart_getreg(bas, REG_DATA);
492
493 uart_unlock(hwmtx);
494
495 return (c);
496 }
497
498 static kobj_method_t ns8250_methods[] = {
499 KOBJMETHOD(uart_attach, ns8250_bus_attach),
500 KOBJMETHOD(uart_detach, ns8250_bus_detach),
501 KOBJMETHOD(uart_flush, ns8250_bus_flush),
502 KOBJMETHOD(uart_getsig, ns8250_bus_getsig),
503 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl),
504 KOBJMETHOD(uart_ipend, ns8250_bus_ipend),
505 KOBJMETHOD(uart_param, ns8250_bus_param),
506 KOBJMETHOD(uart_probe, ns8250_bus_probe),
507 KOBJMETHOD(uart_receive, ns8250_bus_receive),
508 KOBJMETHOD(uart_setsig, ns8250_bus_setsig),
509 KOBJMETHOD(uart_transmit, ns8250_bus_transmit),
510 KOBJMETHOD(uart_txbusy, ns8250_bus_txbusy),
511 KOBJMETHOD(uart_grab, ns8250_bus_grab),
512 KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab),
513 KOBJMETHOD_END
514 };
515
516 struct uart_class uart_ns8250_class = {
517 "ns8250",
518 ns8250_methods,
519 sizeof(struct ns8250_softc),
520 .uc_ops = &uart_ns8250_ops,
521 .uc_range = 8,
522 .uc_rclk = DEFAULT_RCLK,
523 .uc_rshift = 0
524 };
525 UART_CLASS(uart_ns8250_class);
526
527 /*
528 * XXX -- refactor out ACPI and FDT ifdefs
529 */
530 #ifdef DEV_ACPI
531 static struct acpi_spcr_compat_data acpi_spcr_compat_data[] = {
532 { &uart_ns8250_class, ACPI_DBG2_16550_COMPATIBLE },
533 { &uart_ns8250_class, ACPI_DBG2_16550_SUBSET },
534 { &uart_ns8250_class, ACPI_DBG2_16550_WITH_GAS },
535 { NULL, 0 },
536 };
537 UART_ACPI_SPCR_CLASS(acpi_spcr_compat_data);
538
539 static struct acpi_uart_compat_data acpi_compat_data[] = {
540 {"AMD0020", &uart_ns8250_class, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"},
541 {"AMDI0020", &uart_ns8250_class, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"},
542 {"APMC0D08", &uart_ns8250_class, 2, 4, 0, 0, "APM compatible UART"},
543 {"MRVL0001", &uart_ns8250_class, 2, 0, 200000000, UART_F_BUSY_DETECT, "Marvell / Synopsys Designware UART"},
544 {"SCX0006", &uart_ns8250_class, 2, 0, 62500000, UART_F_BUSY_DETECT, "SynQuacer / Synopsys Designware UART"},
545 {"HISI0031", &uart_ns8250_class, 2, 0, 200000000, UART_F_BUSY_DETECT, "HiSilicon / Synopsys Designware UART"},
546 {"INTC1006", &uart_ns8250_class, 2, 0, 25000000, 0, "Intel ARM64 UART"},
547 {"NXP0018", &uart_ns8250_class, 0, 0, 350000000, UART_F_BUSY_DETECT, "NXP / Synopsys Designware UART"},
548 {"PNP0500", &uart_ns8250_class, 0, 0, 0, 0, "Standard PC COM port"},
549 {"PNP0501", &uart_ns8250_class, 0, 0, 0, 0, "16550A-compatible COM port"},
550 {"PNP0502", &uart_ns8250_class, 0, 0, 0, 0, "Multiport serial device (non-intelligent 16550)"},
551 {"PNP0510", &uart_ns8250_class, 0, 0, 0, 0, "Generic IRDA-compatible device"},
552 {"PNP0511", &uart_ns8250_class, 0, 0, 0, 0, "Generic IRDA-compatible device"},
553 {"WACF004", &uart_ns8250_class, 0, 0, 0, 0, "Wacom Tablet PC Screen"},
554 {"WACF00E", &uart_ns8250_class, 0, 0, 0, 0, "Wacom Tablet PC Screen 00e"},
555 {"FUJ02E5", &uart_ns8250_class, 0, 0, 0, 0, "Wacom Tablet at FuS Lifebook T"},
556 {NULL, NULL, 0 , 0, 0, 0, NULL},
557 };
558 UART_ACPI_CLASS_AND_DEVICE(acpi_compat_data);
559 #endif
560
561 #ifdef FDT
562 static struct ofw_compat_data compat_data[] = {
563 {"ns16550", (uintptr_t)&uart_ns8250_class},
564 {"ns16550a", (uintptr_t)&uart_ns8250_class},
565 {NULL, (uintptr_t)NULL},
566 };
567 UART_FDT_CLASS_AND_DEVICE(compat_data);
568 #endif
569
570 /* Use token-pasting to form SER_ and MSR_ named constants. */
571 #define SER(sig) SER_##sig
572 #define SERD(sig) SER_D##sig
573 #define MSR(sig) MSR_##sig
574 #define MSRD(sig) MSR_D##sig
575
576 /*
577 * Detect signal changes using software delta detection. The previous state of
578 * the signals is in 'var' the new hardware state is in 'msr', and 'sig' is the
579 * short name (DCD, CTS, etc) of the signal bit being processed; 'var' gets the
580 * new state of both the signal and the delta bits.
581 */
582 #define SIGCHGSW(var, msr, sig) \
583 if ((msr) & MSR(sig)) { \
584 if ((var & SER(sig)) == 0) \
585 var |= SERD(sig) | SER(sig); \
586 } else { \
587 if ((var & SER(sig)) != 0) \
588 var = SERD(sig) | (var & ~SER(sig)); \
589 }
590
591 /*
592 * Detect signal changes using the hardware msr delta bits. This is currently
593 * used only when PPS timing information is being captured using the "narrow
594 * pulse" option. With a narrow PPS pulse the signal may not still be asserted
595 * by time the interrupt handler is invoked. The hardware will latch the fact
596 * that it changed in the delta bits.
597 */
598 #define SIGCHGHW(var, msr, sig) \
599 if ((msr) & MSRD(sig)) { \
600 if (((msr) & MSR(sig)) != 0) \
601 var |= SERD(sig) | SER(sig); \
602 else \
603 var = SERD(sig) | (var & ~SER(sig)); \
604 }
605
606 int
ns8250_bus_attach(struct uart_softc * sc)607 ns8250_bus_attach(struct uart_softc *sc)
608 {
609 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
610 struct uart_bas *bas;
611 unsigned int ivar;
612 #ifdef FDT
613 phandle_t node;
614 pcell_t cell;
615 #endif
616
617 #ifdef FDT
618 /* Check whether uart has a broken txfifo. */
619 node = ofw_bus_get_node(sc->sc_dev);
620 if ((OF_getencprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0)
621 broken_txfifo = cell ? 1 : 0;
622 #endif
623
624 bas = &sc->sc_bas;
625
626 ns8250->busy_detect = bas->busy_detect;
627 ns8250->mcr = uart_getreg(bas, REG_MCR);
628 ns8250->fcr = FCR_ENABLE;
629 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags",
630 &ivar)) {
631 if (UART_FLAGS_FCR_RX_LOW(ivar))
632 ns8250->fcr |= FCR_RX_LOW;
633 else if (UART_FLAGS_FCR_RX_MEDL(ivar))
634 ns8250->fcr |= FCR_RX_MEDL;
635 else if (UART_FLAGS_FCR_RX_HIGH(ivar))
636 ns8250->fcr |= FCR_RX_HIGH;
637 else
638 ns8250->fcr |= FCR_RX_MEDH;
639 } else
640 ns8250->fcr |= FCR_RX_MEDH;
641
642 /* Get IER mask */
643 ivar = 0xf0;
644 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask",
645 &ivar);
646 ns8250->ier_mask = (uint8_t)(ivar & 0xff);
647
648 /* Get IER RX interrupt bits */
649 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY;
650 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits",
651 &ivar);
652 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff);
653
654 uart_setreg(bas, REG_FCR, ns8250->fcr);
655 uart_barrier(bas);
656 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
657
658 if (ns8250->mcr & MCR_DTR)
659 sc->sc_hwsig |= SER_DTR;
660 if (ns8250->mcr & MCR_RTS)
661 sc->sc_hwsig |= SER_RTS;
662 ns8250_bus_getsig(sc);
663
664 ns8250_clrint(bas);
665 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
666 ns8250->ier |= ns8250->ier_rxbits;
667 uart_setreg(bas, REG_IER, ns8250->ier);
668 uart_barrier(bas);
669
670 /*
671 * Timing of the H/W access was changed with r253161 of uart_core.c
672 * It has been observed that an ITE IT8513E would signal a break
673 * condition with pretty much every character it received, unless
674 * it had enough time to settle between ns8250_bus_attach() and
675 * ns8250_bus_ipend() -- which it accidentally had before r253161.
676 * It's not understood why the UART chip behaves this way and it
677 * could very well be that the DELAY make the H/W work in the same
678 * accidental manner as before. More analysis is warranted, but
679 * at least now we fixed a known regression.
680 */
681 DELAY(200);
682 return (0);
683 }
684
685 int
ns8250_bus_detach(struct uart_softc * sc)686 ns8250_bus_detach(struct uart_softc *sc)
687 {
688 struct ns8250_softc *ns8250;
689 struct uart_bas *bas;
690 u_char ier;
691
692 ns8250 = (struct ns8250_softc *)sc;
693 bas = &sc->sc_bas;
694 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
695 uart_setreg(bas, REG_IER, ier);
696 uart_barrier(bas);
697 ns8250_clrint(bas);
698 return (0);
699 }
700
701 int
ns8250_bus_flush(struct uart_softc * sc,int what)702 ns8250_bus_flush(struct uart_softc *sc, int what)
703 {
704 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
705 struct uart_bas *bas;
706 int error;
707
708 bas = &sc->sc_bas;
709 uart_lock(sc->sc_hwmtx);
710 if (sc->sc_rxfifosz > 1) {
711 ns8250_flush(bas, what);
712 uart_setreg(bas, REG_FCR, ns8250->fcr);
713 uart_barrier(bas);
714 error = 0;
715 } else
716 error = ns8250_drain(bas, what);
717 uart_unlock(sc->sc_hwmtx);
718 return (error);
719 }
720
721 int
ns8250_bus_getsig(struct uart_softc * sc)722 ns8250_bus_getsig(struct uart_softc *sc)
723 {
724 uint32_t old, sig;
725 uint8_t msr;
726
727 /*
728 * The delta bits are reputed to be broken on some hardware, so use
729 * software delta detection by default. Use the hardware delta bits
730 * when capturing PPS pulses which are too narrow for software detection
731 * to see the edges. Hardware delta for RI doesn't work like the
732 * others, so always use software for it. Other threads may be changing
733 * other (non-MSR) bits in sc_hwsig, so loop until it can successfully
734 * update without other changes happening. Note that the SIGCHGxx()
735 * macros carefully preserve the delta bits when we have to loop several
736 * times and a signal transitions between iterations.
737 */
738 do {
739 old = sc->sc_hwsig;
740 sig = old;
741 uart_lock(sc->sc_hwmtx);
742 msr = uart_getreg(&sc->sc_bas, REG_MSR);
743 uart_unlock(sc->sc_hwmtx);
744 if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE) {
745 SIGCHGHW(sig, msr, DSR);
746 SIGCHGHW(sig, msr, CTS);
747 SIGCHGHW(sig, msr, DCD);
748 } else {
749 SIGCHGSW(sig, msr, DSR);
750 SIGCHGSW(sig, msr, CTS);
751 SIGCHGSW(sig, msr, DCD);
752 }
753 SIGCHGSW(sig, msr, RI);
754 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, sig & ~SER_MASK_DELTA));
755 return (sig);
756 }
757
758 int
ns8250_bus_ioctl(struct uart_softc * sc,int request,intptr_t data)759 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
760 {
761 struct uart_bas *bas;
762 int baudrate, divisor, error;
763 uint8_t efr, lcr;
764
765 bas = &sc->sc_bas;
766 error = 0;
767 uart_lock(sc->sc_hwmtx);
768 switch (request) {
769 case UART_IOCTL_BREAK:
770 lcr = uart_getreg(bas, REG_LCR);
771 if (data)
772 lcr |= LCR_SBREAK;
773 else
774 lcr &= ~LCR_SBREAK;
775 uart_setreg(bas, REG_LCR, lcr);
776 uart_barrier(bas);
777 break;
778 case UART_IOCTL_IFLOW:
779 lcr = uart_getreg(bas, REG_LCR);
780 uart_barrier(bas);
781 uart_setreg(bas, REG_LCR, 0xbf);
782 uart_barrier(bas);
783 efr = uart_getreg(bas, REG_EFR);
784 if (data)
785 efr |= EFR_RTS;
786 else
787 efr &= ~EFR_RTS;
788 uart_setreg(bas, REG_EFR, efr);
789 uart_barrier(bas);
790 uart_setreg(bas, REG_LCR, lcr);
791 uart_barrier(bas);
792 break;
793 case UART_IOCTL_OFLOW:
794 lcr = uart_getreg(bas, REG_LCR);
795 uart_barrier(bas);
796 uart_setreg(bas, REG_LCR, 0xbf);
797 uart_barrier(bas);
798 efr = uart_getreg(bas, REG_EFR);
799 if (data)
800 efr |= EFR_CTS;
801 else
802 efr &= ~EFR_CTS;
803 uart_setreg(bas, REG_EFR, efr);
804 uart_barrier(bas);
805 uart_setreg(bas, REG_LCR, lcr);
806 uart_barrier(bas);
807 break;
808 case UART_IOCTL_BAUD:
809 divisor = ns8250_get_divisor(bas);
810 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0;
811 if (baudrate > 0)
812 *(int*)data = baudrate;
813 else
814 error = ENXIO;
815 break;
816 default:
817 error = EINVAL;
818 break;
819 }
820 uart_unlock(sc->sc_hwmtx);
821 return (error);
822 }
823
824 int
ns8250_bus_ipend(struct uart_softc * sc)825 ns8250_bus_ipend(struct uart_softc *sc)
826 {
827 struct uart_bas *bas;
828 struct ns8250_softc *ns8250;
829 int ipend;
830 uint8_t iir, lsr;
831
832 ns8250 = (struct ns8250_softc *)sc;
833 bas = &sc->sc_bas;
834 uart_lock(sc->sc_hwmtx);
835 iir = uart_getreg(bas, REG_IIR);
836
837 if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) {
838 (void)uart_getreg(bas, DW_REG_USR);
839 uart_unlock(sc->sc_hwmtx);
840 return (0);
841 }
842 if (iir & IIR_NOPEND) {
843 uart_unlock(sc->sc_hwmtx);
844 return (0);
845 }
846 ipend = 0;
847 if (iir & IIR_RXRDY) {
848 lsr = uart_getreg(bas, REG_LSR);
849 if (lsr & LSR_OE)
850 ipend |= SER_INT_OVERRUN;
851 if (lsr & LSR_BI)
852 ipend |= SER_INT_BREAK;
853 if (lsr & LSR_RXRDY)
854 ipend |= SER_INT_RXREADY;
855 } else {
856 if (iir & IIR_TXRDY) {
857 ipend |= SER_INT_TXIDLE;
858 ns8250->ier &= ~IER_ETXRDY;
859 uart_setreg(bas, REG_IER, ns8250->ier);
860 uart_barrier(bas);
861 } else
862 ipend |= SER_INT_SIGCHG;
863 }
864 if (ipend == 0)
865 ns8250_clrint(bas);
866 uart_unlock(sc->sc_hwmtx);
867 return (ipend);
868 }
869
870 int
ns8250_bus_param(struct uart_softc * sc,int baudrate,int databits,int stopbits,int parity)871 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits,
872 int stopbits, int parity)
873 {
874 struct ns8250_softc *ns8250;
875 struct uart_bas *bas;
876 int error, limit;
877
878 ns8250 = (struct ns8250_softc*)sc;
879 bas = &sc->sc_bas;
880 uart_lock(sc->sc_hwmtx);
881 /*
882 * When using DW UART with BUSY detection it is necessary to wait
883 * until all serial transfers are finished before manipulating the
884 * line control. LCR will not be affected when UART is busy.
885 */
886 if (ns8250->busy_detect != 0) {
887 /*
888 * Pick an arbitrary high limit to avoid getting stuck in
889 * an infinite loop in case when the hardware is broken.
890 */
891 limit = 10 * 1024;
892 while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) &&
893 --limit)
894 DELAY(4);
895
896 if (limit <= 0) {
897 /* UART appears to be stuck */
898 uart_unlock(sc->sc_hwmtx);
899 return (EIO);
900 }
901 }
902
903 error = ns8250_param(bas, baudrate, databits, stopbits, parity);
904 uart_unlock(sc->sc_hwmtx);
905 return (error);
906 }
907
908 int
ns8250_bus_probe(struct uart_softc * sc)909 ns8250_bus_probe(struct uart_softc *sc)
910 {
911 struct uart_bas *bas;
912 int count, delay, error, limit;
913 uint8_t lsr, mcr, ier;
914
915 bas = &sc->sc_bas;
916
917 error = ns8250_probe(bas);
918 if (error)
919 return (error);
920
921 mcr = MCR_IE;
922 if (sc->sc_sysdev == NULL) {
923 /* By using ns8250_init() we also set DTR and RTS. */
924 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE);
925 } else
926 mcr |= MCR_DTR | MCR_RTS;
927
928 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
929 if (error)
930 return (error);
931
932 /*
933 * Set loopback mode. This avoids having garbage on the wire and
934 * also allows us send and receive data. We set DTR and RTS to
935 * avoid the possibility that automatic flow-control prevents
936 * any data from being sent.
937 */
938 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS);
939 uart_barrier(bas);
940
941 /*
942 * Enable FIFOs. And check that the UART has them. If not, we're
943 * done. Since this is the first time we enable the FIFOs, we reset
944 * them.
945 */
946 uart_setreg(bas, REG_FCR, FCR_ENABLE);
947 uart_barrier(bas);
948 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) {
949 /*
950 * NS16450 or INS8250. We don't bother to differentiate
951 * between them. They're too old to be interesting.
952 */
953 uart_setreg(bas, REG_MCR, mcr);
954 uart_barrier(bas);
955 sc->sc_rxfifosz = sc->sc_txfifosz = 1;
956 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible");
957 return (0);
958 }
959
960 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST);
961 uart_barrier(bas);
962
963 count = 0;
964 delay = ns8250_delay(bas);
965
966 /* We have FIFOs. Drain the transmitter and receiver. */
967 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER);
968 if (error) {
969 uart_setreg(bas, REG_MCR, mcr);
970 uart_setreg(bas, REG_FCR, 0);
971 uart_barrier(bas);
972 goto describe;
973 }
974
975 /*
976 * We should have a sufficiently clean "pipe" to determine the
977 * size of the FIFOs. We send as much characters as is reasonable
978 * and wait for the overflow bit in the LSR register to be
979 * asserted, counting the characters as we send them. Based on
980 * that count we know the FIFO size.
981 */
982 do {
983 uart_setreg(bas, REG_DATA, 0);
984 uart_barrier(bas);
985 count++;
986
987 limit = 30;
988 lsr = 0;
989 /*
990 * LSR bits are cleared upon read, so we must accumulate
991 * them to be able to test LSR_OE below.
992 */
993 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 &&
994 --limit)
995 DELAY(delay);
996 if (limit == 0) {
997 /* See the comment in ns8250_init(). */
998 ier = uart_getreg(bas, REG_IER) & 0xe0;
999 uart_setreg(bas, REG_IER, ier);
1000 uart_setreg(bas, REG_MCR, mcr);
1001 uart_setreg(bas, REG_FCR, 0);
1002 uart_barrier(bas);
1003 count = 0;
1004 goto describe;
1005 }
1006 } while ((lsr & LSR_OE) == 0 && count < 260);
1007 count--;
1008
1009 uart_setreg(bas, REG_MCR, mcr);
1010
1011 /* Reset FIFOs. */
1012 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
1013
1014 describe:
1015 if (count >= 14 && count <= 16) {
1016 sc->sc_rxfifosz = 16;
1017 device_set_desc(sc->sc_dev, "16550 or compatible");
1018 } else if (count >= 28 && count <= 32) {
1019 sc->sc_rxfifosz = 32;
1020 device_set_desc(sc->sc_dev, "16650 or compatible");
1021 } else if (count >= 56 && count <= 64) {
1022 sc->sc_rxfifosz = 64;
1023 device_set_desc(sc->sc_dev, "16750 or compatible");
1024 } else if (count >= 112 && count <= 128) {
1025 sc->sc_rxfifosz = 128;
1026 device_set_desc(sc->sc_dev, "16950 or compatible");
1027 } else if (count >= 224 && count <= 256) {
1028 sc->sc_rxfifosz = 256;
1029 device_set_desc(sc->sc_dev, "16x50 with 256 byte FIFO");
1030 } else {
1031 sc->sc_rxfifosz = 16;
1032 device_set_desc(sc->sc_dev,
1033 "Non-standard ns8250 class UART with FIFOs");
1034 }
1035
1036 /*
1037 * Force the Tx FIFO size to 16 bytes for now. We don't program the
1038 * Tx trigger. Also, we assume that all data has been sent when the
1039 * interrupt happens.
1040 */
1041 sc->sc_txfifosz = 16;
1042
1043 #if 0
1044 /*
1045 * XXX there are some issues related to hardware flow control and
1046 * it's likely that uart(4) is the cause. This basically needs more
1047 * investigation, but we avoid using for hardware flow control
1048 * until then.
1049 */
1050 /* 16650s or higher have automatic flow control. */
1051 if (sc->sc_rxfifosz > 16) {
1052 sc->sc_hwiflow = 1;
1053 sc->sc_hwoflow = 1;
1054 }
1055 #endif
1056
1057 return (0);
1058 }
1059
1060 int
ns8250_bus_receive(struct uart_softc * sc)1061 ns8250_bus_receive(struct uart_softc *sc)
1062 {
1063 struct uart_bas *bas;
1064 struct ns8250_softc *ns8250 = (struct ns8250_softc *)sc;
1065 int xc;
1066 uint8_t lsr;
1067
1068 bas = &sc->sc_bas;
1069 uart_lock(sc->sc_hwmtx);
1070 lsr = uart_getreg(bas, REG_LSR);
1071 while (lsr & LSR_RXRDY) {
1072 if (uart_rx_full(sc)) {
1073 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
1074 break;
1075 }
1076 /* Filter out possible noise on the line.
1077 * Expect that the device should be able to transmit as well as
1078 * receive, so if we receive too many characters before transmit
1079 * is ready, it's probably noise.
1080 */
1081 if ((lsr & (LSR_TXRDY | LSR_TEMT)) == 0 &&
1082 uart_noise_threshold > 0) {
1083 if (++ns8250->noise_count >= uart_noise_threshold)
1084 break;
1085 } else
1086 ns8250->noise_count = 0;
1087 xc = uart_getreg(bas, REG_DATA);
1088 if (lsr & LSR_FE)
1089 xc |= UART_STAT_FRAMERR;
1090 if (lsr & LSR_PE)
1091 xc |= UART_STAT_PARERR;
1092 uart_rx_put(sc, xc);
1093 lsr = uart_getreg(bas, REG_LSR);
1094 }
1095 /* Discard everything left in the Rx FIFO. */
1096 while (lsr & LSR_RXRDY) {
1097 (void)uart_getreg(bas, REG_DATA);
1098 uart_barrier(bas);
1099 lsr = uart_getreg(bas, REG_LSR);
1100 }
1101 uart_unlock(sc->sc_hwmtx);
1102 return (0);
1103 }
1104
1105 int
ns8250_bus_setsig(struct uart_softc * sc,int sig)1106 ns8250_bus_setsig(struct uart_softc *sc, int sig)
1107 {
1108 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
1109 struct uart_bas *bas;
1110 uint32_t new, old;
1111
1112 bas = &sc->sc_bas;
1113 do {
1114 old = sc->sc_hwsig;
1115 new = old;
1116 if (sig & SER_DDTR) {
1117 new = (new & ~SER_DTR) | (sig & (SER_DTR | SER_DDTR));
1118 }
1119 if (sig & SER_DRTS) {
1120 new = (new & ~SER_RTS) | (sig & (SER_RTS | SER_DRTS));
1121 }
1122 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
1123 uart_lock(sc->sc_hwmtx);
1124 ns8250->mcr &= ~(MCR_DTR|MCR_RTS);
1125 if (new & SER_DTR)
1126 ns8250->mcr |= MCR_DTR;
1127 if (new & SER_RTS)
1128 ns8250->mcr |= MCR_RTS;
1129 uart_setreg(bas, REG_MCR, ns8250->mcr);
1130 uart_barrier(bas);
1131 uart_unlock(sc->sc_hwmtx);
1132 return (0);
1133 }
1134
1135 int
ns8250_bus_transmit(struct uart_softc * sc)1136 ns8250_bus_transmit(struct uart_softc *sc)
1137 {
1138 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
1139 struct uart_bas *bas;
1140 int i;
1141
1142 bas = &sc->sc_bas;
1143 uart_lock(sc->sc_hwmtx);
1144 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0)
1145 DELAY(4);
1146 for (i = 0; i < sc->sc_txdatasz; i++) {
1147 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
1148 uart_barrier(bas);
1149 }
1150 if (!broken_txfifo)
1151 ns8250->ier |= IER_ETXRDY;
1152 uart_setreg(bas, REG_IER, ns8250->ier);
1153 uart_barrier(bas);
1154 if (broken_txfifo)
1155 ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
1156 else
1157 sc->sc_txbusy = 1;
1158 uart_unlock(sc->sc_hwmtx);
1159 if (broken_txfifo)
1160 uart_sched_softih(sc, SER_INT_TXIDLE);
1161 return (0);
1162 }
1163
1164 bool
ns8250_bus_txbusy(struct uart_softc * sc)1165 ns8250_bus_txbusy(struct uart_softc *sc)
1166 {
1167 struct uart_bas *bas = &sc->sc_bas;
1168
1169 if ((uart_getreg(bas, REG_LSR) & (LSR_TEMT | LSR_THRE)) !=
1170 (LSR_TEMT | LSR_THRE))
1171 return (true);
1172 return (false);
1173 }
1174
1175 void
ns8250_bus_grab(struct uart_softc * sc)1176 ns8250_bus_grab(struct uart_softc *sc)
1177 {
1178 struct uart_bas *bas = &sc->sc_bas;
1179 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
1180 u_char ier;
1181
1182 /*
1183 * turn off all interrupts to enter polling mode. Leave the
1184 * saved mask alone. We'll restore whatever it was in ungrab.
1185 * All pending interrupt signals are reset when IER is set to 0.
1186 */
1187 uart_lock(sc->sc_hwmtx);
1188 ier = uart_getreg(bas, REG_IER);
1189 uart_setreg(bas, REG_IER, ier & ns8250->ier_mask);
1190 uart_barrier(bas);
1191 uart_unlock(sc->sc_hwmtx);
1192 }
1193
1194 void
ns8250_bus_ungrab(struct uart_softc * sc)1195 ns8250_bus_ungrab(struct uart_softc *sc)
1196 {
1197 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
1198 struct uart_bas *bas = &sc->sc_bas;
1199
1200 /*
1201 * Restore previous interrupt mask
1202 */
1203 uart_lock(sc->sc_hwmtx);
1204 uart_setreg(bas, REG_IER, ns8250->ier);
1205 uart_barrier(bas);
1206 uart_unlock(sc->sc_hwmtx);
1207 }
1208