1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3  * Copyright 2019 Raptor Engineering, LLC
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: AMD
24  *
25  */
26 
27 #include "dm_services.h"
28 #include "dc.h"
29 
30 #include "dcn20/dcn20_init.h"
31 
32 #include "resource.h"
33 #include "include/irq_service_interface.h"
34 #include "dcn20/dcn20_resource.h"
35 
36 #include "dml/dcn20/dcn20_fpu.h"
37 
38 #include "dcn10/dcn10_hubp.h"
39 #include "dcn10/dcn10_ipp.h"
40 #include "dcn20/dcn20_hubbub.h"
41 #include "dcn20/dcn20_mpc.h"
42 #include "dcn20/dcn20_hubp.h"
43 #include "irq/dcn20/irq_service_dcn20.h"
44 #include "dcn20/dcn20_dpp.h"
45 #include "dcn20/dcn20_optc.h"
46 #include "dcn20/dcn20_hwseq.h"
47 #include "dce110/dce110_hwseq.h"
48 #include "dcn10/dcn10_resource.h"
49 #include "dcn20/dcn20_opp.h"
50 
51 #include "dcn20/dcn20_dsc.h"
52 
53 #include "dcn20/dcn20_link_encoder.h"
54 #include "dcn20/dcn20_stream_encoder.h"
55 #include "dce/dce_clock_source.h"
56 #include "dce/dce_audio.h"
57 #include "dce/dce_hwseq.h"
58 #include "virtual/virtual_stream_encoder.h"
59 #include "dce110/dce110_resource.h"
60 #include "dml/display_mode_vba.h"
61 #include "dcn20/dcn20_dccg.h"
62 #include "dcn20/dcn20_vmid.h"
63 #include "dce/dce_panel_cntl.h"
64 
65 #include "dcn20/dcn20_dwb.h"
66 #include "dcn20/dcn20_mmhubbub.h"
67 
68 #include "navi10_ip_offset.h"
69 
70 #include "dcn/dcn_2_0_0_offset.h"
71 #include "dcn/dcn_2_0_0_sh_mask.h"
72 #include "dpcs/dpcs_2_0_0_offset.h"
73 #include "dpcs/dpcs_2_0_0_sh_mask.h"
74 
75 #include "nbio/nbio_2_3_offset.h"
76 
77 #include "mmhub/mmhub_2_0_0_offset.h"
78 #include "mmhub/mmhub_2_0_0_sh_mask.h"
79 
80 #include "reg_helper.h"
81 #include "dce/dce_abm.h"
82 #include "dce/dce_dmcu.h"
83 #include "dce/dce_aux.h"
84 #include "dce/dce_i2c.h"
85 #include "vm_helper.h"
86 
87 #include "link_enc_cfg.h"
88 #include "link.h"
89 
90 #define DC_LOGGER_INIT(logger)
91 
92 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
93 	#define mmDP0_DP_DPHY_INTERNAL_CTRL		0x210f
94 	#define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
95 	#define mmDP1_DP_DPHY_INTERNAL_CTRL		0x220f
96 	#define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
97 	#define mmDP2_DP_DPHY_INTERNAL_CTRL		0x230f
98 	#define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
99 	#define mmDP3_DP_DPHY_INTERNAL_CTRL		0x240f
100 	#define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
101 	#define mmDP4_DP_DPHY_INTERNAL_CTRL		0x250f
102 	#define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
103 	#define mmDP5_DP_DPHY_INTERNAL_CTRL		0x260f
104 	#define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
105 	#define mmDP6_DP_DPHY_INTERNAL_CTRL		0x270f
106 	#define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
107 #endif
108 
109 
110 enum dcn20_clk_src_array_id {
111 	DCN20_CLK_SRC_PLL0,
112 	DCN20_CLK_SRC_PLL1,
113 	DCN20_CLK_SRC_PLL2,
114 	DCN20_CLK_SRC_PLL3,
115 	DCN20_CLK_SRC_PLL4,
116 	DCN20_CLK_SRC_PLL5,
117 	DCN20_CLK_SRC_TOTAL
118 };
119 
120 /* begin *********************
121  * macros to expend register list macro defined in HW object header file */
122 
123 /* DCN */
124 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
125 
126 #define BASE(seg) BASE_INNER(seg)
127 
128 #define SR(reg_name)\
129 		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
130 					mm ## reg_name
131 
132 #define SRI(reg_name, block, id)\
133 	.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
134 					mm ## block ## id ## _ ## reg_name
135 
136 #define SRI2_DWB(reg_name, block, id)\
137 	.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
138 					mm ## reg_name
139 #define SF_DWB(reg_name, field_name, post_fix)\
140 	.field_name = reg_name ## __ ## field_name ## post_fix
141 
142 #define SF_DWB2(reg_name, block, id, field_name, post_fix)	\
143 	.field_name = reg_name ## __ ## field_name ## post_fix
144 
145 #define SRIR(var_name, reg_name, block, id)\
146 	.var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
147 					mm ## block ## id ## _ ## reg_name
148 
149 #define SRII(reg_name, block, id)\
150 	.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
151 					mm ## block ## id ## _ ## reg_name
152 
153 #define DCCG_SRII(reg_name, block, id)\
154 	.block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
155 					mm ## block ## id ## _ ## reg_name
156 
157 #define VUPDATE_SRII(reg_name, block, id)\
158 	.reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
159 					mm ## reg_name ## _ ## block ## id
160 
161 /* NBIO */
162 #define NBIO_BASE_INNER(seg) \
163 	NBIO_BASE__INST0_SEG ## seg
164 
165 #define NBIO_BASE(seg) \
166 	NBIO_BASE_INNER(seg)
167 
168 #define NBIO_SR(reg_name)\
169 		.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
170 					mm ## reg_name
171 
172 /* MMHUB */
173 #define MMHUB_BASE_INNER(seg) \
174 	MMHUB_BASE__INST0_SEG ## seg
175 
176 #define MMHUB_BASE(seg) \
177 	MMHUB_BASE_INNER(seg)
178 
179 #define MMHUB_SR(reg_name)\
180 		.reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
181 					mmMM ## reg_name
182 
183 static const struct bios_registers bios_regs = {
184 		NBIO_SR(BIOS_SCRATCH_3),
185 		NBIO_SR(BIOS_SCRATCH_6)
186 };
187 
188 #define clk_src_regs(index, pllid)\
189 [index] = {\
190 	CS_COMMON_REG_LIST_DCN2_0(index, pllid),\
191 }
192 
193 static const struct dce110_clk_src_regs clk_src_regs[] = {
194 	clk_src_regs(0, A),
195 	clk_src_regs(1, B),
196 	clk_src_regs(2, C),
197 	clk_src_regs(3, D),
198 	clk_src_regs(4, E),
199 	clk_src_regs(5, F)
200 };
201 
202 static const struct dce110_clk_src_shift cs_shift = {
203 		CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
204 };
205 
206 static const struct dce110_clk_src_mask cs_mask = {
207 		CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
208 };
209 
210 static const struct dce_dmcu_registers dmcu_regs = {
211 		DMCU_DCN10_REG_LIST()
212 };
213 
214 static const struct dce_dmcu_shift dmcu_shift = {
215 		DMCU_MASK_SH_LIST_DCN10(__SHIFT)
216 };
217 
218 static const struct dce_dmcu_mask dmcu_mask = {
219 		DMCU_MASK_SH_LIST_DCN10(_MASK)
220 };
221 
222 static const struct dce_abm_registers abm_regs = {
223 		ABM_DCN20_REG_LIST()
224 };
225 
226 static const struct dce_abm_shift abm_shift = {
227 		ABM_MASK_SH_LIST_DCN20(__SHIFT)
228 };
229 
230 static const struct dce_abm_mask abm_mask = {
231 		ABM_MASK_SH_LIST_DCN20(_MASK)
232 };
233 
234 #define audio_regs(id)\
235 [id] = {\
236 		AUD_COMMON_REG_LIST(id)\
237 }
238 
239 static const struct dce_audio_registers audio_regs[] = {
240 	audio_regs(0),
241 	audio_regs(1),
242 	audio_regs(2),
243 	audio_regs(3),
244 	audio_regs(4),
245 	audio_regs(5),
246 	audio_regs(6),
247 };
248 
249 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
250 		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
251 		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
252 		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
253 
254 static const struct dce_audio_shift audio_shift = {
255 		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
256 };
257 
258 static const struct dce_audio_mask audio_mask = {
259 		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
260 };
261 
262 #define stream_enc_regs(id)\
263 [id] = {\
264 	SE_DCN2_REG_LIST(id)\
265 }
266 
267 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
268 	stream_enc_regs(0),
269 	stream_enc_regs(1),
270 	stream_enc_regs(2),
271 	stream_enc_regs(3),
272 	stream_enc_regs(4),
273 	stream_enc_regs(5),
274 };
275 
276 static const struct dcn10_stream_encoder_shift se_shift = {
277 		SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
278 };
279 
280 static const struct dcn10_stream_encoder_mask se_mask = {
281 		SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
282 };
283 
284 
285 #define aux_regs(id)\
286 [id] = {\
287 	DCN2_AUX_REG_LIST(id)\
288 }
289 
290 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
291 		aux_regs(0),
292 		aux_regs(1),
293 		aux_regs(2),
294 		aux_regs(3),
295 		aux_regs(4),
296 		aux_regs(5)
297 };
298 
299 #define hpd_regs(id)\
300 [id] = {\
301 	HPD_REG_LIST(id)\
302 }
303 
304 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
305 		hpd_regs(0),
306 		hpd_regs(1),
307 		hpd_regs(2),
308 		hpd_regs(3),
309 		hpd_regs(4),
310 		hpd_regs(5)
311 };
312 
313 #define link_regs(id, phyid)\
314 [id] = {\
315 	LE_DCN10_REG_LIST(id), \
316 	UNIPHY_DCN2_REG_LIST(phyid), \
317 	DPCS_DCN2_REG_LIST(id), \
318 	SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
319 }
320 
321 static const struct dcn10_link_enc_registers link_enc_regs[] = {
322 	link_regs(0, A),
323 	link_regs(1, B),
324 	link_regs(2, C),
325 	link_regs(3, D),
326 	link_regs(4, E),
327 	link_regs(5, F)
328 };
329 
330 static const struct dcn10_link_enc_shift le_shift = {
331 	LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\
332 	DPCS_DCN2_MASK_SH_LIST(__SHIFT)
333 };
334 
335 static const struct dcn10_link_enc_mask le_mask = {
336 	LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\
337 	DPCS_DCN2_MASK_SH_LIST(_MASK)
338 };
339 
340 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
341 	{ DCN_PANEL_CNTL_REG_LIST() }
342 };
343 
344 static const struct dce_panel_cntl_shift panel_cntl_shift = {
345 	DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
346 };
347 
348 static const struct dce_panel_cntl_mask panel_cntl_mask = {
349 	DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
350 };
351 
352 #define ipp_regs(id)\
353 [id] = {\
354 	IPP_REG_LIST_DCN20(id),\
355 }
356 
357 static const struct dcn10_ipp_registers ipp_regs[] = {
358 	ipp_regs(0),
359 	ipp_regs(1),
360 	ipp_regs(2),
361 	ipp_regs(3),
362 	ipp_regs(4),
363 	ipp_regs(5),
364 };
365 
366 static const struct dcn10_ipp_shift ipp_shift = {
367 		IPP_MASK_SH_LIST_DCN20(__SHIFT)
368 };
369 
370 static const struct dcn10_ipp_mask ipp_mask = {
371 		IPP_MASK_SH_LIST_DCN20(_MASK),
372 };
373 
374 #define opp_regs(id)\
375 [id] = {\
376 	OPP_REG_LIST_DCN20(id),\
377 }
378 
379 static const struct dcn20_opp_registers opp_regs[] = {
380 	opp_regs(0),
381 	opp_regs(1),
382 	opp_regs(2),
383 	opp_regs(3),
384 	opp_regs(4),
385 	opp_regs(5),
386 };
387 
388 static const struct dcn20_opp_shift opp_shift = {
389 		OPP_MASK_SH_LIST_DCN20(__SHIFT)
390 };
391 
392 static const struct dcn20_opp_mask opp_mask = {
393 		OPP_MASK_SH_LIST_DCN20(_MASK)
394 };
395 
396 #define aux_engine_regs(id)\
397 [id] = {\
398 	AUX_COMMON_REG_LIST0(id), \
399 	.AUXN_IMPCAL = 0, \
400 	.AUXP_IMPCAL = 0, \
401 	.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
402 }
403 
404 static const struct dce110_aux_registers aux_engine_regs[] = {
405 		aux_engine_regs(0),
406 		aux_engine_regs(1),
407 		aux_engine_regs(2),
408 		aux_engine_regs(3),
409 		aux_engine_regs(4),
410 		aux_engine_regs(5)
411 };
412 
413 #define tf_regs(id)\
414 [id] = {\
415 	TF_REG_LIST_DCN20(id),\
416 	TF_REG_LIST_DCN20_COMMON_APPEND(id),\
417 }
418 
419 static const struct dcn2_dpp_registers tf_regs[] = {
420 	tf_regs(0),
421 	tf_regs(1),
422 	tf_regs(2),
423 	tf_regs(3),
424 	tf_regs(4),
425 	tf_regs(5),
426 };
427 
428 static const struct dcn2_dpp_shift tf_shift = {
429 		TF_REG_LIST_SH_MASK_DCN20(__SHIFT),
430 		TF_DEBUG_REG_LIST_SH_DCN20
431 };
432 
433 static const struct dcn2_dpp_mask tf_mask = {
434 		TF_REG_LIST_SH_MASK_DCN20(_MASK),
435 		TF_DEBUG_REG_LIST_MASK_DCN20
436 };
437 
438 #define dwbc_regs_dcn2(id)\
439 [id] = {\
440 	DWBC_COMMON_REG_LIST_DCN2_0(id),\
441 		}
442 
443 static const struct dcn20_dwbc_registers dwbc20_regs[] = {
444 	dwbc_regs_dcn2(0),
445 };
446 
447 static const struct dcn20_dwbc_shift dwbc20_shift = {
448 	DWBC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
449 };
450 
451 static const struct dcn20_dwbc_mask dwbc20_mask = {
452 	DWBC_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
453 };
454 
455 #define mcif_wb_regs_dcn2(id)\
456 [id] = {\
457 	MCIF_WB_COMMON_REG_LIST_DCN2_0(id),\
458 		}
459 
460 static const struct dcn20_mmhubbub_registers mcif_wb20_regs[] = {
461 	mcif_wb_regs_dcn2(0),
462 };
463 
464 static const struct dcn20_mmhubbub_shift mcif_wb20_shift = {
465 	MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
466 };
467 
468 static const struct dcn20_mmhubbub_mask mcif_wb20_mask = {
469 	MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
470 };
471 
472 static const struct dcn20_mpc_registers mpc_regs = {
473 		MPC_REG_LIST_DCN2_0(0),
474 		MPC_REG_LIST_DCN2_0(1),
475 		MPC_REG_LIST_DCN2_0(2),
476 		MPC_REG_LIST_DCN2_0(3),
477 		MPC_REG_LIST_DCN2_0(4),
478 		MPC_REG_LIST_DCN2_0(5),
479 		MPC_OUT_MUX_REG_LIST_DCN2_0(0),
480 		MPC_OUT_MUX_REG_LIST_DCN2_0(1),
481 		MPC_OUT_MUX_REG_LIST_DCN2_0(2),
482 		MPC_OUT_MUX_REG_LIST_DCN2_0(3),
483 		MPC_OUT_MUX_REG_LIST_DCN2_0(4),
484 		MPC_OUT_MUX_REG_LIST_DCN2_0(5),
485 		MPC_DBG_REG_LIST_DCN2_0()
486 };
487 
488 static const struct dcn20_mpc_shift mpc_shift = {
489 	MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT),
490 	MPC_DEBUG_REG_LIST_SH_DCN20
491 };
492 
493 static const struct dcn20_mpc_mask mpc_mask = {
494 	MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK),
495 	MPC_DEBUG_REG_LIST_MASK_DCN20
496 };
497 
498 #define tg_regs(id)\
499 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
500 
501 
502 static const struct dcn_optc_registers tg_regs[] = {
503 	tg_regs(0),
504 	tg_regs(1),
505 	tg_regs(2),
506 	tg_regs(3),
507 	tg_regs(4),
508 	tg_regs(5)
509 };
510 
511 static const struct dcn_optc_shift tg_shift = {
512 	TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
513 };
514 
515 static const struct dcn_optc_mask tg_mask = {
516 	TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
517 };
518 
519 #define hubp_regs(id)\
520 [id] = {\
521 	HUBP_REG_LIST_DCN20(id)\
522 }
523 
524 static const struct dcn_hubp2_registers hubp_regs[] = {
525 		hubp_regs(0),
526 		hubp_regs(1),
527 		hubp_regs(2),
528 		hubp_regs(3),
529 		hubp_regs(4),
530 		hubp_regs(5)
531 };
532 
533 static const struct dcn_hubp2_shift hubp_shift = {
534 		HUBP_MASK_SH_LIST_DCN20(__SHIFT)
535 };
536 
537 static const struct dcn_hubp2_mask hubp_mask = {
538 		HUBP_MASK_SH_LIST_DCN20(_MASK)
539 };
540 
541 static const struct dcn_hubbub_registers hubbub_reg = {
542 		HUBBUB_REG_LIST_DCN20(0)
543 };
544 
545 static const struct dcn_hubbub_shift hubbub_shift = {
546 		HUBBUB_MASK_SH_LIST_DCN20(__SHIFT)
547 };
548 
549 static const struct dcn_hubbub_mask hubbub_mask = {
550 		HUBBUB_MASK_SH_LIST_DCN20(_MASK)
551 };
552 
553 #define vmid_regs(id)\
554 [id] = {\
555 		DCN20_VMID_REG_LIST(id)\
556 }
557 
558 static const struct dcn_vmid_registers vmid_regs[] = {
559 	vmid_regs(0),
560 	vmid_regs(1),
561 	vmid_regs(2),
562 	vmid_regs(3),
563 	vmid_regs(4),
564 	vmid_regs(5),
565 	vmid_regs(6),
566 	vmid_regs(7),
567 	vmid_regs(8),
568 	vmid_regs(9),
569 	vmid_regs(10),
570 	vmid_regs(11),
571 	vmid_regs(12),
572 	vmid_regs(13),
573 	vmid_regs(14),
574 	vmid_regs(15)
575 };
576 
577 static const struct dcn20_vmid_shift vmid_shifts = {
578 		DCN20_VMID_MASK_SH_LIST(__SHIFT)
579 };
580 
581 static const struct dcn20_vmid_mask vmid_masks = {
582 		DCN20_VMID_MASK_SH_LIST(_MASK)
583 };
584 
585 static const struct dce110_aux_registers_shift aux_shift = {
586 		DCN_AUX_MASK_SH_LIST(__SHIFT)
587 };
588 
589 static const struct dce110_aux_registers_mask aux_mask = {
590 		DCN_AUX_MASK_SH_LIST(_MASK)
591 };
592 
map_transmitter_id_to_phy_instance(enum transmitter transmitter)593 static int map_transmitter_id_to_phy_instance(
594 	enum transmitter transmitter)
595 {
596 	switch (transmitter) {
597 	case TRANSMITTER_UNIPHY_A:
598 		return 0;
599 	break;
600 	case TRANSMITTER_UNIPHY_B:
601 		return 1;
602 	break;
603 	case TRANSMITTER_UNIPHY_C:
604 		return 2;
605 	break;
606 	case TRANSMITTER_UNIPHY_D:
607 		return 3;
608 	break;
609 	case TRANSMITTER_UNIPHY_E:
610 		return 4;
611 	break;
612 	case TRANSMITTER_UNIPHY_F:
613 		return 5;
614 	break;
615 	default:
616 		ASSERT(0);
617 		return 0;
618 	}
619 }
620 
621 #define dsc_regsDCN20(id)\
622 [id] = {\
623 	DSC_REG_LIST_DCN20(id)\
624 }
625 
626 static const struct dcn20_dsc_registers dsc_regs[] = {
627 	dsc_regsDCN20(0),
628 	dsc_regsDCN20(1),
629 	dsc_regsDCN20(2),
630 	dsc_regsDCN20(3),
631 	dsc_regsDCN20(4),
632 	dsc_regsDCN20(5)
633 };
634 
635 static const struct dcn20_dsc_shift dsc_shift = {
636 	DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
637 };
638 
639 static const struct dcn20_dsc_mask dsc_mask = {
640 	DSC_REG_LIST_SH_MASK_DCN20(_MASK)
641 };
642 
643 static const struct dccg_registers dccg_regs = {
644 		DCCG_REG_LIST_DCN2()
645 };
646 
647 static const struct dccg_shift dccg_shift = {
648 		DCCG_MASK_SH_LIST_DCN2(__SHIFT)
649 };
650 
651 static const struct dccg_mask dccg_mask = {
652 		DCCG_MASK_SH_LIST_DCN2(_MASK)
653 };
654 
655 static const struct resource_caps res_cap_nv10 = {
656 		.num_timing_generator = 6,
657 		.num_opp = 6,
658 		.num_video_plane = 6,
659 		.num_audio = 7,
660 		.num_stream_encoder = 6,
661 		.num_pll = 6,
662 		.num_dwb = 1,
663 		.num_ddc = 6,
664 		.num_vmid = 16,
665 		.num_dsc = 6,
666 };
667 
668 static const struct dc_plane_cap plane_cap = {
669 	.type = DC_PLANE_TYPE_DCN_UNIVERSAL,
670 	.per_pixel_alpha = true,
671 
672 	.pixel_format_support = {
673 			.argb8888 = true,
674 			.nv12 = true,
675 			.fp16 = true,
676 			.p010 = true
677 	},
678 
679 	.max_upscale_factor = {
680 			.argb8888 = 16000,
681 			.nv12 = 16000,
682 			.fp16 = 1
683 	},
684 
685 	.max_downscale_factor = {
686 			.argb8888 = 250,
687 			.nv12 = 250,
688 			.fp16 = 1
689 	},
690 	16,
691 	16
692 };
693 static const struct resource_caps res_cap_nv14 = {
694 		.num_timing_generator = 5,
695 		.num_opp = 5,
696 		.num_video_plane = 5,
697 		.num_audio = 6,
698 		.num_stream_encoder = 5,
699 		.num_pll = 5,
700 		.num_dwb = 1,
701 		.num_ddc = 5,
702 		.num_vmid = 16,
703 		.num_dsc = 5,
704 };
705 
706 static const struct dc_debug_options debug_defaults_drv = {
707 		.disable_dmcu = false,
708 		.force_abm_enable = false,
709 		.clock_trace = true,
710 		.disable_pplib_clock_request = true,
711 		.pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
712 		.force_single_disp_pipe_split = false,
713 		.disable_dcc = DCC_ENABLE,
714 		.vsr_support = true,
715 		.performance_trace = false,
716 		.max_downscale_src_width = 5120,/*upto 5K*/
717 		.disable_pplib_wm_range = false,
718 		.scl_reset_length10 = true,
719 		.sanity_checks = false,
720 		.underflow_assert_delay_us = 0xFFFFFFFF,
721 		.enable_legacy_fast_update = true,
722 		.using_dml2 = false,
723 };
724 
dcn20_dpp_destroy(struct dpp ** dpp)725 void dcn20_dpp_destroy(struct dpp **dpp)
726 {
727 	kfree(TO_DCN20_DPP(*dpp));
728 	*dpp = NULL;
729 }
730 
dcn20_dpp_create(struct dc_context * ctx,uint32_t inst)731 struct dpp *dcn20_dpp_create(
732 	struct dc_context *ctx,
733 	uint32_t inst)
734 {
735 	struct dcn20_dpp *dpp =
736 		kzalloc(sizeof(struct dcn20_dpp), GFP_ATOMIC);
737 
738 	if (!dpp)
739 		return NULL;
740 
741 	if (dpp2_construct(dpp, ctx, inst,
742 			&tf_regs[inst], &tf_shift, &tf_mask))
743 		return &dpp->base;
744 
745 	BREAK_TO_DEBUGGER();
746 	kfree(dpp);
747 	return NULL;
748 }
749 
dcn20_ipp_create(struct dc_context * ctx,uint32_t inst)750 struct input_pixel_processor *dcn20_ipp_create(
751 	struct dc_context *ctx, uint32_t inst)
752 {
753 	struct dcn10_ipp *ipp =
754 		kzalloc(sizeof(struct dcn10_ipp), GFP_ATOMIC);
755 
756 	if (!ipp) {
757 		BREAK_TO_DEBUGGER();
758 		return NULL;
759 	}
760 
761 	dcn20_ipp_construct(ipp, ctx, inst,
762 			&ipp_regs[inst], &ipp_shift, &ipp_mask);
763 	return &ipp->base;
764 }
765 
766 
dcn20_opp_create(struct dc_context * ctx,uint32_t inst)767 struct output_pixel_processor *dcn20_opp_create(
768 	struct dc_context *ctx, uint32_t inst)
769 {
770 	struct dcn20_opp *opp =
771 		kzalloc(sizeof(struct dcn20_opp), GFP_ATOMIC);
772 
773 	if (!opp) {
774 		BREAK_TO_DEBUGGER();
775 		return NULL;
776 	}
777 
778 	dcn20_opp_construct(opp, ctx, inst,
779 			&opp_regs[inst], &opp_shift, &opp_mask);
780 	return &opp->base;
781 }
782 
dcn20_aux_engine_create(struct dc_context * ctx,uint32_t inst)783 struct dce_aux *dcn20_aux_engine_create(
784 	struct dc_context *ctx,
785 	uint32_t inst)
786 {
787 	struct aux_engine_dce110 *aux_engine =
788 		kzalloc(sizeof(struct aux_engine_dce110), GFP_ATOMIC);
789 
790 	if (!aux_engine)
791 		return NULL;
792 
793 	dce110_aux_engine_construct(aux_engine, ctx, inst,
794 				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
795 				    &aux_engine_regs[inst],
796 					&aux_mask,
797 					&aux_shift,
798 					ctx->dc->caps.extended_aux_timeout_support);
799 
800 	return &aux_engine->base;
801 }
802 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
803 
804 static const struct dce_i2c_registers i2c_hw_regs[] = {
805 		i2c_inst_regs(1),
806 		i2c_inst_regs(2),
807 		i2c_inst_regs(3),
808 		i2c_inst_regs(4),
809 		i2c_inst_regs(5),
810 		i2c_inst_regs(6),
811 };
812 
813 static const struct dce_i2c_shift i2c_shifts = {
814 		I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
815 };
816 
817 static const struct dce_i2c_mask i2c_masks = {
818 		I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
819 };
820 
dcn20_i2c_hw_create(struct dc_context * ctx,uint32_t inst)821 struct dce_i2c_hw *dcn20_i2c_hw_create(
822 	struct dc_context *ctx,
823 	uint32_t inst)
824 {
825 	struct dce_i2c_hw *dce_i2c_hw =
826 		kzalloc(sizeof(struct dce_i2c_hw), GFP_ATOMIC);
827 
828 	if (!dce_i2c_hw)
829 		return NULL;
830 
831 	dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
832 				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
833 
834 	return dce_i2c_hw;
835 }
dcn20_mpc_create(struct dc_context * ctx)836 struct mpc *dcn20_mpc_create(struct dc_context *ctx)
837 {
838 	struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
839 					  GFP_ATOMIC);
840 
841 	if (!mpc20)
842 		return NULL;
843 
844 	dcn20_mpc_construct(mpc20, ctx,
845 			&mpc_regs,
846 			&mpc_shift,
847 			&mpc_mask,
848 			6);
849 
850 	return &mpc20->base;
851 }
852 
dcn20_hubbub_create(struct dc_context * ctx)853 struct hubbub *dcn20_hubbub_create(struct dc_context *ctx)
854 {
855 	int i;
856 	struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
857 					  GFP_ATOMIC);
858 
859 	if (!hubbub)
860 		return NULL;
861 
862 	hubbub2_construct(hubbub, ctx,
863 			&hubbub_reg,
864 			&hubbub_shift,
865 			&hubbub_mask);
866 
867 	for (i = 0; i < res_cap_nv10.num_vmid; i++) {
868 		struct dcn20_vmid *vmid = &hubbub->vmid[i];
869 
870 		vmid->ctx = ctx;
871 
872 		vmid->regs = &vmid_regs[i];
873 		vmid->shifts = &vmid_shifts;
874 		vmid->masks = &vmid_masks;
875 	}
876 
877 	return &hubbub->base;
878 }
879 
dcn20_timing_generator_create(struct dc_context * ctx,uint32_t instance)880 struct timing_generator *dcn20_timing_generator_create(
881 		struct dc_context *ctx,
882 		uint32_t instance)
883 {
884 	struct optc *tgn10 =
885 		kzalloc(sizeof(struct optc), GFP_ATOMIC);
886 
887 	if (!tgn10)
888 		return NULL;
889 
890 	tgn10->base.inst = instance;
891 	tgn10->base.ctx = ctx;
892 
893 	tgn10->tg_regs = &tg_regs[instance];
894 	tgn10->tg_shift = &tg_shift;
895 	tgn10->tg_mask = &tg_mask;
896 
897 	dcn20_timing_generator_init(tgn10);
898 
899 	return &tgn10->base;
900 }
901 
902 static const struct encoder_feature_support link_enc_feature = {
903 		.max_hdmi_deep_color = COLOR_DEPTH_121212,
904 		.max_hdmi_pixel_clock = 600000,
905 		.hdmi_ycbcr420_supported = true,
906 		.dp_ycbcr420_supported = true,
907 		.fec_supported = true,
908 		.flags.bits.IS_HBR2_CAPABLE = true,
909 		.flags.bits.IS_HBR3_CAPABLE = true,
910 		.flags.bits.IS_TPS3_CAPABLE = true,
911 		.flags.bits.IS_TPS4_CAPABLE = true
912 };
913 
dcn20_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)914 struct link_encoder *dcn20_link_encoder_create(
915 	struct dc_context *ctx,
916 	const struct encoder_init_data *enc_init_data)
917 {
918 	struct dcn20_link_encoder *enc20 =
919 		kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
920 	int link_regs_id;
921 
922 	if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
923 		return NULL;
924 
925 	link_regs_id =
926 		map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
927 
928 	dcn20_link_encoder_construct(enc20,
929 				      enc_init_data,
930 				      &link_enc_feature,
931 				      &link_enc_regs[link_regs_id],
932 				      &link_enc_aux_regs[enc_init_data->channel - 1],
933 				      &link_enc_hpd_regs[enc_init_data->hpd_source],
934 				      &le_shift,
935 				      &le_mask);
936 
937 	return &enc20->enc10.base;
938 }
939 
dcn20_panel_cntl_create(const struct panel_cntl_init_data * init_data)940 static struct panel_cntl *dcn20_panel_cntl_create(const struct panel_cntl_init_data *init_data)
941 {
942 	struct dce_panel_cntl *panel_cntl =
943 		kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
944 
945 	if (!panel_cntl)
946 		return NULL;
947 
948 	dce_panel_cntl_construct(panel_cntl,
949 			init_data,
950 			&panel_cntl_regs[init_data->inst],
951 			&panel_cntl_shift,
952 			&panel_cntl_mask);
953 
954 	return &panel_cntl->base;
955 }
956 
dcn20_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)957 static struct clock_source *dcn20_clock_source_create(
958 	struct dc_context *ctx,
959 	struct dc_bios *bios,
960 	enum clock_source_id id,
961 	const struct dce110_clk_src_regs *regs,
962 	bool dp_clk_src)
963 {
964 	struct dce110_clk_src *clk_src =
965 		kzalloc(sizeof(struct dce110_clk_src), GFP_ATOMIC);
966 
967 	if (!clk_src)
968 		return NULL;
969 
970 	if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
971 			regs, &cs_shift, &cs_mask)) {
972 		clk_src->base.dp_clk_src = dp_clk_src;
973 		return &clk_src->base;
974 	}
975 
976 	kfree(clk_src);
977 	BREAK_TO_DEBUGGER();
978 	return NULL;
979 }
980 
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)981 static void read_dce_straps(
982 	struct dc_context *ctx,
983 	struct resource_straps *straps)
984 {
985 	generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
986 		FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
987 }
988 
dcn20_create_audio(struct dc_context * ctx,unsigned int inst)989 static struct audio *dcn20_create_audio(
990 		struct dc_context *ctx, unsigned int inst)
991 {
992 	return dce_audio_create(ctx, inst,
993 			&audio_regs[inst], &audio_shift, &audio_mask);
994 }
995 
dcn20_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)996 struct stream_encoder *dcn20_stream_encoder_create(
997 	enum engine_id eng_id,
998 	struct dc_context *ctx)
999 {
1000 	struct dcn10_stream_encoder *enc1 =
1001 		kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1002 
1003 	if (!enc1)
1004 		return NULL;
1005 
1006 	if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {
1007 		if (eng_id >= ENGINE_ID_DIGD)
1008 			eng_id++;
1009 	}
1010 
1011 	dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
1012 					&stream_enc_regs[eng_id],
1013 					&se_shift, &se_mask);
1014 
1015 	return &enc1->base;
1016 }
1017 
1018 static const struct dce_hwseq_registers hwseq_reg = {
1019 		HWSEQ_DCN2_REG_LIST()
1020 };
1021 
1022 static const struct dce_hwseq_shift hwseq_shift = {
1023 		HWSEQ_DCN2_MASK_SH_LIST(__SHIFT)
1024 };
1025 
1026 static const struct dce_hwseq_mask hwseq_mask = {
1027 		HWSEQ_DCN2_MASK_SH_LIST(_MASK)
1028 };
1029 
dcn20_hwseq_create(struct dc_context * ctx)1030 struct dce_hwseq *dcn20_hwseq_create(
1031 	struct dc_context *ctx)
1032 {
1033 	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1034 
1035 	if (hws) {
1036 		hws->ctx = ctx;
1037 		hws->regs = &hwseq_reg;
1038 		hws->shifts = &hwseq_shift;
1039 		hws->masks = &hwseq_mask;
1040 	}
1041 	return hws;
1042 }
1043 
1044 static const struct resource_create_funcs res_create_funcs = {
1045 	.read_dce_straps = read_dce_straps,
1046 	.create_audio = dcn20_create_audio,
1047 	.create_stream_encoder = dcn20_stream_encoder_create,
1048 	.create_hwseq = dcn20_hwseq_create,
1049 };
1050 
1051 static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
1052 
dcn20_clock_source_destroy(struct clock_source ** clk_src)1053 void dcn20_clock_source_destroy(struct clock_source **clk_src)
1054 {
1055 	kfree(TO_DCE110_CLK_SRC(*clk_src));
1056 	*clk_src = NULL;
1057 }
1058 
1059 
dcn20_dsc_create(struct dc_context * ctx,uint32_t inst)1060 struct display_stream_compressor *dcn20_dsc_create(
1061 	struct dc_context *ctx, uint32_t inst)
1062 {
1063 	struct dcn20_dsc *dsc =
1064 		kzalloc(sizeof(struct dcn20_dsc), GFP_ATOMIC);
1065 
1066 	if (!dsc) {
1067 		BREAK_TO_DEBUGGER();
1068 		return NULL;
1069 	}
1070 
1071 	dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1072 	return &dsc->base;
1073 }
1074 
dcn20_dsc_destroy(struct display_stream_compressor ** dsc)1075 void dcn20_dsc_destroy(struct display_stream_compressor **dsc)
1076 {
1077 	kfree(container_of(*dsc, struct dcn20_dsc, base));
1078 	*dsc = NULL;
1079 }
1080 
1081 
dcn20_resource_destruct(struct dcn20_resource_pool * pool)1082 static void dcn20_resource_destruct(struct dcn20_resource_pool *pool)
1083 {
1084 	unsigned int i;
1085 
1086 	for (i = 0; i < pool->base.stream_enc_count; i++) {
1087 		if (pool->base.stream_enc[i] != NULL) {
1088 			kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1089 			pool->base.stream_enc[i] = NULL;
1090 		}
1091 	}
1092 
1093 	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1094 		if (pool->base.dscs[i] != NULL)
1095 			dcn20_dsc_destroy(&pool->base.dscs[i]);
1096 	}
1097 
1098 	if (pool->base.mpc != NULL) {
1099 		kfree(TO_DCN20_MPC(pool->base.mpc));
1100 		pool->base.mpc = NULL;
1101 	}
1102 	if (pool->base.hubbub != NULL) {
1103 		kfree(pool->base.hubbub);
1104 		pool->base.hubbub = NULL;
1105 	}
1106 	for (i = 0; i < pool->base.pipe_count; i++) {
1107 		if (pool->base.dpps[i] != NULL)
1108 			dcn20_dpp_destroy(&pool->base.dpps[i]);
1109 
1110 		if (pool->base.ipps[i] != NULL)
1111 			pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1112 
1113 		if (pool->base.hubps[i] != NULL) {
1114 			kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1115 			pool->base.hubps[i] = NULL;
1116 		}
1117 
1118 		if (pool->base.irqs != NULL) {
1119 			dal_irq_service_destroy(&pool->base.irqs);
1120 		}
1121 	}
1122 
1123 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1124 		if (pool->base.engines[i] != NULL)
1125 			dce110_engine_destroy(&pool->base.engines[i]);
1126 		if (pool->base.hw_i2cs[i] != NULL) {
1127 			kfree(pool->base.hw_i2cs[i]);
1128 			pool->base.hw_i2cs[i] = NULL;
1129 		}
1130 		if (pool->base.sw_i2cs[i] != NULL) {
1131 			kfree(pool->base.sw_i2cs[i]);
1132 			pool->base.sw_i2cs[i] = NULL;
1133 		}
1134 	}
1135 
1136 	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1137 		if (pool->base.opps[i] != NULL)
1138 			pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1139 	}
1140 
1141 	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1142 		if (pool->base.timing_generators[i] != NULL)	{
1143 			kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1144 			pool->base.timing_generators[i] = NULL;
1145 		}
1146 	}
1147 
1148 	for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1149 		if (pool->base.dwbc[i] != NULL) {
1150 			kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
1151 			pool->base.dwbc[i] = NULL;
1152 		}
1153 		if (pool->base.mcif_wb[i] != NULL) {
1154 			kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
1155 			pool->base.mcif_wb[i] = NULL;
1156 		}
1157 	}
1158 
1159 	for (i = 0; i < pool->base.audio_count; i++) {
1160 		if (pool->base.audios[i])
1161 			dce_aud_destroy(&pool->base.audios[i]);
1162 	}
1163 
1164 	for (i = 0; i < pool->base.clk_src_count; i++) {
1165 		if (pool->base.clock_sources[i] != NULL) {
1166 			dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1167 			pool->base.clock_sources[i] = NULL;
1168 		}
1169 	}
1170 
1171 	if (pool->base.dp_clock_source != NULL) {
1172 		dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1173 		pool->base.dp_clock_source = NULL;
1174 	}
1175 
1176 
1177 	if (pool->base.abm != NULL)
1178 		dce_abm_destroy(&pool->base.abm);
1179 
1180 	if (pool->base.dmcu != NULL)
1181 		dce_dmcu_destroy(&pool->base.dmcu);
1182 
1183 	if (pool->base.dccg != NULL)
1184 		dcn_dccg_destroy(&pool->base.dccg);
1185 
1186 	if (pool->base.pp_smu != NULL)
1187 		dcn20_pp_smu_destroy(&pool->base.pp_smu);
1188 
1189 	if (pool->base.oem_device != NULL) {
1190 		struct dc *dc = pool->base.oem_device->ctx->dc;
1191 
1192 		dc->link_srv->destroy_ddc_service(&pool->base.oem_device);
1193 	}
1194 }
1195 
dcn20_hubp_create(struct dc_context * ctx,uint32_t inst)1196 struct hubp *dcn20_hubp_create(
1197 	struct dc_context *ctx,
1198 	uint32_t inst)
1199 {
1200 	struct dcn20_hubp *hubp2 =
1201 		kzalloc(sizeof(struct dcn20_hubp), GFP_ATOMIC);
1202 
1203 	if (!hubp2)
1204 		return NULL;
1205 
1206 	if (hubp2_construct(hubp2, ctx, inst,
1207 			&hubp_regs[inst], &hubp_shift, &hubp_mask))
1208 		return &hubp2->base;
1209 
1210 	BREAK_TO_DEBUGGER();
1211 	kfree(hubp2);
1212 	return NULL;
1213 }
1214 
get_pixel_clock_parameters(struct pipe_ctx * pipe_ctx,struct pixel_clk_params * pixel_clk_params)1215 static void get_pixel_clock_parameters(
1216 	struct pipe_ctx *pipe_ctx,
1217 	struct pixel_clk_params *pixel_clk_params)
1218 {
1219 	const struct dc_stream_state *stream = pipe_ctx->stream;
1220 	struct pipe_ctx *odm_pipe;
1221 	int opp_cnt = 1;
1222 	struct dc_link *link = stream->link;
1223 	struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;
1224 	struct dc *dc = pipe_ctx->stream->ctx->dc;
1225 	struct dce_hwseq *hws = dc->hwseq;
1226 
1227 	for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1228 		opp_cnt++;
1229 
1230 	pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
1231 
1232 	if (!dc->config.unify_link_enc_assignment)
1233 		link_enc = link_enc_cfg_get_link_enc(link);
1234 	if (link_enc)
1235 		pixel_clk_params->encoder_object_id = link_enc->id;
1236 
1237 	pixel_clk_params->signal_type = pipe_ctx->stream->signal;
1238 	pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1239 	/* TODO: un-hardcode*/
1240 	/* TODO - DP2.0 HW: calculate requested_sym_clk for UHBR rates */
1241 	pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
1242 		LINK_RATE_REF_FREQ_IN_KHZ;
1243 	pixel_clk_params->flags.ENABLE_SS = 0;
1244 	pixel_clk_params->color_depth =
1245 		stream->timing.display_color_depth;
1246 	pixel_clk_params->flags.DISPLAY_BLANKED = 1;
1247 	pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
1248 
1249 	if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1250 		pixel_clk_params->color_depth = COLOR_DEPTH_888;
1251 
1252 	if (opp_cnt == 4)
1253 		pixel_clk_params->requested_pix_clk_100hz /= 4;
1254 	else if (pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing) || opp_cnt == 2)
1255 		pixel_clk_params->requested_pix_clk_100hz /= 2;
1256 	else if (hws->funcs.is_dp_dig_pixel_rate_div_policy) {
1257 		if (hws->funcs.is_dp_dig_pixel_rate_div_policy(pipe_ctx))
1258 			pixel_clk_params->requested_pix_clk_100hz /= 2;
1259 	}
1260 
1261 	if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1262 		pixel_clk_params->requested_pix_clk_100hz *= 2;
1263 
1264 	if ((pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container &&
1265 			pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&pipe_ctx->stream->timing)) ||
1266 			(hws->funcs.is_dp_dig_pixel_rate_div_policy &&
1267 			hws->funcs.is_dp_dig_pixel_rate_div_policy(pipe_ctx)) ||
1268 			opp_cnt > 1) {
1269 		pixel_clk_params->dio_se_pix_per_cycle = 2;
1270 	} else {
1271 		pixel_clk_params->dio_se_pix_per_cycle = 1;
1272 	}
1273 }
1274 
build_clamping_params(struct dc_stream_state * stream)1275 static void build_clamping_params(struct dc_stream_state *stream)
1276 {
1277 	stream->clamping.clamping_level = CLAMPING_FULL_RANGE;
1278 	stream->clamping.c_depth = stream->timing.display_color_depth;
1279 	stream->clamping.pixel_encoding = stream->timing.pixel_encoding;
1280 }
1281 
dcn20_build_pipe_pix_clk_params(struct pipe_ctx * pipe_ctx)1282 void dcn20_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx)
1283 {
1284 	get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
1285 	pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
1286 			pipe_ctx->clock_source,
1287 			&pipe_ctx->stream_res.pix_clk_params,
1288 			&pipe_ctx->pll_settings);
1289 }
1290 
build_pipe_hw_param(struct pipe_ctx * pipe_ctx)1291 static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
1292 {
1293 	struct resource_pool *pool = pipe_ctx->stream->ctx->dc->res_pool;
1294 
1295 	if (pool->funcs->build_pipe_pix_clk_params) {
1296 		pool->funcs->build_pipe_pix_clk_params(pipe_ctx);
1297 	} else {
1298 		dcn20_build_pipe_pix_clk_params(pipe_ctx);
1299 	}
1300 
1301 	pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
1302 
1303 	resource_build_bit_depth_reduction_params(pipe_ctx->stream,
1304 					&pipe_ctx->stream->bit_depth_params);
1305 	build_clamping_params(pipe_ctx->stream);
1306 
1307 	return DC_OK;
1308 }
1309 
dcn20_build_mapped_resource(const struct dc * dc,struct dc_state * context,struct dc_stream_state * stream)1310 enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream)
1311 {
1312 	enum dc_status status = DC_OK;
1313 	struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);
1314 
1315 	if (!pipe_ctx)
1316 		return DC_ERROR_UNEXPECTED;
1317 
1318 
1319 	status = build_pipe_hw_param(pipe_ctx);
1320 
1321 	return status;
1322 }
1323 
1324 
dcn20_acquire_dsc(const struct dc * dc,struct resource_context * res_ctx,struct display_stream_compressor ** dsc,int pipe_idx)1325 void dcn20_acquire_dsc(const struct dc *dc,
1326 			struct resource_context *res_ctx,
1327 			struct display_stream_compressor **dsc,
1328 			int pipe_idx)
1329 {
1330 	int i;
1331 	const struct resource_pool *pool = dc->res_pool;
1332 	struct display_stream_compressor *dsc_old = dc->current_state->res_ctx.pipe_ctx[pipe_idx].stream_res.dsc;
1333 
1334 	ASSERT(*dsc == NULL); /* If this ASSERT fails, dsc was not released properly */
1335 	*dsc = NULL;
1336 
1337 	/* Always do 1-to-1 mapping when number of DSCs is same as number of pipes */
1338 	if (pool->res_cap->num_dsc == pool->res_cap->num_opp) {
1339 		*dsc = pool->dscs[pipe_idx];
1340 		res_ctx->is_dsc_acquired[pipe_idx] = true;
1341 		return;
1342 	}
1343 
1344 	/* Return old DSC to avoid the need for re-programming */
1345 	if (dsc_old && !res_ctx->is_dsc_acquired[dsc_old->inst]) {
1346 		*dsc = dsc_old;
1347 		res_ctx->is_dsc_acquired[dsc_old->inst] = true;
1348 		return ;
1349 	}
1350 
1351 	/* Find first free DSC */
1352 	for (i = 0; i < pool->res_cap->num_dsc; i++)
1353 		if (!res_ctx->is_dsc_acquired[i]) {
1354 			*dsc = pool->dscs[i];
1355 			res_ctx->is_dsc_acquired[i] = true;
1356 			break;
1357 		}
1358 }
1359 
dcn20_release_dsc(struct resource_context * res_ctx,const struct resource_pool * pool,struct display_stream_compressor ** dsc)1360 void dcn20_release_dsc(struct resource_context *res_ctx,
1361 			const struct resource_pool *pool,
1362 			struct display_stream_compressor **dsc)
1363 {
1364 	int i;
1365 
1366 	for (i = 0; i < pool->res_cap->num_dsc; i++)
1367 		if (pool->dscs[i] == *dsc) {
1368 			res_ctx->is_dsc_acquired[i] = false;
1369 			*dsc = NULL;
1370 			break;
1371 		}
1372 }
1373 
1374 
1375 
dcn20_add_dsc_to_stream_resource(struct dc * dc,struct dc_state * dc_ctx,struct dc_stream_state * dc_stream)1376 enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc,
1377 		struct dc_state *dc_ctx,
1378 		struct dc_stream_state *dc_stream)
1379 {
1380 	enum dc_status result = DC_OK;
1381 	int i;
1382 
1383 	/* Get a DSC if required and available */
1384 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
1385 		struct pipe_ctx *pipe_ctx = &dc_ctx->res_ctx.pipe_ctx[i];
1386 
1387 		if (pipe_ctx->top_pipe)
1388 			continue;
1389 
1390 		if (pipe_ctx->stream != dc_stream)
1391 			continue;
1392 
1393 		if (pipe_ctx->stream_res.dsc)
1394 			continue;
1395 
1396 		dcn20_acquire_dsc(dc, &dc_ctx->res_ctx, &pipe_ctx->stream_res.dsc, i);
1397 
1398 		/* The number of DSCs can be less than the number of pipes */
1399 		if (!pipe_ctx->stream_res.dsc) {
1400 			result = DC_NO_DSC_RESOURCE;
1401 		}
1402 
1403 		break;
1404 	}
1405 
1406 	return result;
1407 }
1408 
1409 
remove_dsc_from_stream_resource(struct dc * dc,struct dc_state * new_ctx,struct dc_stream_state * dc_stream)1410 static enum dc_status remove_dsc_from_stream_resource(struct dc *dc,
1411 		struct dc_state *new_ctx,
1412 		struct dc_stream_state *dc_stream)
1413 {
1414 	struct pipe_ctx *pipe_ctx = NULL;
1415 	int i;
1416 
1417 	for (i = 0; i < MAX_PIPES; i++) {
1418 		if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
1419 			pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
1420 
1421 			if (pipe_ctx->stream_res.dsc)
1422 				dcn20_release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc);
1423 		}
1424 	}
1425 
1426 	if (!pipe_ctx)
1427 		return DC_ERROR_UNEXPECTED;
1428 	else
1429 		return DC_OK;
1430 }
1431 
1432 
dcn20_add_stream_to_ctx(struct dc * dc,struct dc_state * new_ctx,struct dc_stream_state * dc_stream)1433 enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1434 {
1435 	enum dc_status result = DC_ERROR_UNEXPECTED;
1436 
1437 	result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1438 
1439 	if (result == DC_OK)
1440 		result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
1441 
1442 	/* Get a DSC if required and available */
1443 	if (result == DC_OK && dc_stream->timing.flags.DSC)
1444 		result = dcn20_add_dsc_to_stream_resource(dc, new_ctx, dc_stream);
1445 
1446 	if (result == DC_OK)
1447 		result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream);
1448 
1449 	return result;
1450 }
1451 
1452 
dcn20_remove_stream_from_ctx(struct dc * dc,struct dc_state * new_ctx,struct dc_stream_state * dc_stream)1453 enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1454 {
1455 	enum dc_status result = DC_OK;
1456 
1457 	result = remove_dsc_from_stream_resource(dc, new_ctx, dc_stream);
1458 
1459 	return result;
1460 }
1461 
1462 /**
1463  * dcn20_split_stream_for_odm - Check if stream can be splited for ODM
1464  *
1465  * @dc: DC object with resource pool info required for pipe split
1466  * @res_ctx: Persistent state of resources
1467  * @prev_odm_pipe: Reference to the previous ODM pipe
1468  * @next_odm_pipe: Reference to the next ODM pipe
1469  *
1470  * This function takes a logically active pipe and a logically free pipe and
1471  * halves all the scaling parameters that need to be halved while populating
1472  * the free pipe with the required resources and configuring the next/previous
1473  * ODM pipe pointers.
1474  *
1475  * Return:
1476  * Return true if split stream for ODM is possible, otherwise, return false.
1477  */
dcn20_split_stream_for_odm(const struct dc * dc,struct resource_context * res_ctx,struct pipe_ctx * prev_odm_pipe,struct pipe_ctx * next_odm_pipe)1478 bool dcn20_split_stream_for_odm(
1479 		const struct dc *dc,
1480 		struct resource_context *res_ctx,
1481 		struct pipe_ctx *prev_odm_pipe,
1482 		struct pipe_ctx *next_odm_pipe)
1483 {
1484 	int pipe_idx = next_odm_pipe->pipe_idx;
1485 	const struct resource_pool *pool = dc->res_pool;
1486 
1487 	*next_odm_pipe = *prev_odm_pipe;
1488 
1489 	next_odm_pipe->pipe_idx = pipe_idx;
1490 	next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx];
1491 	next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx];
1492 	next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx];
1493 	next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx];
1494 	next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx];
1495 	next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst;
1496 	next_odm_pipe->stream_res.dsc = NULL;
1497 	if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) {
1498 		next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe;
1499 		next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe;
1500 	}
1501 	if (prev_odm_pipe->top_pipe && prev_odm_pipe->top_pipe->next_odm_pipe) {
1502 		prev_odm_pipe->top_pipe->next_odm_pipe->bottom_pipe = next_odm_pipe;
1503 		next_odm_pipe->top_pipe = prev_odm_pipe->top_pipe->next_odm_pipe;
1504 	}
1505 	if (prev_odm_pipe->bottom_pipe && prev_odm_pipe->bottom_pipe->next_odm_pipe) {
1506 		prev_odm_pipe->bottom_pipe->next_odm_pipe->top_pipe = next_odm_pipe;
1507 		next_odm_pipe->bottom_pipe = prev_odm_pipe->bottom_pipe->next_odm_pipe;
1508 	}
1509 	prev_odm_pipe->next_odm_pipe = next_odm_pipe;
1510 	next_odm_pipe->prev_odm_pipe = prev_odm_pipe;
1511 
1512 	if (prev_odm_pipe->plane_state) {
1513 		if (!resource_build_scaling_params(prev_odm_pipe) ||
1514 			!resource_build_scaling_params(next_odm_pipe)) {
1515 				return false;
1516 		}
1517 	}
1518 
1519 	if (!next_odm_pipe->top_pipe)
1520 		next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx];
1521 	else
1522 		next_odm_pipe->stream_res.opp = next_odm_pipe->top_pipe->stream_res.opp;
1523 	if (next_odm_pipe->stream->timing.flags.DSC == 1 && !next_odm_pipe->top_pipe) {
1524 		dcn20_acquire_dsc(dc, res_ctx, &next_odm_pipe->stream_res.dsc, next_odm_pipe->pipe_idx);
1525 		ASSERT(next_odm_pipe->stream_res.dsc);
1526 		if (next_odm_pipe->stream_res.dsc == NULL)
1527 			return false;
1528 	}
1529 
1530 	return true;
1531 }
1532 
dcn20_split_stream_for_mpc(struct resource_context * res_ctx,const struct resource_pool * pool,struct pipe_ctx * primary_pipe,struct pipe_ctx * secondary_pipe)1533 void dcn20_split_stream_for_mpc(
1534 		struct resource_context *res_ctx,
1535 		const struct resource_pool *pool,
1536 		struct pipe_ctx *primary_pipe,
1537 		struct pipe_ctx *secondary_pipe)
1538 {
1539 	int pipe_idx = secondary_pipe->pipe_idx;
1540 	struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe;
1541 
1542 	*secondary_pipe = *primary_pipe;
1543 	secondary_pipe->bottom_pipe = sec_bot_pipe;
1544 
1545 	secondary_pipe->pipe_idx = pipe_idx;
1546 	secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];
1547 	secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];
1548 	secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];
1549 	secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];
1550 	secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
1551 	secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
1552 	secondary_pipe->stream_res.dsc = NULL;
1553 	if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) {
1554 		ASSERT(!secondary_pipe->bottom_pipe);
1555 		secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe;
1556 		secondary_pipe->bottom_pipe->top_pipe = secondary_pipe;
1557 	}
1558 	primary_pipe->bottom_pipe = secondary_pipe;
1559 	secondary_pipe->top_pipe = primary_pipe;
1560 
1561 	ASSERT(primary_pipe->plane_state);
1562 }
1563 
dcn20_calc_max_scaled_time(unsigned int time_per_pixel,enum mmhubbub_wbif_mode mode,unsigned int urgent_watermark)1564 unsigned int dcn20_calc_max_scaled_time(
1565 		unsigned int time_per_pixel,
1566 		enum mmhubbub_wbif_mode mode,
1567 		unsigned int urgent_watermark)
1568 {
1569 	unsigned int time_per_byte = 0;
1570 	unsigned int total_y_free_entry = 0x200; /* two memory piece for luma */
1571 	unsigned int total_c_free_entry = 0x140; /* two memory piece for chroma */
1572 	unsigned int small_free_entry, max_free_entry;
1573 	unsigned int buf_lh_capability;
1574 	unsigned int max_scaled_time;
1575 
1576 	if (mode == PACKED_444) /* packed mode */
1577 		time_per_byte = time_per_pixel/4;
1578 	else if (mode == PLANAR_420_8BPC)
1579 		time_per_byte  = time_per_pixel;
1580 	else if (mode == PLANAR_420_10BPC) /* p010 */
1581 		time_per_byte  = time_per_pixel * 819/1024;
1582 
1583 	if (time_per_byte == 0)
1584 		time_per_byte = 1;
1585 
1586 	small_free_entry  = total_c_free_entry;
1587 	max_free_entry    = (mode == PACKED_444) ? total_y_free_entry + total_c_free_entry : small_free_entry;
1588 	buf_lh_capability = max_free_entry*time_per_byte*32/16; /* there is 4bit fraction */
1589 	max_scaled_time   = buf_lh_capability - urgent_watermark;
1590 	return max_scaled_time;
1591 }
1592 
dcn20_set_mcif_arb_params(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt)1593 void dcn20_set_mcif_arb_params(
1594 		struct dc *dc,
1595 		struct dc_state *context,
1596 		display_e2e_pipe_params_st *pipes,
1597 		int pipe_cnt)
1598 {
1599 	enum mmhubbub_wbif_mode wbif_mode;
1600 	struct mcif_arb_params *wb_arb_params;
1601 	int i, j, dwb_pipe;
1602 
1603 	/* Writeback MCIF_WB arbitration parameters */
1604 	dwb_pipe = 0;
1605 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
1606 
1607 		if (!context->res_ctx.pipe_ctx[i].stream)
1608 			continue;
1609 
1610 		for (j = 0; j < MAX_DWB_PIPES; j++) {
1611 			if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].wb_enabled == false)
1612 				continue;
1613 
1614 			//wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params;
1615 			wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];
1616 
1617 			if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.out_format == dwb_scaler_mode_yuv420) {
1618 				if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
1619 					wbif_mode = PLANAR_420_8BPC;
1620 				else
1621 					wbif_mode = PLANAR_420_10BPC;
1622 			} else
1623 				wbif_mode = PACKED_444;
1624 
1625 			DC_FP_START();
1626 			dcn20_fpu_set_wb_arb_params(wb_arb_params, context, pipes, pipe_cnt, i);
1627 			DC_FP_END();
1628 
1629 			wb_arb_params->slice_lines = 32;
1630 			wb_arb_params->arbitration_slice = 2;
1631 			wb_arb_params->max_scaled_time = dcn20_calc_max_scaled_time(wb_arb_params->time_per_pixel,
1632 				wbif_mode,
1633 				wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */
1634 
1635 			dwb_pipe++;
1636 
1637 			if (dwb_pipe >= MAX_DWB_PIPES)
1638 				return;
1639 		}
1640 	}
1641 }
1642 
dcn20_validate_dsc(struct dc * dc,struct dc_state * new_ctx)1643 bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
1644 {
1645 	int i;
1646 
1647 	/* Validate DSC config, dsc count validation is already done */
1648 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
1649 		struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
1650 		struct dc_stream_state *stream = pipe_ctx->stream;
1651 		struct dsc_config dsc_cfg;
1652 		struct pipe_ctx *odm_pipe;
1653 		int opp_cnt = 1;
1654 
1655 		for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1656 			opp_cnt++;
1657 
1658 		/* Only need to validate top pipe */
1659 		if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC)
1660 			continue;
1661 
1662 		dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left
1663 				+ stream->timing.h_border_right) / opp_cnt;
1664 		dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top
1665 				+ stream->timing.v_border_bottom;
1666 		dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
1667 		dsc_cfg.color_depth = stream->timing.display_color_depth;
1668 		dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
1669 		dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
1670 		dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
1671 
1672 		if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg))
1673 			return false;
1674 	}
1675 	return true;
1676 }
1677 
dcn20_find_secondary_pipe(struct dc * dc,struct resource_context * res_ctx,const struct resource_pool * pool,const struct pipe_ctx * primary_pipe)1678 struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
1679 		struct resource_context *res_ctx,
1680 		const struct resource_pool *pool,
1681 		const struct pipe_ctx *primary_pipe)
1682 {
1683 	struct pipe_ctx *secondary_pipe = NULL;
1684 
1685 	if (dc && primary_pipe) {
1686 		int j;
1687 		int preferred_pipe_idx = 0;
1688 
1689 		/* first check the prev dc state:
1690 		 * if this primary pipe has a bottom pipe in prev. state
1691 		 * and if the bottom pipe is still available (which it should be),
1692 		 * pick that pipe as secondary
1693 		 * Same logic applies for ODM pipes
1694 		 */
1695 		if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe) {
1696 			preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx;
1697 			if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
1698 				secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
1699 				secondary_pipe->pipe_idx = preferred_pipe_idx;
1700 			}
1701 		}
1702 		if (secondary_pipe == NULL &&
1703 				dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe) {
1704 			preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx;
1705 			if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
1706 				secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
1707 				secondary_pipe->pipe_idx = preferred_pipe_idx;
1708 			}
1709 		}
1710 
1711 		/*
1712 		 * if this primary pipe does not have a bottom pipe in prev. state
1713 		 * start backward and find a pipe that did not used to be a bottom pipe in
1714 		 * prev. dc state. This way we make sure we keep the same assignment as
1715 		 * last state and will not have to reprogram every pipe
1716 		 */
1717 		if (secondary_pipe == NULL) {
1718 			for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
1719 				if (dc->current_state->res_ctx.pipe_ctx[j].top_pipe == NULL
1720 						&& dc->current_state->res_ctx.pipe_ctx[j].prev_odm_pipe == NULL) {
1721 					preferred_pipe_idx = j;
1722 
1723 					if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
1724 						secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
1725 						secondary_pipe->pipe_idx = preferred_pipe_idx;
1726 						break;
1727 					}
1728 				}
1729 			}
1730 		}
1731 		/*
1732 		 * We should never hit this assert unless assignments are shuffled around
1733 		 * if this happens we will prob. hit a vsync tdr
1734 		 */
1735 		ASSERT(secondary_pipe);
1736 		/*
1737 		 * search backwards for the second pipe to keep pipe
1738 		 * assignment more consistent
1739 		 */
1740 		if (secondary_pipe == NULL) {
1741 			for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
1742 				preferred_pipe_idx = j;
1743 
1744 				if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
1745 					secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
1746 					secondary_pipe->pipe_idx = preferred_pipe_idx;
1747 					break;
1748 				}
1749 			}
1750 		}
1751 	}
1752 
1753 	return secondary_pipe;
1754 }
1755 
dcn20_merge_pipes_for_validate(struct dc * dc,struct dc_state * context)1756 void dcn20_merge_pipes_for_validate(
1757 		struct dc *dc,
1758 		struct dc_state *context)
1759 {
1760 	int i;
1761 
1762 	/* merge previously split odm pipes since mode support needs to make the decision */
1763 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
1764 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1765 		struct pipe_ctx *odm_pipe = pipe->next_odm_pipe;
1766 
1767 		if (pipe->prev_odm_pipe)
1768 			continue;
1769 
1770 		pipe->next_odm_pipe = NULL;
1771 		while (odm_pipe) {
1772 			struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;
1773 
1774 			odm_pipe->plane_state = NULL;
1775 			odm_pipe->stream = NULL;
1776 			odm_pipe->top_pipe = NULL;
1777 			odm_pipe->bottom_pipe = NULL;
1778 			odm_pipe->prev_odm_pipe = NULL;
1779 			odm_pipe->next_odm_pipe = NULL;
1780 			if (odm_pipe->stream_res.dsc)
1781 				dcn20_release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc);
1782 			/* Clear plane_res and stream_res */
1783 			memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res));
1784 			memset(&odm_pipe->stream_res, 0, sizeof(odm_pipe->stream_res));
1785 			odm_pipe = next_odm_pipe;
1786 		}
1787 		if (pipe->plane_state)
1788 			resource_build_scaling_params(pipe);
1789 	}
1790 
1791 	/* merge previously mpc split pipes since mode support needs to make the decision */
1792 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
1793 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1794 		struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
1795 
1796 		if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state)
1797 			continue;
1798 
1799 		pipe->bottom_pipe = hsplit_pipe->bottom_pipe;
1800 		if (hsplit_pipe->bottom_pipe)
1801 			hsplit_pipe->bottom_pipe->top_pipe = pipe;
1802 		hsplit_pipe->plane_state = NULL;
1803 		hsplit_pipe->stream = NULL;
1804 		hsplit_pipe->top_pipe = NULL;
1805 		hsplit_pipe->bottom_pipe = NULL;
1806 
1807 		/* Clear plane_res and stream_res */
1808 		memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res));
1809 		memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res));
1810 		if (pipe->plane_state)
1811 			resource_build_scaling_params(pipe);
1812 	}
1813 }
1814 
dcn20_validate_apply_pipe_split_flags(struct dc * dc,struct dc_state * context,int vlevel,int * split,bool * merge)1815 int dcn20_validate_apply_pipe_split_flags(
1816 		struct dc *dc,
1817 		struct dc_state *context,
1818 		int vlevel,
1819 		int *split,
1820 		bool *merge)
1821 {
1822 	int i, pipe_idx, vlevel_split;
1823 	int plane_count = 0;
1824 	bool force_split = false;
1825 	bool avoid_split = dc->debug.pipe_split_policy == MPC_SPLIT_AVOID;
1826 	struct vba_vars_st *v = &context->bw_ctx.dml.vba;
1827 	int max_mpc_comb = v->maxMpcComb;
1828 
1829 	if (context->stream_count > 1) {
1830 		if (dc->debug.pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP)
1831 			avoid_split = true;
1832 	} else if (dc->debug.force_single_disp_pipe_split)
1833 			force_split = true;
1834 
1835 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
1836 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1837 
1838 		/**
1839 		 * Workaround for avoiding pipe-split in cases where we'd split
1840 		 * planes that are too small, resulting in splits that aren't
1841 		 * valid for the scaler.
1842 		 */
1843 		if (pipe->plane_state &&
1844 		    (pipe->plane_state->dst_rect.width <= 16 ||
1845 		     pipe->plane_state->dst_rect.height <= 16 ||
1846 		     pipe->plane_state->src_rect.width <= 16 ||
1847 		     pipe->plane_state->src_rect.height <= 16))
1848 			avoid_split = true;
1849 
1850 		/* TODO: fix dc bugs and remove this split threshold thing */
1851 		if (pipe->stream && !pipe->prev_odm_pipe &&
1852 				(!pipe->top_pipe || pipe->top_pipe->plane_state != pipe->plane_state))
1853 			++plane_count;
1854 	}
1855 	if (plane_count > dc->res_pool->pipe_count / 2)
1856 		avoid_split = true;
1857 
1858 	/* W/A: Mode timing with borders may not work well with pipe split, avoid for this corner case */
1859 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
1860 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1861 		struct dc_crtc_timing timing;
1862 
1863 		if (!pipe->stream)
1864 			continue;
1865 		else {
1866 			timing = pipe->stream->timing;
1867 			if (timing.h_border_left + timing.h_border_right
1868 					+ timing.v_border_top + timing.v_border_bottom > 0) {
1869 				avoid_split = true;
1870 				break;
1871 			}
1872 		}
1873 	}
1874 
1875 	/* Avoid split loop looks for lowest voltage level that allows most unsplit pipes possible */
1876 	if (avoid_split) {
1877 		for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1878 			if (!context->res_ctx.pipe_ctx[i].stream)
1879 				continue;
1880 
1881 			for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++)
1882 				if (v->NoOfDPP[vlevel][0][pipe_idx] == 1 &&
1883 						v->ModeSupport[vlevel][0])
1884 					break;
1885 			/* Impossible to not split this pipe */
1886 			if (vlevel > context->bw_ctx.dml.soc.num_states)
1887 				vlevel = vlevel_split;
1888 			else
1889 				max_mpc_comb = 0;
1890 			pipe_idx++;
1891 		}
1892 		v->maxMpcComb = max_mpc_comb;
1893 	}
1894 
1895 	/* Split loop sets which pipe should be split based on dml outputs and dc flags */
1896 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1897 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1898 		int pipe_plane = v->pipe_plane[pipe_idx];
1899 		bool split4mpc = context->stream_count == 1 && plane_count == 1
1900 				&& dc->config.enable_4to1MPC && dc->res_pool->pipe_count >= 4;
1901 
1902 		if (!context->res_ctx.pipe_ctx[i].stream)
1903 			continue;
1904 
1905 		if (split4mpc || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 4)
1906 			split[i] = 4;
1907 		else if (force_split || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 2)
1908 				split[i] = 2;
1909 
1910 		if ((pipe->stream->view_format ==
1911 				VIEW_3D_FORMAT_SIDE_BY_SIDE ||
1912 				pipe->stream->view_format ==
1913 				VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&
1914 				(pipe->stream->timing.timing_3d_format ==
1915 				TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
1916 				 pipe->stream->timing.timing_3d_format ==
1917 				TIMING_3D_FORMAT_SIDE_BY_SIDE))
1918 			split[i] = 2;
1919 		if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) {
1920 			split[i] = 2;
1921 			v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_2to1;
1922 		}
1923 		if (dc->debug.force_odm_combine_4to1 & (1 << pipe->stream_res.tg->inst)) {
1924 			split[i] = 4;
1925 			v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_4to1;
1926 		}
1927 		/*420 format workaround*/
1928 		if (pipe->stream->timing.h_addressable > 7680 &&
1929 				pipe->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
1930 			split[i] = 4;
1931 		}
1932 		v->ODMCombineEnabled[pipe_plane] =
1933 			v->ODMCombineEnablePerState[vlevel][pipe_plane];
1934 
1935 		if (v->ODMCombineEnabled[pipe_plane] == dm_odm_combine_mode_disabled) {
1936 			if (resource_get_mpc_slice_count(pipe) == 2) {
1937 				/*If need split for mpc but 2 way split already*/
1938 				if (split[i] == 4)
1939 					split[i] = 2; /* 2 -> 4 MPC */
1940 				else if (split[i] == 2)
1941 					split[i] = 0; /* 2 -> 2 MPC */
1942 				else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)
1943 					merge[i] = true; /* 2 -> 1 MPC */
1944 			} else if (resource_get_mpc_slice_count(pipe) == 4) {
1945 				/*If need split for mpc but 4 way split already*/
1946 				if (split[i] == 2 && ((pipe->top_pipe && !pipe->top_pipe->top_pipe)
1947 						|| !pipe->bottom_pipe)) {
1948 					merge[i] = true; /* 4 -> 2 MPC */
1949 				} else if (split[i] == 0 && pipe->top_pipe &&
1950 						pipe->top_pipe->plane_state == pipe->plane_state)
1951 					merge[i] = true; /* 4 -> 1 MPC */
1952 				split[i] = 0;
1953 			} else if (resource_get_odm_slice_count(pipe) > 1) {
1954 				/* ODM -> MPC transition */
1955 				if (pipe->prev_odm_pipe) {
1956 					split[i] = 0;
1957 					merge[i] = true;
1958 				}
1959 			}
1960 		} else {
1961 			if (resource_get_odm_slice_count(pipe) == 2) {
1962 				/*If need split for odm but 2 way split already*/
1963 				if (split[i] == 4)
1964 					split[i] = 2; /* 2 -> 4 ODM */
1965 				else if (split[i] == 2)
1966 					split[i] = 0; /* 2 -> 2 ODM */
1967 				else if (pipe->prev_odm_pipe) {
1968 					ASSERT(0); /* NOT expected yet */
1969 					merge[i] = true; /* exit ODM */
1970 				}
1971 			} else if (resource_get_odm_slice_count(pipe) == 4) {
1972 				/*If need split for odm but 4 way split already*/
1973 				if (split[i] == 2 && ((pipe->prev_odm_pipe && !pipe->prev_odm_pipe->prev_odm_pipe)
1974 						|| !pipe->next_odm_pipe)) {
1975 					merge[i] = true; /* 4 -> 2 ODM */
1976 				} else if (split[i] == 0 && pipe->prev_odm_pipe) {
1977 					ASSERT(0); /* NOT expected yet */
1978 					merge[i] = true; /* exit ODM */
1979 				}
1980 				split[i] = 0;
1981 			} else if (resource_get_mpc_slice_count(pipe) > 1) {
1982 				/* MPC -> ODM transition */
1983 				ASSERT(0); /* NOT expected yet */
1984 				if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {
1985 					split[i] = 0;
1986 					merge[i] = true;
1987 				}
1988 			}
1989 		}
1990 
1991 		/* Adjust dppclk when split is forced, do not bother with dispclk */
1992 		if (split[i] != 0 && v->NoOfDPP[vlevel][max_mpc_comb][pipe_idx] == 1) {
1993 			DC_FP_START();
1994 			dcn20_fpu_adjust_dppclk(v, vlevel, max_mpc_comb, pipe_idx, false);
1995 			DC_FP_END();
1996 		}
1997 		pipe_idx++;
1998 	}
1999 
2000 	return vlevel;
2001 }
2002 
dcn20_fast_validate_bw(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int * pipe_cnt_out,int * pipe_split_from,int * vlevel_out,bool fast_validate)2003 bool dcn20_fast_validate_bw(
2004 		struct dc *dc,
2005 		struct dc_state *context,
2006 		display_e2e_pipe_params_st *pipes,
2007 		int *pipe_cnt_out,
2008 		int *pipe_split_from,
2009 		int *vlevel_out,
2010 		bool fast_validate)
2011 {
2012 	bool out = false;
2013 	int split[MAX_PIPES] = { 0 };
2014 	bool merge[MAX_PIPES] = { false };
2015 	int pipe_cnt, i, pipe_idx, vlevel;
2016 
2017 	ASSERT(pipes);
2018 	if (!pipes)
2019 		return false;
2020 
2021 	dcn20_merge_pipes_for_validate(dc, context);
2022 
2023 	DC_FP_START();
2024 	pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
2025 	DC_FP_END();
2026 
2027 	*pipe_cnt_out = pipe_cnt;
2028 
2029 	if (!pipe_cnt) {
2030 		out = true;
2031 		goto validate_out;
2032 	}
2033 
2034 	vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
2035 
2036 	if (vlevel > context->bw_ctx.dml.soc.num_states)
2037 		goto validate_fail;
2038 
2039 	vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
2040 
2041 	/*initialize pipe_just_split_from to invalid idx*/
2042 	for (i = 0; i < MAX_PIPES; i++)
2043 		pipe_split_from[i] = -1;
2044 
2045 	for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
2046 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2047 		struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
2048 
2049 		if (!pipe->stream || pipe_split_from[i] >= 0)
2050 			continue;
2051 
2052 		pipe_idx++;
2053 
2054 		if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
2055 			hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
2056 			ASSERT(hsplit_pipe);
2057 			if (!dcn20_split_stream_for_odm(
2058 					dc, &context->res_ctx,
2059 					pipe, hsplit_pipe))
2060 				goto validate_fail;
2061 			pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2062 			dcn20_build_mapped_resource(dc, context, pipe->stream);
2063 		}
2064 
2065 		if (!pipe->plane_state)
2066 			continue;
2067 		/* Skip 2nd half of already split pipe */
2068 		if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)
2069 			continue;
2070 
2071 		/* We do not support mpo + odm at the moment */
2072 		if (hsplit_pipe && hsplit_pipe->plane_state != pipe->plane_state
2073 				&& context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx])
2074 			goto validate_fail;
2075 
2076 		if (split[i] == 2) {
2077 			if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {
2078 				/* pipe not split previously needs split */
2079 				hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
2080 				ASSERT(hsplit_pipe);
2081 				if (!hsplit_pipe) {
2082 					DC_FP_START();
2083 					dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe_idx, true);
2084 					DC_FP_END();
2085 					continue;
2086 				}
2087 				if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
2088 					if (!dcn20_split_stream_for_odm(
2089 							dc, &context->res_ctx,
2090 							pipe, hsplit_pipe))
2091 						goto validate_fail;
2092 					dcn20_build_mapped_resource(dc, context, pipe->stream);
2093 				} else {
2094 					dcn20_split_stream_for_mpc(
2095 							&context->res_ctx, dc->res_pool,
2096 							pipe, hsplit_pipe);
2097 					resource_build_scaling_params(pipe);
2098 					resource_build_scaling_params(hsplit_pipe);
2099 				}
2100 				pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2101 			}
2102 		} else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
2103 			/* merge should already have been done */
2104 			ASSERT(0);
2105 		}
2106 	}
2107 
2108 	/* Actual dsc count per stream dsc validation*/
2109 	if (!dcn20_validate_dsc(dc, context)) {
2110 		context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
2111 				DML_FAIL_DSC_VALIDATION_FAILURE;
2112 		goto validate_fail;
2113 	}
2114 
2115 	*vlevel_out = vlevel;
2116 
2117 	out = true;
2118 	goto validate_out;
2119 
2120 validate_fail:
2121 	out = false;
2122 
2123 validate_out:
2124 	return out;
2125 }
2126 
dcn20_validate_bandwidth(struct dc * dc,struct dc_state * context,bool fast_validate)2127 bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
2128 		bool fast_validate)
2129 {
2130 	bool voltage_supported;
2131 	display_e2e_pipe_params_st *pipes;
2132 
2133 	pipes = kcalloc(dc->res_pool->pipe_count, sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
2134 	if (!pipes)
2135 		return false;
2136 
2137 	DC_FP_START();
2138 	voltage_supported = dcn20_validate_bandwidth_fp(dc, context, fast_validate, pipes);
2139 	DC_FP_END();
2140 
2141 	kfree(pipes);
2142 	return voltage_supported;
2143 }
2144 
dcn20_acquire_free_pipe_for_layer(const struct dc_state * cur_ctx,struct dc_state * new_ctx,const struct resource_pool * pool,const struct pipe_ctx * opp_head)2145 struct pipe_ctx *dcn20_acquire_free_pipe_for_layer(
2146 		const struct dc_state *cur_ctx,
2147 		struct dc_state *new_ctx,
2148 		const struct resource_pool *pool,
2149 		const struct pipe_ctx *opp_head)
2150 {
2151 	struct resource_context *res_ctx = &new_ctx->res_ctx;
2152 	struct pipe_ctx *otg_master = resource_get_otg_master_for_stream(res_ctx, opp_head->stream);
2153 	struct pipe_ctx *sec_dpp_pipe = resource_find_free_secondary_pipe_legacy(res_ctx, pool, otg_master);
2154 
2155 	ASSERT(otg_master);
2156 
2157 	if (!sec_dpp_pipe)
2158 		return NULL;
2159 
2160 	sec_dpp_pipe->stream = opp_head->stream;
2161 	sec_dpp_pipe->stream_res.tg = opp_head->stream_res.tg;
2162 	sec_dpp_pipe->stream_res.opp = opp_head->stream_res.opp;
2163 
2164 	sec_dpp_pipe->plane_res.hubp = pool->hubps[sec_dpp_pipe->pipe_idx];
2165 	sec_dpp_pipe->plane_res.ipp = pool->ipps[sec_dpp_pipe->pipe_idx];
2166 	sec_dpp_pipe->plane_res.dpp = pool->dpps[sec_dpp_pipe->pipe_idx];
2167 	sec_dpp_pipe->plane_res.mpcc_inst = pool->dpps[sec_dpp_pipe->pipe_idx]->inst;
2168 
2169 	return sec_dpp_pipe;
2170 }
2171 
dcn20_get_dcc_compression_cap(const struct dc * dc,const struct dc_dcc_surface_param * input,struct dc_surface_dcc_cap * output)2172 bool dcn20_get_dcc_compression_cap(const struct dc *dc,
2173 		const struct dc_dcc_surface_param *input,
2174 		struct dc_surface_dcc_cap *output)
2175 {
2176 	if (dc->res_pool->hubbub->funcs->get_dcc_compression_cap)
2177 		return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
2178 			dc->res_pool->hubbub, input, output);
2179 
2180 	return false;
2181 }
2182 
dcn20_destroy_resource_pool(struct resource_pool ** pool)2183 static void dcn20_destroy_resource_pool(struct resource_pool **pool)
2184 {
2185 	struct dcn20_resource_pool *dcn20_pool = TO_DCN20_RES_POOL(*pool);
2186 
2187 	dcn20_resource_destruct(dcn20_pool);
2188 	kfree(dcn20_pool);
2189 	*pool = NULL;
2190 }
2191 
2192 
2193 static struct dc_cap_funcs cap_funcs = {
2194 	.get_dcc_compression_cap = dcn20_get_dcc_compression_cap
2195 };
2196 
2197 
dcn20_patch_unknown_plane_state(struct dc_plane_state * plane_state)2198 enum dc_status dcn20_patch_unknown_plane_state(struct dc_plane_state *plane_state)
2199 {
2200 	enum surface_pixel_format surf_pix_format = plane_state->format;
2201 	unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format);
2202 
2203 	plane_state->tiling_info.gfx9.swizzle = DC_SW_64KB_S;
2204 	if (bpp == 64)
2205 		plane_state->tiling_info.gfx9.swizzle = DC_SW_64KB_D;
2206 
2207 	return DC_OK;
2208 }
2209 
dcn20_release_pipe(struct dc_state * context,struct pipe_ctx * pipe,const struct resource_pool * pool)2210 void dcn20_release_pipe(struct dc_state *context,
2211 			struct pipe_ctx *pipe,
2212 			const struct resource_pool *pool)
2213 {
2214 	if (resource_is_pipe_type(pipe, OPP_HEAD) && pipe->stream_res.dsc)
2215 		dcn20_release_dsc(&context->res_ctx, pool, &pipe->stream_res.dsc);
2216 	memset(pipe, 0, sizeof(*pipe));
2217 }
2218 
2219 static const struct resource_funcs dcn20_res_pool_funcs = {
2220 	.destroy = dcn20_destroy_resource_pool,
2221 	.link_enc_create = dcn20_link_encoder_create,
2222 	.panel_cntl_create = dcn20_panel_cntl_create,
2223 	.validate_bandwidth = dcn20_validate_bandwidth,
2224 	.acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
2225 	.release_pipe = dcn20_release_pipe,
2226 	.add_stream_to_ctx = dcn20_add_stream_to_ctx,
2227 	.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
2228 	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
2229 	.populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
2230 	.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
2231 	.set_mcif_arb_params = dcn20_set_mcif_arb_params,
2232 	.populate_dml_pipes = dcn20_populate_dml_pipes_from_context,
2233 	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
2234 	.get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe
2235 };
2236 
dcn20_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)2237 bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
2238 {
2239 	int i;
2240 	uint32_t pipe_count = pool->res_cap->num_dwb;
2241 
2242 	for (i = 0; i < pipe_count; i++) {
2243 		struct dcn20_dwbc *dwbc20 = kzalloc(sizeof(struct dcn20_dwbc),
2244 						    GFP_KERNEL);
2245 
2246 		if (!dwbc20) {
2247 			dm_error("DC: failed to create dwbc20!\n");
2248 			return false;
2249 		}
2250 		dcn20_dwbc_construct(dwbc20, ctx,
2251 				&dwbc20_regs[i],
2252 				&dwbc20_shift,
2253 				&dwbc20_mask,
2254 				i);
2255 		pool->dwbc[i] = &dwbc20->base;
2256 	}
2257 	return true;
2258 }
2259 
dcn20_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)2260 bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
2261 {
2262 	int i;
2263 	uint32_t pipe_count = pool->res_cap->num_dwb;
2264 
2265 	ASSERT(pipe_count > 0);
2266 
2267 	for (i = 0; i < pipe_count; i++) {
2268 		struct dcn20_mmhubbub *mcif_wb20 = kzalloc(sizeof(struct dcn20_mmhubbub),
2269 						    GFP_KERNEL);
2270 
2271 		if (!mcif_wb20) {
2272 			dm_error("DC: failed to create mcif_wb20!\n");
2273 			return false;
2274 		}
2275 
2276 		dcn20_mmhubbub_construct(mcif_wb20, ctx,
2277 				&mcif_wb20_regs[i],
2278 				&mcif_wb20_shift,
2279 				&mcif_wb20_mask,
2280 				i);
2281 
2282 		pool->mcif_wb[i] = &mcif_wb20->base;
2283 	}
2284 	return true;
2285 }
2286 
dcn20_pp_smu_create(struct dc_context * ctx)2287 static struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx)
2288 {
2289 	struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_ATOMIC);
2290 
2291 	if (!pp_smu)
2292 		return pp_smu;
2293 
2294 	dm_pp_get_funcs(ctx, pp_smu);
2295 
2296 	if (pp_smu->ctx.ver != PP_SMU_VER_NV)
2297 		pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
2298 
2299 	return pp_smu;
2300 }
2301 
dcn20_pp_smu_destroy(struct pp_smu_funcs ** pp_smu)2302 static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
2303 {
2304 	if (pp_smu && *pp_smu) {
2305 		kfree(*pp_smu);
2306 		*pp_smu = NULL;
2307 	}
2308 }
2309 
get_asic_rev_soc_bb(uint32_t hw_internal_rev)2310 static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb(
2311 	uint32_t hw_internal_rev)
2312 {
2313 	if (ASICREV_IS_NAVI14_M(hw_internal_rev))
2314 		return &dcn2_0_nv14_soc;
2315 
2316 	if (ASICREV_IS_NAVI12_P(hw_internal_rev))
2317 		return &dcn2_0_nv12_soc;
2318 
2319 	return &dcn2_0_soc;
2320 }
2321 
get_asic_rev_ip_params(uint32_t hw_internal_rev)2322 static struct _vcs_dpi_ip_params_st *get_asic_rev_ip_params(
2323 	uint32_t hw_internal_rev)
2324 {
2325 	if (ASICREV_IS_NAVI14_M(hw_internal_rev))
2326 		return &dcn2_0_nv14_ip;
2327 
2328 	/* NV12 and NV10 */
2329 	return &dcn2_0_ip;
2330 }
2331 
get_dml_project_version(uint32_t hw_internal_rev)2332 static enum dml_project get_dml_project_version(uint32_t hw_internal_rev)
2333 {
2334 	return DML_PROJECT_NAVI10v2;
2335 }
2336 
init_soc_bounding_box(struct dc * dc,struct dcn20_resource_pool * pool)2337 static bool init_soc_bounding_box(struct dc *dc,
2338 				  struct dcn20_resource_pool *pool)
2339 {
2340 	struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
2341 			get_asic_rev_soc_bb(dc->ctx->asic_id.hw_internal_rev);
2342 	struct _vcs_dpi_ip_params_st *loaded_ip =
2343 			get_asic_rev_ip_params(dc->ctx->asic_id.hw_internal_rev);
2344 
2345 	DC_LOGGER_INIT(dc->ctx->logger);
2346 
2347 	if (pool->base.pp_smu) {
2348 		struct pp_smu_nv_clock_table max_clocks = {0};
2349 		unsigned int uclk_states[8] = {0};
2350 		unsigned int num_states = 0;
2351 		enum pp_smu_status status;
2352 		bool clock_limits_available = false;
2353 		bool uclk_states_available = false;
2354 
2355 		if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) {
2356 			status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states)
2357 				(&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states);
2358 
2359 			uclk_states_available = (status == PP_SMU_RESULT_OK);
2360 		}
2361 
2362 		if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) {
2363 			status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks)
2364 					(&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks);
2365 			/* SMU cannot set DCF clock to anything equal to or higher than SOC clock
2366 			 */
2367 			if (max_clocks.dcfClockInKhz >= max_clocks.socClockInKhz)
2368 				max_clocks.dcfClockInKhz = max_clocks.socClockInKhz - 1000;
2369 			clock_limits_available = (status == PP_SMU_RESULT_OK);
2370 		}
2371 
2372 		if (clock_limits_available && uclk_states_available && num_states) {
2373 			DC_FP_START();
2374 			dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states);
2375 			DC_FP_END();
2376 		} else if (clock_limits_available) {
2377 			DC_FP_START();
2378 			dcn20_cap_soc_clocks(loaded_bb, max_clocks);
2379 			DC_FP_END();
2380 		}
2381 	}
2382 
2383 	loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
2384 	loaded_ip->max_num_dpp = pool->base.pipe_count;
2385 	DC_FP_START();
2386 	dcn20_patch_bounding_box(dc, loaded_bb);
2387 	DC_FP_END();
2388 	return true;
2389 }
2390 
dcn20_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn20_resource_pool * pool)2391 static bool dcn20_resource_construct(
2392 	uint8_t num_virtual_links,
2393 	struct dc *dc,
2394 	struct dcn20_resource_pool *pool)
2395 {
2396 	int i;
2397 	struct dc_context *ctx = dc->ctx;
2398 	struct irq_service_init_data init_data;
2399 	struct ddc_service_init_data ddc_init_data = {0};
2400 	struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
2401 			get_asic_rev_soc_bb(ctx->asic_id.hw_internal_rev);
2402 	struct _vcs_dpi_ip_params_st *loaded_ip =
2403 			get_asic_rev_ip_params(ctx->asic_id.hw_internal_rev);
2404 	enum dml_project dml_project_version =
2405 			get_dml_project_version(ctx->asic_id.hw_internal_rev);
2406 
2407 	ctx->dc_bios->regs = &bios_regs;
2408 	pool->base.funcs = &dcn20_res_pool_funcs;
2409 
2410 	if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {
2411 		pool->base.res_cap = &res_cap_nv14;
2412 		pool->base.pipe_count = 5;
2413 		pool->base.mpcc_count = 5;
2414 	} else {
2415 		pool->base.res_cap = &res_cap_nv10;
2416 		pool->base.pipe_count = 6;
2417 		pool->base.mpcc_count = 6;
2418 	}
2419 	/*************************************************
2420 	 *  Resource + asic cap harcoding                *
2421 	 *************************************************/
2422 	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
2423 
2424 	dc->caps.max_downscale_ratio = 200;
2425 	dc->caps.i2c_speed_in_khz = 100;
2426 	dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
2427 	dc->caps.max_cursor_size = 256;
2428 	dc->caps.min_horizontal_blanking_period = 80;
2429 	dc->caps.dmdata_alloc_size = 2048;
2430 
2431 	dc->caps.max_slave_planes = 1;
2432 	dc->caps.max_slave_yuv_planes = 1;
2433 	dc->caps.max_slave_rgb_planes = 1;
2434 	dc->caps.post_blend_color_processing = true;
2435 	dc->caps.force_dp_tps4_for_cp2520 = true;
2436 	dc->caps.extended_aux_timeout_support = true;
2437 	dc->caps.dmcub_support = true;
2438 
2439 	/* Color pipeline capabilities */
2440 	dc->caps.color.dpp.dcn_arch = 1;
2441 	dc->caps.color.dpp.input_lut_shared = 0;
2442 	dc->caps.color.dpp.icsc = 1;
2443 	dc->caps.color.dpp.dgam_ram = 1;
2444 	dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
2445 	dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
2446 	dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;
2447 	dc->caps.color.dpp.dgam_rom_caps.pq = 0;
2448 	dc->caps.color.dpp.dgam_rom_caps.hlg = 0;
2449 	dc->caps.color.dpp.post_csc = 0;
2450 	dc->caps.color.dpp.gamma_corr = 0;
2451 	dc->caps.color.dpp.dgam_rom_for_yuv = 1;
2452 
2453 	dc->caps.color.dpp.hw_3d_lut = 1;
2454 	dc->caps.color.dpp.ogam_ram = 1;
2455 	// no OGAM ROM on DCN2, only MPC ROM
2456 	dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
2457 	dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
2458 	dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
2459 	dc->caps.color.dpp.ogam_rom_caps.pq = 0;
2460 	dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
2461 	dc->caps.color.dpp.ocsc = 0;
2462 
2463 	dc->caps.color.mpc.gamut_remap = 0;
2464 	dc->caps.color.mpc.num_3dluts = 0;
2465 	dc->caps.color.mpc.shared_3d_lut = 0;
2466 	dc->caps.color.mpc.ogam_ram = 1;
2467 	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
2468 	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
2469 	dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
2470 	dc->caps.color.mpc.ogam_rom_caps.pq = 0;
2471 	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
2472 	dc->caps.color.mpc.ocsc = 1;
2473 
2474 	dc->caps.dp_hdmi21_pcon_support = true;
2475 
2476 	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2477 		dc->debug = debug_defaults_drv;
2478 
2479 	//dcn2.0x
2480 	dc->work_arounds.dedcn20_305_wa = true;
2481 
2482 	// Init the vm_helper
2483 	if (dc->vm_helper)
2484 		vm_helper_init(dc->vm_helper, 16);
2485 
2486 	/*************************************************
2487 	 *  Create resources                             *
2488 	 *************************************************/
2489 
2490 	pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
2491 			dcn20_clock_source_create(ctx, ctx->dc_bios,
2492 				CLOCK_SOURCE_COMBO_PHY_PLL0,
2493 				&clk_src_regs[0], false);
2494 	pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
2495 			dcn20_clock_source_create(ctx, ctx->dc_bios,
2496 				CLOCK_SOURCE_COMBO_PHY_PLL1,
2497 				&clk_src_regs[1], false);
2498 	pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
2499 			dcn20_clock_source_create(ctx, ctx->dc_bios,
2500 				CLOCK_SOURCE_COMBO_PHY_PLL2,
2501 				&clk_src_regs[2], false);
2502 	pool->base.clock_sources[DCN20_CLK_SRC_PLL3] =
2503 			dcn20_clock_source_create(ctx, ctx->dc_bios,
2504 				CLOCK_SOURCE_COMBO_PHY_PLL3,
2505 				&clk_src_regs[3], false);
2506 	pool->base.clock_sources[DCN20_CLK_SRC_PLL4] =
2507 			dcn20_clock_source_create(ctx, ctx->dc_bios,
2508 				CLOCK_SOURCE_COMBO_PHY_PLL4,
2509 				&clk_src_regs[4], false);
2510 	pool->base.clock_sources[DCN20_CLK_SRC_PLL5] =
2511 			dcn20_clock_source_create(ctx, ctx->dc_bios,
2512 				CLOCK_SOURCE_COMBO_PHY_PLL5,
2513 				&clk_src_regs[5], false);
2514 	pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL;
2515 	/* todo: not reuse phy_pll registers */
2516 	pool->base.dp_clock_source =
2517 			dcn20_clock_source_create(ctx, ctx->dc_bios,
2518 				CLOCK_SOURCE_ID_DP_DTO,
2519 				&clk_src_regs[0], true);
2520 
2521 	for (i = 0; i < pool->base.clk_src_count; i++) {
2522 		if (pool->base.clock_sources[i] == NULL) {
2523 			dm_error("DC: failed to create clock sources!\n");
2524 			BREAK_TO_DEBUGGER();
2525 			goto create_fail;
2526 		}
2527 	}
2528 
2529 	pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2530 	if (pool->base.dccg == NULL) {
2531 		dm_error("DC: failed to create dccg!\n");
2532 		BREAK_TO_DEBUGGER();
2533 		goto create_fail;
2534 	}
2535 
2536 	pool->base.dmcu = dcn20_dmcu_create(ctx,
2537 			&dmcu_regs,
2538 			&dmcu_shift,
2539 			&dmcu_mask);
2540 	if (pool->base.dmcu == NULL) {
2541 		dm_error("DC: failed to create dmcu!\n");
2542 		BREAK_TO_DEBUGGER();
2543 		goto create_fail;
2544 	}
2545 
2546 	pool->base.abm = dce_abm_create(ctx,
2547 			&abm_regs,
2548 			&abm_shift,
2549 			&abm_mask);
2550 	if (pool->base.abm == NULL) {
2551 		dm_error("DC: failed to create abm!\n");
2552 		BREAK_TO_DEBUGGER();
2553 		goto create_fail;
2554 	}
2555 
2556 	pool->base.pp_smu = dcn20_pp_smu_create(ctx);
2557 
2558 
2559 	if (!init_soc_bounding_box(dc, pool)) {
2560 		dm_error("DC: failed to initialize soc bounding box!\n");
2561 		BREAK_TO_DEBUGGER();
2562 		goto create_fail;
2563 	}
2564 
2565 	dml_init_instance(&dc->dml, loaded_bb, loaded_ip, dml_project_version);
2566 
2567 	if (!dc->debug.disable_pplib_wm_range) {
2568 		struct pp_smu_wm_range_sets ranges = {0};
2569 		int i = 0;
2570 
2571 		ranges.num_reader_wm_sets = 0;
2572 
2573 		if (loaded_bb->num_states == 1) {
2574 			ranges.reader_wm_sets[0].wm_inst = i;
2575 			ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
2576 			ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
2577 			ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
2578 			ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
2579 
2580 			ranges.num_reader_wm_sets = 1;
2581 		} else if (loaded_bb->num_states > 1) {
2582 			for (i = 0; i < 4 && i < loaded_bb->num_states; i++) {
2583 				ranges.reader_wm_sets[i].wm_inst = i;
2584 				ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
2585 				ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
2586 				DC_FP_START();
2587 				dcn20_fpu_set_wm_ranges(i, &ranges, loaded_bb);
2588 				DC_FP_END();
2589 
2590 				ranges.num_reader_wm_sets = i + 1;
2591 			}
2592 
2593 			ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
2594 			ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
2595 		}
2596 
2597 		ranges.num_writer_wm_sets = 1;
2598 
2599 		ranges.writer_wm_sets[0].wm_inst = 0;
2600 		ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
2601 		ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
2602 		ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
2603 		ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
2604 
2605 		/* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
2606 		if (pool->base.pp_smu && pool->base.pp_smu->nv_funcs.set_wm_ranges)
2607 			pool->base.pp_smu->nv_funcs.set_wm_ranges(&pool->base.pp_smu->nv_funcs.pp_smu, &ranges);
2608 	}
2609 
2610 	init_data.ctx = dc->ctx;
2611 	pool->base.irqs = dal_irq_service_dcn20_create(&init_data);
2612 	if (!pool->base.irqs)
2613 		goto create_fail;
2614 
2615 	/* mem input -> ipp -> dpp -> opp -> TG */
2616 	for (i = 0; i < pool->base.pipe_count; i++) {
2617 		pool->base.hubps[i] = dcn20_hubp_create(ctx, i);
2618 		if (pool->base.hubps[i] == NULL) {
2619 			BREAK_TO_DEBUGGER();
2620 			dm_error(
2621 				"DC: failed to create memory input!\n");
2622 			goto create_fail;
2623 		}
2624 
2625 		pool->base.ipps[i] = dcn20_ipp_create(ctx, i);
2626 		if (pool->base.ipps[i] == NULL) {
2627 			BREAK_TO_DEBUGGER();
2628 			dm_error(
2629 				"DC: failed to create input pixel processor!\n");
2630 			goto create_fail;
2631 		}
2632 
2633 		pool->base.dpps[i] = dcn20_dpp_create(ctx, i);
2634 		if (pool->base.dpps[i] == NULL) {
2635 			BREAK_TO_DEBUGGER();
2636 			dm_error(
2637 				"DC: failed to create dpps!\n");
2638 			goto create_fail;
2639 		}
2640 	}
2641 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2642 		pool->base.engines[i] = dcn20_aux_engine_create(ctx, i);
2643 		if (pool->base.engines[i] == NULL) {
2644 			BREAK_TO_DEBUGGER();
2645 			dm_error(
2646 				"DC:failed to create aux engine!!\n");
2647 			goto create_fail;
2648 		}
2649 		pool->base.hw_i2cs[i] = dcn20_i2c_hw_create(ctx, i);
2650 		if (pool->base.hw_i2cs[i] == NULL) {
2651 			BREAK_TO_DEBUGGER();
2652 			dm_error(
2653 				"DC:failed to create hw i2c!!\n");
2654 			goto create_fail;
2655 		}
2656 		pool->base.sw_i2cs[i] = NULL;
2657 	}
2658 
2659 	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2660 		pool->base.opps[i] = dcn20_opp_create(ctx, i);
2661 		if (pool->base.opps[i] == NULL) {
2662 			BREAK_TO_DEBUGGER();
2663 			dm_error(
2664 				"DC: failed to create output pixel processor!\n");
2665 			goto create_fail;
2666 		}
2667 	}
2668 
2669 	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2670 		pool->base.timing_generators[i] = dcn20_timing_generator_create(
2671 				ctx, i);
2672 		if (pool->base.timing_generators[i] == NULL) {
2673 			BREAK_TO_DEBUGGER();
2674 			dm_error("DC: failed to create tg!\n");
2675 			goto create_fail;
2676 		}
2677 	}
2678 
2679 	pool->base.timing_generator_count = i;
2680 
2681 	pool->base.mpc = dcn20_mpc_create(ctx);
2682 	if (pool->base.mpc == NULL) {
2683 		BREAK_TO_DEBUGGER();
2684 		dm_error("DC: failed to create mpc!\n");
2685 		goto create_fail;
2686 	}
2687 
2688 	pool->base.hubbub = dcn20_hubbub_create(ctx);
2689 	if (pool->base.hubbub == NULL) {
2690 		BREAK_TO_DEBUGGER();
2691 		dm_error("DC: failed to create hubbub!\n");
2692 		goto create_fail;
2693 	}
2694 
2695 	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2696 		pool->base.dscs[i] = dcn20_dsc_create(ctx, i);
2697 		if (pool->base.dscs[i] == NULL) {
2698 			BREAK_TO_DEBUGGER();
2699 			dm_error("DC: failed to create display stream compressor %d!\n", i);
2700 			goto create_fail;
2701 		}
2702 	}
2703 
2704 	if (!dcn20_dwbc_create(ctx, &pool->base)) {
2705 		BREAK_TO_DEBUGGER();
2706 		dm_error("DC: failed to create dwbc!\n");
2707 		goto create_fail;
2708 	}
2709 	if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
2710 		BREAK_TO_DEBUGGER();
2711 		dm_error("DC: failed to create mcif_wb!\n");
2712 		goto create_fail;
2713 	}
2714 
2715 	if (!resource_construct(num_virtual_links, dc, &pool->base,
2716 			&res_create_funcs))
2717 		goto create_fail;
2718 
2719 	dcn20_hw_sequencer_construct(dc);
2720 
2721 	// IF NV12, set PG function pointer to NULL. It's not that
2722 	// PG isn't supported for NV12, it's that we don't want to
2723 	// program the registers because that will cause more power
2724 	// to be consumed. We could have created dcn20_init_hw to get
2725 	// the same effect by checking ASIC rev, but there was a
2726 	// request at some point to not check ASIC rev on hw sequencer.
2727 	if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
2728 		dc->hwseq->funcs.enable_power_gating_plane = NULL;
2729 		dc->debug.disable_dpp_power_gate = true;
2730 		dc->debug.disable_hubp_power_gate = true;
2731 	}
2732 
2733 
2734 	dc->caps.max_planes =  pool->base.pipe_count;
2735 
2736 	for (i = 0; i < dc->caps.max_planes; ++i)
2737 		dc->caps.planes[i] = plane_cap;
2738 
2739 	dc->cap_funcs = cap_funcs;
2740 
2741 	if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
2742 		ddc_init_data.ctx = dc->ctx;
2743 		ddc_init_data.link = NULL;
2744 		ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
2745 		ddc_init_data.id.enum_id = 0;
2746 		ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
2747 		pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);
2748 	} else {
2749 		pool->base.oem_device = NULL;
2750 	}
2751 
2752 	return true;
2753 
2754 create_fail:
2755 
2756 	dcn20_resource_destruct(pool);
2757 
2758 	return false;
2759 }
2760 
dcn20_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)2761 struct resource_pool *dcn20_create_resource_pool(
2762 		const struct dc_init_data *init_data,
2763 		struct dc *dc)
2764 {
2765 	struct dcn20_resource_pool *pool =
2766 		kzalloc(sizeof(struct dcn20_resource_pool), GFP_ATOMIC);
2767 
2768 	if (!pool)
2769 		return NULL;
2770 
2771 	if (dcn20_resource_construct(init_data->num_virtual_links, dc, pool))
2772 		return &pool->base;
2773 
2774 	BREAK_TO_DEBUGGER();
2775 	kfree(pool);
2776 	return NULL;
2777 }
2778