1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #ifndef _CORESIGHT_CORESIGHT_TPDM_H 7 #define _CORESIGHT_CORESIGHT_TPDM_H 8 9 /* The max number of the datasets that TPDM supports */ 10 #define TPDM_DATASETS 7 11 12 /* CMB/MCMB Subunit Registers */ 13 #define TPDM_CMB_CR (0xA00) 14 /* CMB subunit timestamp insertion enable register */ 15 #define TPDM_CMB_TIER (0xA04) 16 /* CMB subunit timestamp pattern registers */ 17 #define TPDM_CMB_TPR(n) (0xA08 + (n * 4)) 18 /* CMB subunit timestamp pattern mask registers */ 19 #define TPDM_CMB_TPMR(n) (0xA10 + (n * 4)) 20 /* CMB subunit trigger pattern registers */ 21 #define TPDM_CMB_XPR(n) (0xA18 + (n * 4)) 22 /* CMB subunit trigger pattern mask registers */ 23 #define TPDM_CMB_XPMR(n) (0xA20 + (n * 4)) 24 /* CMB MSR register */ 25 #define TPDM_CMB_MSR(n) (0xA80 + (n * 4)) 26 27 /* Enable bit for CMB subunit */ 28 #define TPDM_CMB_CR_ENA BIT(0) 29 /* Trace collection mode for CMB subunit */ 30 #define TPDM_CMB_CR_MODE BIT(1) 31 /* MCMB trigger lane select */ 32 #define TPDM_CMB_CR_XTRIG_LNSEL GENMASK(20, 18) 33 /* MCMB lane enablement */ 34 #define TPDM_CMB_CR_E_LN GENMASK(17, 10) 35 /* Timestamp control for pattern match */ 36 #define TPDM_CMB_TIER_PATT_TSENAB BIT(0) 37 /* CMB CTI timestamp request */ 38 #define TPDM_CMB_TIER_XTRIG_TSENAB BIT(1) 39 /* For timestamp fo all trace */ 40 #define TPDM_CMB_TIER_TS_ALL BIT(2) 41 42 /* Patten register number */ 43 #define TPDM_CMB_MAX_PATT 2 44 45 /* MAX number of DSB MSR */ 46 #define TPDM_CMB_MAX_MSR 32 47 48 /* MAX lanes in the output pattern for MCMB configurations*/ 49 #define TPDM_MCMB_MAX_LANES 8 50 51 /* Filter bit 0~7 from the value for CR_E_LN */ 52 #define TPDM_MCMB_E_LN_MASK GENMASK(7, 0) 53 54 /* DSB Subunit Registers */ 55 #define TPDM_DSB_CR (0x780) 56 #define TPDM_DSB_TIER (0x784) 57 #define TPDM_DSB_TPR(n) (0x788 + (n * 4)) 58 #define TPDM_DSB_TPMR(n) (0x7A8 + (n * 4)) 59 #define TPDM_DSB_XPR(n) (0x7C8 + (n * 4)) 60 #define TPDM_DSB_XPMR(n) (0x7E8 + (n * 4)) 61 #define TPDM_DSB_EDCR(n) (0x808 + (n * 4)) 62 #define TPDM_DSB_EDCMR(n) (0x848 + (n * 4)) 63 #define TPDM_DSB_MSR(n) (0x980 + (n * 4)) 64 65 /* Enable bit for DSB subunit */ 66 #define TPDM_DSB_CR_ENA BIT(0) 67 /* Enable bit for DSB subunit perfmance mode */ 68 #define TPDM_DSB_CR_MODE BIT(1) 69 /* Enable bit for DSB subunit trigger type */ 70 #define TPDM_DSB_CR_TRIG_TYPE BIT(12) 71 /* Data bits for DSB high performace mode */ 72 #define TPDM_DSB_CR_HPSEL GENMASK(6, 2) 73 /* Data bits for DSB test mode */ 74 #define TPDM_DSB_CR_TEST_MODE GENMASK(10, 9) 75 76 /* Enable bit for DSB subunit pattern timestamp */ 77 #define TPDM_DSB_TIER_PATT_TSENAB BIT(0) 78 /* Enable bit for DSB subunit trigger timestamp */ 79 #define TPDM_DSB_TIER_XTRIG_TSENAB BIT(1) 80 /* Bit for DSB subunit pattern type */ 81 #define TPDM_DSB_TIER_PATT_TYPE BIT(2) 82 83 /* DSB programming modes */ 84 /* DSB mode bits mask */ 85 #define TPDM_DSB_MODE_MASK GENMASK(8, 0) 86 /* Test mode control bit*/ 87 #define TPDM_DSB_MODE_TEST(val) (val & GENMASK(1, 0)) 88 /* Performance mode */ 89 #define TPDM_DSB_MODE_PERF BIT(3) 90 /* High performance mode */ 91 #define TPDM_DSB_MODE_HPBYTESEL(val) (val & GENMASK(8, 4)) 92 93 #define EDCRS_PER_WORD 16 94 #define EDCR_TO_WORD_IDX(r) ((r) / EDCRS_PER_WORD) 95 #define EDCR_TO_WORD_SHIFT(r) ((r % EDCRS_PER_WORD) * 2) 96 #define EDCR_TO_WORD_VAL(val, r) (val << EDCR_TO_WORD_SHIFT(r)) 97 #define EDCR_TO_WORD_MASK(r) EDCR_TO_WORD_VAL(0x3, r) 98 99 #define EDCMRS_PER_WORD 32 100 #define EDCMR_TO_WORD_IDX(r) ((r) / EDCMRS_PER_WORD) 101 #define EDCMR_TO_WORD_SHIFT(r) ((r) % EDCMRS_PER_WORD) 102 103 /* TPDM integration test registers */ 104 #define TPDM_ITATBCNTRL (0xEF0) 105 #define TPDM_ITCNTRL (0xF00) 106 107 /* Register value for integration test */ 108 #define ATBCNTRL_VAL_32 0xC00F1409 109 #define ATBCNTRL_VAL_64 0xC01F1409 110 111 /* 112 * Number of cycles to write value when 113 * integration test. 114 */ 115 #define INTEGRATION_TEST_CYCLE 10 116 117 /** 118 * The bits of PERIPHIDR0 register. 119 * The fields [6:0] of PERIPHIDR0 are used to determine what 120 * interfaces and subunits are present on a given TPDM. 121 * 122 * PERIPHIDR0[0] : Fix to 1 if ImplDef subunit present, else 0 123 * PERIPHIDR0[1] : Fix to 1 if DSB subunit present, else 0 124 * PERIPHIDR0[2] : Fix to 1 if CMB subunit present, else 0 125 * PERIPHIDR0[6] : Fix to 1 if MCMB subunit present, else 0 126 */ 127 128 #define TPDM_PIDR0_DS_IMPDEF BIT(0) 129 #define TPDM_PIDR0_DS_DSB BIT(1) 130 #define TPDM_PIDR0_DS_CMB BIT(2) 131 #define TPDM_PIDR0_DS_MCMB BIT(6) 132 133 #define TPDM_DSB_MAX_LINES 256 134 /* MAX number of EDCR registers */ 135 #define TPDM_DSB_MAX_EDCR 16 136 /* MAX number of EDCMR registers */ 137 #define TPDM_DSB_MAX_EDCMR 8 138 /* MAX number of DSB pattern */ 139 #define TPDM_DSB_MAX_PATT 8 140 /* MAX number of DSB MSR */ 141 #define TPDM_DSB_MAX_MSR 32 142 143 #define tpdm_simple_dataset_ro(name, mem, idx) \ 144 (&((struct tpdm_dataset_attribute[]) { \ 145 { \ 146 __ATTR(name, 0444, tpdm_simple_dataset_show, NULL), \ 147 mem, \ 148 idx, \ 149 } \ 150 })[0].attr.attr) 151 152 #define tpdm_simple_dataset_rw(name, mem, idx) \ 153 (&((struct tpdm_dataset_attribute[]) { \ 154 { \ 155 __ATTR(name, 0644, tpdm_simple_dataset_show, \ 156 tpdm_simple_dataset_store), \ 157 mem, \ 158 idx, \ 159 } \ 160 })[0].attr.attr) 161 162 #define tpdm_patt_enable_ts(name, mem) \ 163 (&((struct tpdm_dataset_attribute[]) { \ 164 { \ 165 __ATTR(name, 0644, enable_ts_show, \ 166 enable_ts_store), \ 167 mem, \ 168 0, \ 169 } \ 170 })[0].attr.attr) 171 172 #define DSB_EDGE_CTRL_ATTR(nr) \ 173 tpdm_simple_dataset_ro(edcr##nr, \ 174 DSB_EDGE_CTRL, nr) 175 176 #define DSB_EDGE_CTRL_MASK_ATTR(nr) \ 177 tpdm_simple_dataset_ro(edcmr##nr, \ 178 DSB_EDGE_CTRL_MASK, nr) 179 180 #define DSB_TRIG_PATT_ATTR(nr) \ 181 tpdm_simple_dataset_rw(xpr##nr, \ 182 DSB_TRIG_PATT, nr) 183 184 #define DSB_TRIG_PATT_MASK_ATTR(nr) \ 185 tpdm_simple_dataset_rw(xpmr##nr, \ 186 DSB_TRIG_PATT_MASK, nr) 187 188 #define DSB_PATT_ATTR(nr) \ 189 tpdm_simple_dataset_rw(tpr##nr, \ 190 DSB_PATT, nr) 191 192 #define DSB_PATT_MASK_ATTR(nr) \ 193 tpdm_simple_dataset_rw(tpmr##nr, \ 194 DSB_PATT_MASK, nr) 195 196 #define DSB_PATT_ENABLE_TS \ 197 tpdm_patt_enable_ts(enable_ts, \ 198 DSB_PATT) 199 200 #define DSB_MSR_ATTR(nr) \ 201 tpdm_simple_dataset_rw(msr##nr, \ 202 DSB_MSR, nr) 203 204 #define CMB_TRIG_PATT_ATTR(nr) \ 205 tpdm_simple_dataset_rw(xpr##nr, \ 206 CMB_TRIG_PATT, nr) 207 208 #define CMB_TRIG_PATT_MASK_ATTR(nr) \ 209 tpdm_simple_dataset_rw(xpmr##nr, \ 210 CMB_TRIG_PATT_MASK, nr) 211 212 #define CMB_PATT_ATTR(nr) \ 213 tpdm_simple_dataset_rw(tpr##nr, \ 214 CMB_PATT, nr) 215 216 #define CMB_PATT_MASK_ATTR(nr) \ 217 tpdm_simple_dataset_rw(tpmr##nr, \ 218 CMB_PATT_MASK, nr) 219 220 #define CMB_PATT_ENABLE_TS \ 221 tpdm_patt_enable_ts(enable_ts, \ 222 CMB_PATT) 223 224 #define CMB_MSR_ATTR(nr) \ 225 tpdm_simple_dataset_rw(msr##nr, \ 226 CMB_MSR, nr) 227 228 /** 229 * struct dsb_dataset - specifics associated to dsb dataset 230 * @mode: DSB programming mode 231 * @edge_ctrl_idx Index number of the edge control 232 * @edge_ctrl: Save value for edge control 233 * @edge_ctrl_mask: Save value for edge control mask 234 * @patt_val: Save value for pattern 235 * @patt_mask: Save value for pattern mask 236 * @trig_patt: Save value for trigger pattern 237 * @trig_patt_mask: Save value for trigger pattern mask 238 * @msr Save value for MSR 239 * @patt_ts: Enable/Disable pattern timestamp 240 * @patt_type: Set pattern type 241 * @trig_ts: Enable/Disable trigger timestamp. 242 * @trig_type: Enable/Disable trigger type. 243 */ 244 struct dsb_dataset { 245 u32 mode; 246 u32 edge_ctrl_idx; 247 u32 edge_ctrl[TPDM_DSB_MAX_EDCR]; 248 u32 edge_ctrl_mask[TPDM_DSB_MAX_EDCMR]; 249 u32 patt_val[TPDM_DSB_MAX_PATT]; 250 u32 patt_mask[TPDM_DSB_MAX_PATT]; 251 u32 trig_patt[TPDM_DSB_MAX_PATT]; 252 u32 trig_patt_mask[TPDM_DSB_MAX_PATT]; 253 u32 msr[TPDM_DSB_MAX_MSR]; 254 bool patt_ts; 255 bool patt_type; 256 bool trig_ts; 257 bool trig_type; 258 }; 259 260 /** 261 * struct cmb_dataset 262 * @trace_mode: Dataset collection mode 263 * @patt_val: Save value for pattern 264 * @patt_mask: Save value for pattern mask 265 * @trig_patt: Save value for trigger pattern 266 * @trig_patt_mask: Save value for trigger pattern mask 267 * @msr Save value for MSR 268 * @patt_ts: Indicates if pattern match for timestamp is enabled. 269 * @trig_ts: Indicates if CTI trigger for timestamp is enabled. 270 * @ts_all: Indicates if timestamp is enabled for all packets. 271 * struct mcmb_dataset 272 * @mcmb_trig_lane: Save data for trigger lane 273 * @mcmb_lane_select: Save data for lane enablement 274 */ 275 struct cmb_dataset { 276 u32 trace_mode; 277 u32 patt_val[TPDM_CMB_MAX_PATT]; 278 u32 patt_mask[TPDM_CMB_MAX_PATT]; 279 u32 trig_patt[TPDM_CMB_MAX_PATT]; 280 u32 trig_patt_mask[TPDM_CMB_MAX_PATT]; 281 u32 msr[TPDM_CMB_MAX_MSR]; 282 bool patt_ts; 283 bool trig_ts; 284 bool ts_all; 285 struct { 286 u8 trig_lane; 287 u8 lane_select; 288 } mcmb; 289 }; 290 291 /** 292 * struct tpdm_drvdata - specifics associated to an TPDM component 293 * @base: memory mapped base address for this component. 294 * @dev: The device entity associated to this component. 295 * @csdev: component vitals needed by the framework. 296 * @spinlock: lock for the drvdata value. 297 * @enable: enable status of the component. 298 * @datasets: The datasets types present of the TPDM. 299 * @dsb Specifics associated to TPDM DSB. 300 * @cmb Specifics associated to TPDM CMB. 301 * @dsb_msr_num Number of MSR supported by DSB TPDM 302 * @cmb_msr_num Number of MSR supported by CMB TPDM 303 */ 304 305 struct tpdm_drvdata { 306 void __iomem *base; 307 struct device *dev; 308 struct coresight_device *csdev; 309 spinlock_t spinlock; 310 bool enable; 311 unsigned long datasets; 312 struct dsb_dataset *dsb; 313 struct cmb_dataset *cmb; 314 u32 dsb_msr_num; 315 u32 cmb_msr_num; 316 }; 317 318 /* Enumerate members of various datasets */ 319 enum dataset_mem { 320 DSB_EDGE_CTRL, 321 DSB_EDGE_CTRL_MASK, 322 DSB_TRIG_PATT, 323 DSB_TRIG_PATT_MASK, 324 DSB_PATT, 325 DSB_PATT_MASK, 326 DSB_MSR, 327 CMB_TRIG_PATT, 328 CMB_TRIG_PATT_MASK, 329 CMB_PATT, 330 CMB_PATT_MASK, 331 CMB_MSR 332 }; 333 334 /** 335 * struct tpdm_dataset_attribute - Record the member variables and 336 * index number of datasets that need to be operated by sysfs file 337 * @attr: The device attribute 338 * @mem: The member in the dataset data structure 339 * @idx: The index number of the array data 340 */ 341 struct tpdm_dataset_attribute { 342 struct device_attribute attr; 343 enum dataset_mem mem; 344 u32 idx; 345 }; 346 #endif /* _CORESIGHT_CORESIGHT_TPDM_H */ 347