1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
4  */
5 
6 #ifndef _CORESIGHT_CTCU_H
7 #define _CORESIGHT_CTCU_H
8 #include "coresight-trace-id.h"
9 
10 /* Maximum number of supported ETR devices for a single CTCU. */
11 #define ETR_MAX_NUM	2
12 
13 /**
14  * struct ctcu_etr_config
15  * @atid_offset:	offset to the ATID0 Register.
16  * @port_num:		in-port number of CTCU device that connected to ETR.
17  */
18 struct ctcu_etr_config {
19 	const u32 atid_offset;
20 	const u32 port_num;
21 };
22 
23 struct ctcu_config {
24 	const struct ctcu_etr_config *etr_cfgs;
25 	int num_etr_config;
26 };
27 
28 struct ctcu_drvdata {
29 	void __iomem		*base;
30 	struct clk		*apb_clk;
31 	struct device		*dev;
32 	struct coresight_device	*csdev;
33 	raw_spinlock_t		spin_lock;
34 	u32			atid_offset[ETR_MAX_NUM];
35 	/* refcnt for each traceid of each sink */
36 	u8			traceid_refcnt[ETR_MAX_NUM][CORESIGHT_TRACE_ID_RES_TOP];
37 };
38 
39 #endif
40