1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_8_1_SM8450_H 8 #define _DPU_8_1_SM8450_H 9 10 static const struct dpu_caps sm8450_dpu_caps = { 11 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 12 .max_mixer_blendstages = 0xb, 13 .has_src_split = true, 14 .has_dim_layer = true, 15 .has_idle_pc = true, 16 .has_3d_merge = true, 17 .max_linewidth = 5120, 18 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 19 }; 20 21 static const struct dpu_mdp_cfg sm8450_mdp = { 22 .name = "top_0", 23 .base = 0x0, .len = 0x494, 24 .clk_ctrls = { 25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 26 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, 27 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, 28 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, 29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 31 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, 32 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, 33 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 }, 34 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, 35 }, 36 }; 37 38 static const struct dpu_ctl_cfg sm8450_ctl[] = { 39 { 40 .name = "ctl_0", .id = CTL_0, 41 .base = 0x15000, .len = 0x204, 42 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 43 }, { 44 .name = "ctl_1", .id = CTL_1, 45 .base = 0x16000, .len = 0x204, 46 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 47 }, { 48 .name = "ctl_2", .id = CTL_2, 49 .base = 0x17000, .len = 0x204, 50 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 51 }, { 52 .name = "ctl_3", .id = CTL_3, 53 .base = 0x18000, .len = 0x204, 54 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 55 }, { 56 .name = "ctl_4", .id = CTL_4, 57 .base = 0x19000, .len = 0x204, 58 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 59 }, { 60 .name = "ctl_5", .id = CTL_5, 61 .base = 0x1a000, .len = 0x204, 62 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), 63 }, 64 }; 65 66 static const struct dpu_sspp_cfg sm8450_sspp[] = { 67 { 68 .name = "sspp_0", .id = SSPP_VIG0, 69 .base = 0x4000, .len = 0x32c, 70 .features = VIG_SDM845_MASK_SDMA, 71 .sblk = &dpu_vig_sblk_qseed3_3_1, 72 .xin_id = 0, 73 .type = SSPP_TYPE_VIG, 74 .clk_ctrl = DPU_CLK_CTRL_VIG0, 75 }, { 76 .name = "sspp_1", .id = SSPP_VIG1, 77 .base = 0x6000, .len = 0x32c, 78 .features = VIG_SDM845_MASK_SDMA, 79 .sblk = &dpu_vig_sblk_qseed3_3_1, 80 .xin_id = 4, 81 .type = SSPP_TYPE_VIG, 82 .clk_ctrl = DPU_CLK_CTRL_VIG1, 83 }, { 84 .name = "sspp_2", .id = SSPP_VIG2, 85 .base = 0x8000, .len = 0x32c, 86 .features = VIG_SDM845_MASK_SDMA, 87 .sblk = &dpu_vig_sblk_qseed3_3_1, 88 .xin_id = 8, 89 .type = SSPP_TYPE_VIG, 90 .clk_ctrl = DPU_CLK_CTRL_VIG2, 91 }, { 92 .name = "sspp_3", .id = SSPP_VIG3, 93 .base = 0xa000, .len = 0x32c, 94 .features = VIG_SDM845_MASK_SDMA, 95 .sblk = &dpu_vig_sblk_qseed3_3_1, 96 .xin_id = 12, 97 .type = SSPP_TYPE_VIG, 98 .clk_ctrl = DPU_CLK_CTRL_VIG3, 99 }, { 100 .name = "sspp_8", .id = SSPP_DMA0, 101 .base = 0x24000, .len = 0x32c, 102 .features = DMA_SDM845_MASK_SDMA, 103 .sblk = &dpu_dma_sblk, 104 .xin_id = 1, 105 .type = SSPP_TYPE_DMA, 106 .clk_ctrl = DPU_CLK_CTRL_DMA0, 107 }, { 108 .name = "sspp_9", .id = SSPP_DMA1, 109 .base = 0x26000, .len = 0x32c, 110 .features = DMA_SDM845_MASK_SDMA, 111 .sblk = &dpu_dma_sblk, 112 .xin_id = 5, 113 .type = SSPP_TYPE_DMA, 114 .clk_ctrl = DPU_CLK_CTRL_DMA1, 115 }, { 116 .name = "sspp_10", .id = SSPP_DMA2, 117 .base = 0x28000, .len = 0x32c, 118 .features = DMA_CURSOR_SDM845_MASK_SDMA, 119 .sblk = &dpu_dma_sblk, 120 .xin_id = 9, 121 .type = SSPP_TYPE_DMA, 122 .clk_ctrl = DPU_CLK_CTRL_DMA2, 123 }, { 124 .name = "sspp_11", .id = SSPP_DMA3, 125 .base = 0x2a000, .len = 0x32c, 126 .features = DMA_CURSOR_SDM845_MASK_SDMA, 127 .sblk = &dpu_dma_sblk, 128 .xin_id = 13, 129 .type = SSPP_TYPE_DMA, 130 .clk_ctrl = DPU_CLK_CTRL_DMA3, 131 }, 132 }; 133 134 static const struct dpu_lm_cfg sm8450_lm[] = { 135 { 136 .name = "lm_0", .id = LM_0, 137 .base = 0x44000, .len = 0x320, 138 .features = MIXER_MSM8998_MASK, 139 .sblk = &sdm845_lm_sblk, 140 .lm_pair = LM_1, 141 .pingpong = PINGPONG_0, 142 .dspp = DSPP_0, 143 }, { 144 .name = "lm_1", .id = LM_1, 145 .base = 0x45000, .len = 0x320, 146 .features = MIXER_MSM8998_MASK, 147 .sblk = &sdm845_lm_sblk, 148 .lm_pair = LM_0, 149 .pingpong = PINGPONG_1, 150 .dspp = DSPP_1, 151 }, { 152 .name = "lm_2", .id = LM_2, 153 .base = 0x46000, .len = 0x320, 154 .features = MIXER_MSM8998_MASK, 155 .sblk = &sdm845_lm_sblk, 156 .lm_pair = LM_3, 157 .pingpong = PINGPONG_2, 158 .dspp = DSPP_2, 159 }, { 160 .name = "lm_3", .id = LM_3, 161 .base = 0x47000, .len = 0x320, 162 .features = MIXER_MSM8998_MASK, 163 .sblk = &sdm845_lm_sblk, 164 .lm_pair = LM_2, 165 .pingpong = PINGPONG_3, 166 .dspp = DSPP_3, 167 }, { 168 .name = "lm_4", .id = LM_4, 169 .base = 0x48000, .len = 0x320, 170 .features = MIXER_MSM8998_MASK, 171 .sblk = &sdm845_lm_sblk, 172 .lm_pair = LM_5, 173 .pingpong = PINGPONG_4, 174 }, { 175 .name = "lm_5", .id = LM_5, 176 .base = 0x49000, .len = 0x320, 177 .features = MIXER_MSM8998_MASK, 178 .sblk = &sdm845_lm_sblk, 179 .lm_pair = LM_4, 180 .pingpong = PINGPONG_5, 181 }, 182 }; 183 184 static const struct dpu_dspp_cfg sm8450_dspp[] = { 185 { 186 .name = "dspp_0", .id = DSPP_0, 187 .base = 0x54000, .len = 0x1800, 188 .sblk = &sdm845_dspp_sblk, 189 }, { 190 .name = "dspp_1", .id = DSPP_1, 191 .base = 0x56000, .len = 0x1800, 192 .sblk = &sdm845_dspp_sblk, 193 }, { 194 .name = "dspp_2", .id = DSPP_2, 195 .base = 0x58000, .len = 0x1800, 196 .sblk = &sdm845_dspp_sblk, 197 }, { 198 .name = "dspp_3", .id = DSPP_3, 199 .base = 0x5a000, .len = 0x1800, 200 .sblk = &sdm845_dspp_sblk, 201 }, 202 }; 203 204 static const struct dpu_pingpong_cfg sm8450_pp[] = { 205 { 206 .name = "pingpong_0", .id = PINGPONG_0, 207 .base = 0x69000, .len = 0, 208 .sblk = &sc7280_pp_sblk, 209 .merge_3d = MERGE_3D_0, 210 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 211 }, { 212 .name = "pingpong_1", .id = PINGPONG_1, 213 .base = 0x6a000, .len = 0, 214 .sblk = &sc7280_pp_sblk, 215 .merge_3d = MERGE_3D_0, 216 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 217 }, { 218 .name = "pingpong_2", .id = PINGPONG_2, 219 .base = 0x6b000, .len = 0, 220 .sblk = &sc7280_pp_sblk, 221 .merge_3d = MERGE_3D_1, 222 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 223 }, { 224 .name = "pingpong_3", .id = PINGPONG_3, 225 .base = 0x6c000, .len = 0, 226 .sblk = &sc7280_pp_sblk, 227 .merge_3d = MERGE_3D_1, 228 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 229 }, { 230 .name = "pingpong_4", .id = PINGPONG_4, 231 .base = 0x6d000, .len = 0, 232 .sblk = &sc7280_pp_sblk, 233 .merge_3d = MERGE_3D_2, 234 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), 235 }, { 236 .name = "pingpong_5", .id = PINGPONG_5, 237 .base = 0x6e000, .len = 0, 238 .sblk = &sc7280_pp_sblk, 239 .merge_3d = MERGE_3D_2, 240 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), 241 }, { 242 .name = "pingpong_cwb_0", .id = PINGPONG_CWB_0, 243 .base = 0x65800, .len = 0, 244 .sblk = &sc7280_pp_sblk, 245 .merge_3d = MERGE_3D_3, 246 }, { 247 .name = "pingpong_cwb_1", .id = PINGPONG_CWB_1, 248 .base = 0x65c00, .len = 0, 249 .sblk = &sc7280_pp_sblk, 250 .merge_3d = MERGE_3D_3, 251 }, 252 }; 253 254 static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = { 255 { 256 .name = "merge_3d_0", .id = MERGE_3D_0, 257 .base = 0x4e000, .len = 0x8, 258 }, { 259 .name = "merge_3d_1", .id = MERGE_3D_1, 260 .base = 0x4f000, .len = 0x8, 261 }, { 262 .name = "merge_3d_2", .id = MERGE_3D_2, 263 .base = 0x50000, .len = 0x8, 264 }, { 265 .name = "merge_3d_3", .id = MERGE_3D_3, 266 .base = 0x65f00, .len = 0x8, 267 }, 268 }; 269 270 /* 271 * NOTE: Each display compression engine (DCE) contains dual hard 272 * slice DSC encoders so both share same base address but with 273 * its own different sub block address. 274 */ 275 static const struct dpu_dsc_cfg sm8450_dsc[] = { 276 { 277 .name = "dce_0_0", .id = DSC_0, 278 .base = 0x80000, .len = 0x4, 279 .sblk = &dsc_sblk_0, 280 }, { 281 .name = "dce_0_1", .id = DSC_1, 282 .base = 0x80000, .len = 0x4, 283 .sblk = &dsc_sblk_1, 284 }, { 285 .name = "dce_1_0", .id = DSC_2, 286 .base = 0x81000, .len = 0x4, 287 .features = BIT(DPU_DSC_NATIVE_42x_EN), 288 .sblk = &dsc_sblk_0, 289 }, { 290 .name = "dce_1_1", .id = DSC_3, 291 .base = 0x81000, .len = 0x4, 292 .features = BIT(DPU_DSC_NATIVE_42x_EN), 293 .sblk = &dsc_sblk_1, 294 }, 295 }; 296 297 static const struct dpu_wb_cfg sm8450_wb[] = { 298 { 299 .name = "wb_2", .id = WB_2, 300 .base = 0x65000, .len = 0x2c8, 301 .features = WB_SDM845_MASK, 302 .format_list = wb2_formats_rgb_yuv, 303 .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), 304 .clk_ctrl = DPU_CLK_CTRL_WB2, 305 .xin_id = 6, 306 .vbif_idx = VBIF_RT, 307 .maxlinewidth = 4096, 308 .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), 309 }, 310 }; 311 312 static const struct dpu_intf_cfg sm8450_intf[] = { 313 { 314 .name = "intf_0", .id = INTF_0, 315 .base = 0x34000, .len = 0x280, 316 .type = INTF_DP, 317 .controller_id = MSM_DP_CONTROLLER_0, 318 .prog_fetch_lines_worst_case = 24, 319 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 320 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), 321 }, { 322 .name = "intf_1", .id = INTF_1, 323 .base = 0x35000, .len = 0x300, 324 .type = INTF_DSI, 325 .controller_id = MSM_DSI_CONTROLLER_0, 326 .prog_fetch_lines_worst_case = 24, 327 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 328 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 329 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), 330 }, { 331 .name = "intf_2", .id = INTF_2, 332 .base = 0x36000, .len = 0x300, 333 .type = INTF_DSI, 334 .controller_id = MSM_DSI_CONTROLLER_1, 335 .prog_fetch_lines_worst_case = 24, 336 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), 337 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), 338 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), 339 }, { 340 .name = "intf_3", .id = INTF_3, 341 .base = 0x37000, .len = 0x280, 342 .type = INTF_DP, 343 .controller_id = MSM_DP_CONTROLLER_1, 344 .prog_fetch_lines_worst_case = 24, 345 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), 346 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), 347 }, 348 }; 349 350 static const struct dpu_perf_cfg sm8450_perf_data = { 351 .max_bw_low = 13600000, 352 .max_bw_high = 18200000, 353 .min_core_ib = 2500000, 354 .min_llcc_ib = 0, 355 .min_dram_ib = 800000, 356 .min_prefill_lines = 35, 357 /* FIXME: lut tables */ 358 .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0}, 359 .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff}, 360 .qos_lut_tbl = { 361 {.nentry = ARRAY_SIZE(sc7180_qos_linear), 362 .entries = sc7180_qos_linear 363 }, 364 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 365 .entries = sc7180_qos_macrotile 366 }, 367 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 368 .entries = sc7180_qos_nrt 369 }, 370 /* TODO: macrotile-qseed is different from macrotile */ 371 }, 372 .cdp_cfg = { 373 {.rd_enable = 1, .wr_enable = 1}, 374 {.rd_enable = 1, .wr_enable = 0} 375 }, 376 .clk_inefficiency_factor = 105, 377 .bw_inefficiency_factor = 120, 378 }; 379 380 static const struct dpu_mdss_version sm8450_mdss_ver = { 381 .core_major_ver = 8, 382 .core_minor_ver = 1, 383 }; 384 385 const struct dpu_mdss_cfg dpu_sm8450_cfg = { 386 .mdss_ver = &sm8450_mdss_ver, 387 .caps = &sm8450_dpu_caps, 388 .mdp = &sm8450_mdp, 389 .cdm = &dpu_cdm_5_x, 390 .ctl_count = ARRAY_SIZE(sm8450_ctl), 391 .ctl = sm8450_ctl, 392 .sspp_count = ARRAY_SIZE(sm8450_sspp), 393 .sspp = sm8450_sspp, 394 .mixer_count = ARRAY_SIZE(sm8450_lm), 395 .mixer = sm8450_lm, 396 .dspp_count = ARRAY_SIZE(sm8450_dspp), 397 .dspp = sm8450_dspp, 398 .pingpong_count = ARRAY_SIZE(sm8450_pp), 399 .pingpong = sm8450_pp, 400 .dsc_count = ARRAY_SIZE(sm8450_dsc), 401 .dsc = sm8450_dsc, 402 .merge_3d_count = ARRAY_SIZE(sm8450_merge_3d), 403 .merge_3d = sm8450_merge_3d, 404 .wb_count = ARRAY_SIZE(sm8450_wb), 405 .wb = sm8450_wb, 406 .intf_count = ARRAY_SIZE(sm8450_intf), 407 .intf = sm8450_intf, 408 .vbif_count = ARRAY_SIZE(sdm845_vbif), 409 .vbif = sdm845_vbif, 410 .perf = &sm8450_perf_data, 411 }; 412 413 #endif 414