1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_8_0_SC8280XP_H 8 #define _DPU_8_0_SC8280XP_H 9 10 static const struct dpu_caps sc8280xp_dpu_caps = { 11 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 12 .max_mixer_blendstages = 11, 13 .has_src_split = true, 14 .has_dim_layer = true, 15 .has_idle_pc = true, 16 .has_3d_merge = true, 17 .max_linewidth = 5120, 18 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 19 }; 20 21 static const struct dpu_mdp_cfg sc8280xp_mdp = { 22 .name = "top_0", 23 .base = 0x0, .len = 0x494, 24 .clk_ctrls = { 25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 26 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, 27 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, 28 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, 29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 31 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, 32 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, 33 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, 34 }, 35 }; 36 37 static const struct dpu_ctl_cfg sc8280xp_ctl[] = { 38 { 39 .name = "ctl_0", .id = CTL_0, 40 .base = 0x15000, .len = 0x204, 41 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 42 }, { 43 .name = "ctl_1", .id = CTL_1, 44 .base = 0x16000, .len = 0x204, 45 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 46 }, { 47 .name = "ctl_2", .id = CTL_2, 48 .base = 0x17000, .len = 0x204, 49 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 50 }, { 51 .name = "ctl_3", .id = CTL_3, 52 .base = 0x18000, .len = 0x204, 53 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 54 }, { 55 .name = "ctl_4", .id = CTL_4, 56 .base = 0x19000, .len = 0x204, 57 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 58 }, { 59 .name = "ctl_5", .id = CTL_5, 60 .base = 0x1a000, .len = 0x204, 61 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), 62 }, 63 }; 64 65 static const struct dpu_sspp_cfg sc8280xp_sspp[] = { 66 { 67 .name = "sspp_0", .id = SSPP_VIG0, 68 .base = 0x4000, .len = 0x2ac, 69 .features = VIG_SDM845_MASK_SDMA, 70 .sblk = &dpu_vig_sblk_qseed3_3_0, 71 .xin_id = 0, 72 .type = SSPP_TYPE_VIG, 73 .clk_ctrl = DPU_CLK_CTRL_VIG0, 74 }, { 75 .name = "sspp_1", .id = SSPP_VIG1, 76 .base = 0x6000, .len = 0x2ac, 77 .features = VIG_SDM845_MASK_SDMA, 78 .sblk = &dpu_vig_sblk_qseed3_3_0, 79 .xin_id = 4, 80 .type = SSPP_TYPE_VIG, 81 .clk_ctrl = DPU_CLK_CTRL_VIG1, 82 }, { 83 .name = "sspp_2", .id = SSPP_VIG2, 84 .base = 0x8000, .len = 0x2ac, 85 .features = VIG_SDM845_MASK_SDMA, 86 .sblk = &dpu_vig_sblk_qseed3_3_0, 87 .xin_id = 8, 88 .type = SSPP_TYPE_VIG, 89 .clk_ctrl = DPU_CLK_CTRL_VIG2, 90 }, { 91 .name = "sspp_3", .id = SSPP_VIG3, 92 .base = 0xa000, .len = 0x2ac, 93 .features = VIG_SDM845_MASK_SDMA, 94 .sblk = &dpu_vig_sblk_qseed3_3_0, 95 .xin_id = 12, 96 .type = SSPP_TYPE_VIG, 97 .clk_ctrl = DPU_CLK_CTRL_VIG3, 98 }, { 99 .name = "sspp_8", .id = SSPP_DMA0, 100 .base = 0x24000, .len = 0x2ac, 101 .features = DMA_SDM845_MASK_SDMA, 102 .sblk = &dpu_dma_sblk, 103 .xin_id = 1, 104 .type = SSPP_TYPE_DMA, 105 .clk_ctrl = DPU_CLK_CTRL_DMA0, 106 }, { 107 .name = "sspp_9", .id = SSPP_DMA1, 108 .base = 0x26000, .len = 0x2ac, 109 .features = DMA_SDM845_MASK_SDMA, 110 .sblk = &dpu_dma_sblk, 111 .xin_id = 5, 112 .type = SSPP_TYPE_DMA, 113 .clk_ctrl = DPU_CLK_CTRL_DMA1, 114 }, { 115 .name = "sspp_10", .id = SSPP_DMA2, 116 .base = 0x28000, .len = 0x2ac, 117 .features = DMA_CURSOR_SDM845_MASK_SDMA, 118 .sblk = &dpu_dma_sblk, 119 .xin_id = 9, 120 .type = SSPP_TYPE_DMA, 121 .clk_ctrl = DPU_CLK_CTRL_DMA2, 122 }, { 123 .name = "sspp_11", .id = SSPP_DMA3, 124 .base = 0x2a000, .len = 0x2ac, 125 .features = DMA_CURSOR_SDM845_MASK_SDMA, 126 .sblk = &dpu_dma_sblk, 127 .xin_id = 13, 128 .type = SSPP_TYPE_DMA, 129 .clk_ctrl = DPU_CLK_CTRL_DMA3, 130 }, 131 }; 132 133 static const struct dpu_lm_cfg sc8280xp_lm[] = { 134 { 135 .name = "lm_0", .id = LM_0, 136 .base = 0x44000, .len = 0x320, 137 .features = MIXER_MSM8998_MASK, 138 .sblk = &sdm845_lm_sblk, 139 .lm_pair = LM_1, 140 .pingpong = PINGPONG_0, 141 .dspp = DSPP_0, 142 }, { 143 .name = "lm_1", .id = LM_1, 144 .base = 0x45000, .len = 0x320, 145 .features = MIXER_MSM8998_MASK, 146 .sblk = &sdm845_lm_sblk, 147 .lm_pair = LM_0, 148 .pingpong = PINGPONG_1, 149 .dspp = DSPP_1, 150 }, { 151 .name = "lm_2", .id = LM_2, 152 .base = 0x46000, .len = 0x320, 153 .features = MIXER_MSM8998_MASK, 154 .sblk = &sdm845_lm_sblk, 155 .lm_pair = LM_3, 156 .pingpong = PINGPONG_2, 157 .dspp = DSPP_2, 158 }, { 159 .name = "lm_3", .id = LM_3, 160 .base = 0x47000, .len = 0x320, 161 .features = MIXER_MSM8998_MASK, 162 .sblk = &sdm845_lm_sblk, 163 .lm_pair = LM_2, 164 .pingpong = PINGPONG_3, 165 .dspp = DSPP_3, 166 }, { 167 .name = "lm_4", .id = LM_4, 168 .base = 0x48000, .len = 0x320, 169 .features = MIXER_MSM8998_MASK, 170 .sblk = &sdm845_lm_sblk, 171 .lm_pair = LM_5, 172 .pingpong = PINGPONG_4, 173 }, { 174 .name = "lm_5", .id = LM_5, 175 .base = 0x49000, .len = 0x320, 176 .features = MIXER_MSM8998_MASK, 177 .sblk = &sdm845_lm_sblk, 178 .lm_pair = LM_4, 179 .pingpong = PINGPONG_5, 180 }, 181 }; 182 183 static const struct dpu_dspp_cfg sc8280xp_dspp[] = { 184 { 185 .name = "dspp_0", .id = DSPP_0, 186 .base = 0x54000, .len = 0x1800, 187 .sblk = &sdm845_dspp_sblk, 188 }, { 189 .name = "dspp_1", .id = DSPP_1, 190 .base = 0x56000, .len = 0x1800, 191 .sblk = &sdm845_dspp_sblk, 192 }, { 193 .name = "dspp_2", .id = DSPP_2, 194 .base = 0x58000, .len = 0x1800, 195 .sblk = &sdm845_dspp_sblk, 196 }, { 197 .name = "dspp_3", .id = DSPP_3, 198 .base = 0x5a000, .len = 0x1800, 199 .sblk = &sdm845_dspp_sblk, 200 }, 201 }; 202 203 static const struct dpu_pingpong_cfg sc8280xp_pp[] = { 204 { 205 .name = "pingpong_0", .id = PINGPONG_0, 206 .base = 0x69000, .len = 0, 207 .sblk = &sc7280_pp_sblk, 208 .merge_3d = MERGE_3D_0, 209 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 210 }, { 211 .name = "pingpong_1", .id = PINGPONG_1, 212 .base = 0x6a000, .len = 0, 213 .sblk = &sc7280_pp_sblk, 214 .merge_3d = MERGE_3D_0, 215 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 216 }, { 217 .name = "pingpong_2", .id = PINGPONG_2, 218 .base = 0x6b000, .len = 0, 219 .sblk = &sc7280_pp_sblk, 220 .merge_3d = MERGE_3D_1, 221 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 222 }, { 223 .name = "pingpong_3", .id = PINGPONG_3, 224 .base = 0x6c000, .len = 0, 225 .sblk = &sc7280_pp_sblk, 226 .merge_3d = MERGE_3D_1, 227 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 228 }, { 229 .name = "pingpong_4", .id = PINGPONG_4, 230 .base = 0x6d000, .len = 0, 231 .sblk = &sc7280_pp_sblk, 232 .merge_3d = MERGE_3D_2, 233 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), 234 }, { 235 .name = "pingpong_5", .id = PINGPONG_5, 236 .base = 0x6e000, .len = 0, 237 .sblk = &sc7280_pp_sblk, 238 .merge_3d = MERGE_3D_2, 239 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), 240 }, 241 }; 242 243 static const struct dpu_merge_3d_cfg sc8280xp_merge_3d[] = { 244 { 245 .name = "merge_3d_0", .id = MERGE_3D_0, 246 .base = 0x4e000, .len = 0x8, 247 }, { 248 .name = "merge_3d_1", .id = MERGE_3D_1, 249 .base = 0x4f000, .len = 0x8, 250 }, { 251 .name = "merge_3d_2", .id = MERGE_3D_2, 252 .base = 0x50000, .len = 0x8, 253 }, 254 }; 255 256 /* 257 * NOTE: Each display compression engine (DCE) contains dual hard 258 * slice DSC encoders so both share same base address but with 259 * its own different sub block address. 260 */ 261 static const struct dpu_dsc_cfg sc8280xp_dsc[] = { 262 { 263 .name = "dce_0_0", .id = DSC_0, 264 .base = 0x80000, .len = 0x4, 265 .sblk = &dsc_sblk_0, 266 }, { 267 .name = "dce_0_1", .id = DSC_1, 268 .base = 0x80000, .len = 0x4, 269 .sblk = &dsc_sblk_1, 270 }, { 271 .name = "dce_1_0", .id = DSC_2, 272 .base = 0x81000, .len = 0x4, 273 .features = BIT(DPU_DSC_NATIVE_42x_EN), 274 .sblk = &dsc_sblk_0, 275 }, { 276 .name = "dce_1_1", .id = DSC_3, 277 .base = 0x81000, .len = 0x4, 278 .features = BIT(DPU_DSC_NATIVE_42x_EN), 279 .sblk = &dsc_sblk_1, 280 }, { 281 .name = "dce_2_0", .id = DSC_4, 282 .base = 0x82000, .len = 0x4, 283 .sblk = &dsc_sblk_0, 284 }, { 285 .name = "dce_2_1", .id = DSC_5, 286 .base = 0x82000, .len = 0x4, 287 .sblk = &dsc_sblk_1, 288 }, 289 }; 290 291 /* TODO: INTF 3, 8 and 7 are used for MST, marked as INTF_NONE for now */ 292 static const struct dpu_intf_cfg sc8280xp_intf[] = { 293 { 294 .name = "intf_0", .id = INTF_0, 295 .base = 0x34000, .len = 0x280, 296 .type = INTF_DP, 297 .controller_id = MSM_DP_CONTROLLER_0, 298 .prog_fetch_lines_worst_case = 24, 299 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 300 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), 301 }, { 302 .name = "intf_1", .id = INTF_1, 303 .base = 0x35000, .len = 0x300, 304 .type = INTF_DSI, 305 .controller_id = MSM_DSI_CONTROLLER_0, 306 .prog_fetch_lines_worst_case = 24, 307 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 308 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 309 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), 310 }, { 311 .name = "intf_2", .id = INTF_2, 312 .base = 0x36000, .len = 0x300, 313 .type = INTF_DSI, 314 .controller_id = MSM_DSI_CONTROLLER_1, 315 .prog_fetch_lines_worst_case = 24, 316 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), 317 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), 318 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), 319 }, { 320 .name = "intf_3", .id = INTF_3, 321 .base = 0x37000, .len = 0x280, 322 .type = INTF_NONE, 323 .controller_id = MSM_DP_CONTROLLER_0, 324 .prog_fetch_lines_worst_case = 24, 325 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), 326 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), 327 }, { 328 .name = "intf_4", .id = INTF_4, 329 .base = 0x38000, .len = 0x280, 330 .type = INTF_DP, 331 .controller_id = MSM_DP_CONTROLLER_1, 332 .prog_fetch_lines_worst_case = 24, 333 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20), 334 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21), 335 }, { 336 .name = "intf_5", .id = INTF_5, 337 .base = 0x39000, .len = 0x280, 338 .type = INTF_DP, 339 .controller_id = MSM_DP_CONTROLLER_3, 340 .prog_fetch_lines_worst_case = 24, 341 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22), 342 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23), 343 }, { 344 .name = "intf_6", .id = INTF_6, 345 .base = 0x3a000, .len = 0x280, 346 .type = INTF_DP, 347 .controller_id = MSM_DP_CONTROLLER_2, 348 .prog_fetch_lines_worst_case = 24, 349 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16), 350 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17), 351 }, { 352 .name = "intf_7", .id = INTF_7, 353 .base = 0x3b000, .len = 0x280, 354 .type = INTF_NONE, 355 .controller_id = MSM_DP_CONTROLLER_2, 356 .prog_fetch_lines_worst_case = 24, 357 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18), 358 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 19), 359 }, { 360 .name = "intf_8", .id = INTF_8, 361 .base = 0x3c000, .len = 0x280, 362 .type = INTF_NONE, 363 .controller_id = MSM_DP_CONTROLLER_1, 364 .prog_fetch_lines_worst_case = 24, 365 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), 366 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), 367 }, 368 }; 369 370 static const struct dpu_perf_cfg sc8280xp_perf_data = { 371 .max_bw_low = 13600000, 372 .max_bw_high = 18200000, 373 .min_core_ib = 2500000, 374 .min_llcc_ib = 0, 375 .min_dram_ib = 800000, 376 .danger_lut_tbl = {0xf, 0xffff, 0x0}, 377 .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff}, 378 .qos_lut_tbl = { 379 {.nentry = ARRAY_SIZE(sc8180x_qos_linear), 380 .entries = sc8180x_qos_linear 381 }, 382 {.nentry = ARRAY_SIZE(sc8180x_qos_macrotile), 383 .entries = sc8180x_qos_macrotile 384 }, 385 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 386 .entries = sc7180_qos_nrt 387 }, 388 /* TODO: macrotile-qseed is different from macrotile */ 389 }, 390 .cdp_cfg = { 391 {.rd_enable = 1, .wr_enable = 1}, 392 {.rd_enable = 1, .wr_enable = 0} 393 }, 394 .clk_inefficiency_factor = 105, 395 .bw_inefficiency_factor = 120, 396 }; 397 398 static const struct dpu_mdss_version sc8280xp_mdss_ver = { 399 .core_major_ver = 8, 400 .core_minor_ver = 0, 401 }; 402 403 const struct dpu_mdss_cfg dpu_sc8280xp_cfg = { 404 .mdss_ver = &sc8280xp_mdss_ver, 405 .caps = &sc8280xp_dpu_caps, 406 .mdp = &sc8280xp_mdp, 407 .cdm = &dpu_cdm_5_x, 408 .ctl_count = ARRAY_SIZE(sc8280xp_ctl), 409 .ctl = sc8280xp_ctl, 410 .sspp_count = ARRAY_SIZE(sc8280xp_sspp), 411 .sspp = sc8280xp_sspp, 412 .mixer_count = ARRAY_SIZE(sc8280xp_lm), 413 .mixer = sc8280xp_lm, 414 .dspp_count = ARRAY_SIZE(sc8280xp_dspp), 415 .dspp = sc8280xp_dspp, 416 .pingpong_count = ARRAY_SIZE(sc8280xp_pp), 417 .pingpong = sc8280xp_pp, 418 .dsc_count = ARRAY_SIZE(sc8280xp_dsc), 419 .dsc = sc8280xp_dsc, 420 .merge_3d_count = ARRAY_SIZE(sc8280xp_merge_3d), 421 .merge_3d = sc8280xp_merge_3d, 422 .intf_count = ARRAY_SIZE(sc8280xp_intf), 423 .intf = sc8280xp_intf, 424 .vbif_count = ARRAY_SIZE(sdm845_vbif), 425 .vbif = sdm845_vbif, 426 .perf = &sc8280xp_perf_data, 427 }; 428 429 #endif 430