1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_7_2_SC7280_H 8 #define _DPU_7_2_SC7280_H 9 10 static const struct dpu_caps sc7280_dpu_caps = { 11 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 12 .max_mixer_blendstages = 0x7, 13 .has_dim_layer = true, 14 .has_idle_pc = true, 15 .max_linewidth = 2400, 16 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 17 }; 18 19 static const struct dpu_mdp_cfg sc7280_mdp = { 20 .name = "top_0", 21 .base = 0x0, .len = 0x2014, 22 .clk_ctrls = { 23 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 24 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 25 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 26 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, 27 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 }, 28 }, 29 }; 30 31 static const struct dpu_ctl_cfg sc7280_ctl[] = { 32 { 33 .name = "ctl_0", .id = CTL_0, 34 .base = 0x15000, .len = 0x1e8, 35 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 36 }, { 37 .name = "ctl_1", .id = CTL_1, 38 .base = 0x16000, .len = 0x1e8, 39 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 40 }, { 41 .name = "ctl_2", .id = CTL_2, 42 .base = 0x17000, .len = 0x1e8, 43 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 44 }, { 45 .name = "ctl_3", .id = CTL_3, 46 .base = 0x18000, .len = 0x1e8, 47 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 48 }, 49 }; 50 51 static const struct dpu_sspp_cfg sc7280_sspp[] = { 52 { 53 .name = "sspp_0", .id = SSPP_VIG0, 54 .base = 0x4000, .len = 0x1f8, 55 .features = VIG_SC7280_MASK_SDMA, 56 .sblk = &dpu_vig_sblk_qseed3_3_0_rot_v2, 57 .xin_id = 0, 58 .type = SSPP_TYPE_VIG, 59 .clk_ctrl = DPU_CLK_CTRL_VIG0, 60 }, { 61 .name = "sspp_8", .id = SSPP_DMA0, 62 .base = 0x24000, .len = 0x1f8, 63 .features = DMA_SDM845_MASK_SDMA, 64 .sblk = &dpu_dma_sblk, 65 .xin_id = 1, 66 .type = SSPP_TYPE_DMA, 67 .clk_ctrl = DPU_CLK_CTRL_DMA0, 68 }, { 69 .name = "sspp_9", .id = SSPP_DMA1, 70 .base = 0x26000, .len = 0x1f8, 71 .features = DMA_CURSOR_SDM845_MASK_SDMA, 72 .sblk = &dpu_dma_sblk, 73 .xin_id = 5, 74 .type = SSPP_TYPE_DMA, 75 .clk_ctrl = DPU_CLK_CTRL_DMA1, 76 }, { 77 .name = "sspp_10", .id = SSPP_DMA2, 78 .base = 0x28000, .len = 0x1f8, 79 .features = DMA_CURSOR_SDM845_MASK_SDMA, 80 .sblk = &dpu_dma_sblk, 81 .xin_id = 9, 82 .type = SSPP_TYPE_DMA, 83 .clk_ctrl = DPU_CLK_CTRL_DMA2, 84 }, 85 }; 86 87 static const struct dpu_lm_cfg sc7280_lm[] = { 88 { 89 .name = "lm_0", .id = LM_0, 90 .base = 0x44000, .len = 0x320, 91 .features = MIXER_MSM8998_MASK, 92 .sblk = &sc7180_lm_sblk, 93 .pingpong = PINGPONG_0, 94 .dspp = DSPP_0, 95 }, { 96 .name = "lm_2", .id = LM_2, 97 .base = 0x46000, .len = 0x320, 98 .features = MIXER_MSM8998_MASK, 99 .sblk = &sc7180_lm_sblk, 100 .lm_pair = LM_3, 101 .pingpong = PINGPONG_2, 102 }, { 103 .name = "lm_3", .id = LM_3, 104 .base = 0x47000, .len = 0x320, 105 .features = MIXER_MSM8998_MASK, 106 .sblk = &sc7180_lm_sblk, 107 .lm_pair = LM_2, 108 .pingpong = PINGPONG_3, 109 }, 110 }; 111 112 static const struct dpu_dspp_cfg sc7280_dspp[] = { 113 { 114 .name = "dspp_0", .id = DSPP_0, 115 .base = 0x54000, .len = 0x1800, 116 .sblk = &sdm845_dspp_sblk, 117 }, 118 }; 119 120 static const struct dpu_pingpong_cfg sc7280_pp[] = { 121 { 122 .name = "pingpong_0", .id = PINGPONG_0, 123 .base = 0x69000, .len = 0, 124 .sblk = &sc7280_pp_sblk, 125 .merge_3d = 0, 126 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 127 }, { 128 .name = "pingpong_1", .id = PINGPONG_1, 129 .base = 0x6a000, .len = 0, 130 .sblk = &sc7280_pp_sblk, 131 .merge_3d = 0, 132 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 133 }, { 134 .name = "pingpong_2", .id = PINGPONG_2, 135 .base = 0x6b000, .len = 0, 136 .sblk = &sc7280_pp_sblk, 137 .merge_3d = 0, 138 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 139 }, { 140 .name = "pingpong_3", .id = PINGPONG_3, 141 .base = 0x6c000, .len = 0, 142 .sblk = &sc7280_pp_sblk, 143 .merge_3d = 0, 144 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 145 }, 146 }; 147 148 /* NOTE: sc7280 only has one DSC hard slice encoder */ 149 static const struct dpu_dsc_cfg sc7280_dsc[] = { 150 { 151 .name = "dce_0_0", .id = DSC_0, 152 .base = 0x80000, .len = 0x4, 153 .features = BIT(DPU_DSC_NATIVE_42x_EN), 154 .sblk = &dsc_sblk_0, 155 }, 156 }; 157 158 static const struct dpu_wb_cfg sc7280_wb[] = { 159 { 160 .name = "wb_2", .id = WB_2, 161 .base = 0x65000, .len = 0x2c8, 162 .features = WB_SDM845_MASK, 163 .format_list = wb2_formats_rgb_yuv, 164 .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), 165 .clk_ctrl = DPU_CLK_CTRL_WB2, 166 .xin_id = 6, 167 .vbif_idx = VBIF_RT, 168 .maxlinewidth = 4096, 169 .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), 170 }, 171 }; 172 173 static const struct dpu_intf_cfg sc7280_intf[] = { 174 { 175 .name = "intf_0", .id = INTF_0, 176 .base = 0x34000, .len = 0x280, 177 .type = INTF_DP, 178 .controller_id = MSM_DP_CONTROLLER_0, 179 .prog_fetch_lines_worst_case = 24, 180 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 181 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), 182 }, { 183 .name = "intf_1", .id = INTF_1, 184 .base = 0x35000, .len = 0x2c4, 185 .type = INTF_DSI, 186 .controller_id = MSM_DSI_CONTROLLER_0, 187 .prog_fetch_lines_worst_case = 24, 188 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 189 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 190 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), 191 }, { 192 .name = "intf_5", .id = INTF_5, 193 .base = 0x39000, .len = 0x280, 194 .type = INTF_DP, 195 .controller_id = MSM_DP_CONTROLLER_1, 196 .prog_fetch_lines_worst_case = 24, 197 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22), 198 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23), 199 }, 200 }; 201 202 static const struct dpu_perf_cfg sc7280_perf_data = { 203 .max_bw_low = 4700000, 204 .max_bw_high = 8800000, 205 .min_core_ib = 2500000, 206 .min_llcc_ib = 0, 207 .min_dram_ib = 1600000, 208 .min_prefill_lines = 24, 209 .danger_lut_tbl = {0xffff, 0xffff, 0x0}, 210 .safe_lut_tbl = {0xff00, 0xff00, 0xffff}, 211 .qos_lut_tbl = { 212 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 213 .entries = sc7180_qos_macrotile 214 }, 215 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 216 .entries = sc7180_qos_macrotile 217 }, 218 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 219 .entries = sc7180_qos_nrt 220 }, 221 }, 222 .cdp_cfg = { 223 {.rd_enable = 1, .wr_enable = 1}, 224 {.rd_enable = 1, .wr_enable = 0} 225 }, 226 .clk_inefficiency_factor = 105, 227 .bw_inefficiency_factor = 120, 228 }; 229 230 static const struct dpu_mdss_version sc7280_mdss_ver = { 231 .core_major_ver = 7, 232 .core_minor_ver = 2, 233 }; 234 235 const struct dpu_mdss_cfg dpu_sc7280_cfg = { 236 .mdss_ver = &sc7280_mdss_ver, 237 .caps = &sc7280_dpu_caps, 238 .mdp = &sc7280_mdp, 239 .cdm = &dpu_cdm_5_x, 240 .ctl_count = ARRAY_SIZE(sc7280_ctl), 241 .ctl = sc7280_ctl, 242 .sspp_count = ARRAY_SIZE(sc7280_sspp), 243 .sspp = sc7280_sspp, 244 .dspp_count = ARRAY_SIZE(sc7280_dspp), 245 .dspp = sc7280_dspp, 246 .mixer_count = ARRAY_SIZE(sc7280_lm), 247 .mixer = sc7280_lm, 248 .pingpong_count = ARRAY_SIZE(sc7280_pp), 249 .pingpong = sc7280_pp, 250 .dsc_count = ARRAY_SIZE(sc7280_dsc), 251 .dsc = sc7280_dsc, 252 .wb_count = ARRAY_SIZE(sc7280_wb), 253 .wb = sc7280_wb, 254 .intf_count = ARRAY_SIZE(sc7280_intf), 255 .intf = sc7280_intf, 256 .vbif_count = ARRAY_SIZE(sdm845_vbif), 257 .vbif = sdm845_vbif, 258 .perf = &sc7280_perf_data, 259 }; 260 261 #endif 262