1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com> 5 */ 6 7 #ifndef _DPU_5_2_SM7150_H 8 #define _DPU_5_2_SM7150_H 9 10 static const struct dpu_caps sm7150_dpu_caps = { 11 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 12 .max_mixer_blendstages = 0xb, 13 .has_src_split = true, 14 .has_dim_layer = true, 15 .has_idle_pc = true, 16 .has_3d_merge = true, 17 .max_linewidth = 2880, 18 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 19 .max_hdeci_exp = MAX_HORZ_DECIMATION, 20 .max_vdeci_exp = MAX_VERT_DECIMATION, 21 }; 22 23 static const struct dpu_mdp_cfg sm7150_mdp = { 24 .name = "top_0", 25 .base = 0x0, .len = 0x45c, 26 .clk_ctrls = { 27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 28 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, 29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 31 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, 32 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 }, 33 }, 34 }; 35 36 static const struct dpu_ctl_cfg sm7150_ctl[] = { 37 { 38 .name = "ctl_0", .id = CTL_0, 39 .base = 0x1000, .len = 0x1e0, 40 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 41 }, { 42 .name = "ctl_1", .id = CTL_1, 43 .base = 0x1200, .len = 0x1e0, 44 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 45 }, { 46 .name = "ctl_2", .id = CTL_2, 47 .base = 0x1400, .len = 0x1e0, 48 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 49 }, { 50 .name = "ctl_3", .id = CTL_3, 51 .base = 0x1600, .len = 0x1e0, 52 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 53 }, { 54 .name = "ctl_4", .id = CTL_4, 55 .base = 0x1800, .len = 0x1e0, 56 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 57 }, { 58 .name = "ctl_5", .id = CTL_5, 59 .base = 0x1a00, .len = 0x1e0, 60 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), 61 }, 62 }; 63 64 static const struct dpu_sspp_cfg sm7150_sspp[] = { 65 { 66 .name = "sspp_0", .id = SSPP_VIG0, 67 .base = 0x4000, .len = 0x1f0, 68 .features = VIG_SDM845_MASK_NO_SDMA, 69 .sblk = &dpu_vig_sblk_qseed3_2_4, 70 .xin_id = 0, 71 .type = SSPP_TYPE_VIG, 72 .clk_ctrl = DPU_CLK_CTRL_VIG0, 73 }, { 74 .name = "sspp_1", .id = SSPP_VIG1, 75 .base = 0x6000, .len = 0x1f0, 76 .features = VIG_SDM845_MASK_NO_SDMA, 77 .sblk = &dpu_vig_sblk_qseed3_2_4, 78 .xin_id = 4, 79 .type = SSPP_TYPE_VIG, 80 .clk_ctrl = DPU_CLK_CTRL_VIG1, 81 }, { 82 .name = "sspp_2", .id = SSPP_DMA0, 83 .base = 0x24000, .len = 0x1f0, 84 .features = DMA_SDM845_MASK_NO_SDMA, 85 .sblk = &dpu_dma_sblk, 86 .xin_id = 1, 87 .type = SSPP_TYPE_DMA, 88 .clk_ctrl = DPU_CLK_CTRL_DMA0, 89 }, { 90 .name = "sspp_9", .id = SSPP_DMA1, 91 .base = 0x26000, .len = 0x1f0, 92 .features = DMA_SDM845_MASK_NO_SDMA, 93 .sblk = &dpu_dma_sblk, 94 .xin_id = 5, 95 .type = SSPP_TYPE_DMA, 96 .clk_ctrl = DPU_CLK_CTRL_DMA1, 97 }, { 98 .name = "sspp_10", .id = SSPP_DMA2, 99 .base = 0x28000, .len = 0x1f0, 100 .features = DMA_CURSOR_SDM845_MASK_NO_SDMA, 101 .sblk = &dpu_dma_sblk, 102 .xin_id = 9, 103 .type = SSPP_TYPE_DMA, 104 .clk_ctrl = DPU_CLK_CTRL_DMA2, 105 }, 106 }; 107 108 static const struct dpu_lm_cfg sm7150_lm[] = { 109 { 110 .name = "lm_0", .id = LM_0, 111 .base = 0x44000, .len = 0x320, 112 .features = MIXER_MSM8998_MASK, 113 .sblk = &sdm845_lm_sblk, 114 .lm_pair = LM_1, 115 .pingpong = PINGPONG_0, 116 .dspp = DSPP_0, 117 }, { 118 .name = "lm_1", .id = LM_1, 119 .base = 0x45000, .len = 0x320, 120 .features = MIXER_MSM8998_MASK, 121 .sblk = &sdm845_lm_sblk, 122 .lm_pair = LM_0, 123 .pingpong = PINGPONG_1, 124 .dspp = DSPP_1, 125 }, { 126 .name = "lm_2", .id = LM_2, 127 .base = 0x46000, .len = 0x320, 128 .features = MIXER_MSM8998_MASK, 129 .sblk = &sdm845_lm_sblk, 130 .lm_pair = LM_3, 131 .pingpong = PINGPONG_2, 132 }, { 133 .name = "lm_3", .id = LM_3, 134 .base = 0x47000, .len = 0x320, 135 .features = MIXER_MSM8998_MASK, 136 .sblk = &sdm845_lm_sblk, 137 .lm_pair = LM_2, 138 .pingpong = PINGPONG_3, 139 }, 140 }; 141 142 static const struct dpu_dspp_cfg sm7150_dspp[] = { 143 { 144 .name = "dspp_0", .id = DSPP_0, 145 .base = 0x54000, .len = 0x1800, 146 .sblk = &sdm845_dspp_sblk, 147 }, { 148 .name = "dspp_1", .id = DSPP_1, 149 .base = 0x56000, .len = 0x1800, 150 .sblk = &sdm845_dspp_sblk, 151 }, 152 }; 153 154 static const struct dpu_pingpong_cfg sm7150_pp[] = { 155 { 156 .name = "pingpong_0", .id = PINGPONG_0, 157 .base = 0x70000, .len = 0xd4, 158 .sblk = &sdm845_pp_sblk, 159 .merge_3d = MERGE_3D_0, 160 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 161 }, { 162 .name = "pingpong_1", .id = PINGPONG_1, 163 .base = 0x70800, .len = 0xd4, 164 .sblk = &sdm845_pp_sblk, 165 .merge_3d = MERGE_3D_0, 166 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 167 }, { 168 .name = "pingpong_2", .id = PINGPONG_2, 169 .base = 0x71000, .len = 0xd4, 170 .sblk = &sdm845_pp_sblk, 171 .merge_3d = MERGE_3D_1, 172 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 173 }, { 174 .name = "pingpong_3", .id = PINGPONG_3, 175 .base = 0x71800, .len = 0xd4, 176 .sblk = &sdm845_pp_sblk, 177 .merge_3d = MERGE_3D_1, 178 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 179 }, 180 }; 181 182 static const struct dpu_merge_3d_cfg sm7150_merge_3d[] = { 183 { 184 .name = "merge_3d_0", .id = MERGE_3D_0, 185 .base = 0x83000, .len = 0x8, 186 }, { 187 .name = "merge_3d_1", .id = MERGE_3D_1, 188 .base = 0x83100, .len = 0x8, 189 }, 190 }; 191 192 static const struct dpu_dsc_cfg sm7150_dsc[] = { 193 { 194 .name = "dsc_0", .id = DSC_0, 195 .base = 0x80000, .len = 0x140, 196 }, { 197 .name = "dsc_1", .id = DSC_1, 198 .base = 0x80400, .len = 0x140, 199 }, 200 }; 201 202 static const struct dpu_intf_cfg sm7150_intf[] = { 203 { 204 .name = "intf_0", .id = INTF_0, 205 .base = 0x6a000, .len = 0x280, 206 .type = INTF_DP, 207 .controller_id = MSM_DP_CONTROLLER_0, 208 .prog_fetch_lines_worst_case = 24, 209 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 210 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), 211 }, { 212 .name = "intf_1", .id = INTF_1, 213 .base = 0x6a800, .len = 0x2bc, 214 .type = INTF_DSI, 215 .controller_id = MSM_DSI_CONTROLLER_0, 216 .prog_fetch_lines_worst_case = 24, 217 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 218 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 219 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), 220 }, { 221 .name = "intf_2", .id = INTF_2, 222 .base = 0x6b000, .len = 0x2bc, 223 .type = INTF_DSI, 224 .controller_id = MSM_DSI_CONTROLLER_1, 225 .prog_fetch_lines_worst_case = 24, 226 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), 227 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), 228 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), 229 }, { 230 .name = "intf_3", .id = INTF_3, 231 .base = 0x6b800, .len = 0x280, 232 .type = INTF_DP, 233 .controller_id = MSM_DP_CONTROLLER_1, 234 .prog_fetch_lines_worst_case = 24, 235 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), 236 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), 237 }, 238 }; 239 240 static const struct dpu_wb_cfg sm7150_wb[] = { 241 { 242 .name = "wb_2", .id = WB_2, 243 .base = 0x65000, .len = 0x2c8, 244 .features = WB_SDM845_MASK, 245 .format_list = wb2_formats_rgb_yuv, 246 .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv), 247 .clk_ctrl = DPU_CLK_CTRL_WB2, 248 .xin_id = 6, 249 .vbif_idx = VBIF_RT, 250 .maxlinewidth = 4096, 251 .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), 252 }, 253 }; 254 255 static const struct dpu_perf_cfg sm7150_perf_data = { 256 .max_bw_low = 7100000, 257 .max_bw_high = 7100000, 258 .min_core_ib = 2400000, 259 .min_llcc_ib = 800000, 260 .min_dram_ib = 800000, 261 .min_prefill_lines = 24, 262 .danger_lut_tbl = {0xf, 0xffff, 0x0}, 263 .safe_lut_tbl = {0xfff8, 0xf000, 0xffff}, 264 .qos_lut_tbl = { 265 { 266 .nentry = ARRAY_SIZE(sm8150_qos_linear), 267 .entries = sm8150_qos_linear 268 }, { 269 .nentry = ARRAY_SIZE(sc7180_qos_macrotile), 270 .entries = sc7180_qos_macrotile 271 }, { 272 .nentry = ARRAY_SIZE(sc7180_qos_nrt), 273 .entries = sc7180_qos_nrt 274 }, 275 }, 276 .cdp_cfg = { 277 {.rd_enable = 1, .wr_enable = 1}, 278 {.rd_enable = 1, .wr_enable = 0} 279 }, 280 .clk_inefficiency_factor = 105, 281 .bw_inefficiency_factor = 120, 282 }; 283 284 static const struct dpu_mdss_version sm7150_mdss_ver = { 285 .core_major_ver = 5, 286 .core_minor_ver = 2, 287 }; 288 289 const struct dpu_mdss_cfg dpu_sm7150_cfg = { 290 .mdss_ver = &sm7150_mdss_ver, 291 .caps = &sm7150_dpu_caps, 292 .mdp = &sm7150_mdp, 293 .cdm = &dpu_cdm_5_x, 294 .ctl_count = ARRAY_SIZE(sm7150_ctl), 295 .ctl = sm7150_ctl, 296 .sspp_count = ARRAY_SIZE(sm7150_sspp), 297 .sspp = sm7150_sspp, 298 .mixer_count = ARRAY_SIZE(sm7150_lm), 299 .mixer = sm7150_lm, 300 .dspp_count = ARRAY_SIZE(sm7150_dspp), 301 .dspp = sm7150_dspp, 302 .pingpong_count = ARRAY_SIZE(sm7150_pp), 303 .pingpong = sm7150_pp, 304 .merge_3d_count = ARRAY_SIZE(sm7150_merge_3d), 305 .merge_3d = sm7150_merge_3d, 306 .dsc_count = ARRAY_SIZE(sm7150_dsc), 307 .dsc = sm7150_dsc, 308 .intf_count = ARRAY_SIZE(sm7150_intf), 309 .intf = sm7150_intf, 310 .wb_count = ARRAY_SIZE(sm7150_wb), 311 .wb = sm7150_wb, 312 .vbif_count = ARRAY_SIZE(sdm845_vbif), 313 .vbif = sdm845_vbif, 314 .perf = &sm7150_perf_data, 315 }; 316 317 #endif 318