1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * camss-csid-4-1.c
4 *
5 * Qualcomm MSM Camera Subsystem - CSID (CSI Decoder) Module
6 *
7 * Copyright (C) 2020 Linaro Ltd.
8 */
9
10 #include <linux/completion.h>
11 #include <linux/interrupt.h>
12 #include <linux/io.h>
13 #include <linux/kernel.h>
14 #include <linux/of.h>
15
16 #include "camss-csid.h"
17 #include "camss-csid-gen1.h"
18 #include "camss.h"
19
20 #define CAMSS_CSID_CORE_CTRL_0 0x004
21 #define CAMSS_CSID_CORE_CTRL_1 0x008
22 #define CAMSS_CSID_RST_CMD 0x00c
23 #define CAMSS_CSID_CID_LUT_VC_n(n) (0x010 + 0x4 * (n))
24 #define CAMSS_CSID_CID_n_CFG(n) (0x020 + 0x4 * (n))
25 #define CAMSS_CSID_CID_n_CFG_ISPIF_EN BIT(0)
26 #define CAMSS_CSID_CID_n_CFG_RDI_EN BIT(1)
27 #define CAMSS_CSID_CID_n_CFG_DECODE_FORMAT_SHIFT 4
28 #define CAMSS_CSID_CID_n_CFG_PLAIN_FORMAT_8 (PLAIN_FORMAT_PLAIN8 << 8)
29 #define CAMSS_CSID_CID_n_CFG_PLAIN_FORMAT_16 (PLAIN_FORMAT_PLAIN16 << 8)
30 #define CAMSS_CSID_CID_n_CFG_PLAIN_ALIGNMENT_LSB (0 << 9)
31 #define CAMSS_CSID_CID_n_CFG_PLAIN_ALIGNMENT_MSB (1 << 9)
32 #define CAMSS_CSID_CID_n_CFG_RDI_MODE_RAW_DUMP (0 << 10)
33 #define CAMSS_CSID_CID_n_CFG_RDI_MODE_PLAIN_PACKING (1 << 10)
34 #define CAMSS_CSID_IRQ_CLEAR_CMD 0x060
35 #define CAMSS_CSID_IRQ_MASK 0x064
36 #define CAMSS_CSID_IRQ_STATUS 0x068
37 #define CAMSS_CSID_TG_CTRL 0x0a0
38 #define CAMSS_CSID_TG_CTRL_DISABLE 0xa06436
39 #define CAMSS_CSID_TG_CTRL_ENABLE 0xa06437
40 #define CAMSS_CSID_TG_VC_CFG 0x0a4
41 #define CAMSS_CSID_TG_VC_CFG_H_BLANKING 0x3ff
42 #define CAMSS_CSID_TG_VC_CFG_V_BLANKING 0x7f
43 #define CAMSS_CSID_TG_DT_n_CGG_0(n) (0x0ac + 0xc * (n))
44 #define CAMSS_CSID_TG_DT_n_CGG_1(n) (0x0b0 + 0xc * (n))
45 #define CAMSS_CSID_TG_DT_n_CGG_2(n) (0x0b4 + 0xc * (n))
46
csid_configure_stream(struct csid_device * csid,u8 enable)47 static void csid_configure_stream(struct csid_device *csid, u8 enable)
48 {
49 struct csid_testgen_config *tg = &csid->testgen;
50 u32 val;
51
52 if (enable) {
53 struct v4l2_mbus_framefmt *input_format;
54 const struct csid_format_info *format;
55 u8 vc = 0; /* Virtual Channel 0 */
56 u8 cid = vc * 4; /* id of Virtual Channel and Data Type set */
57 u8 dt_shift;
58
59 if (tg->enabled) {
60 /* Config Test Generator */
61 u32 num_lines, num_bytes_per_line;
62
63 input_format = &csid->fmt[MSM_CSID_PAD_SRC];
64 format = csid_get_fmt_entry(csid->res->formats->formats,
65 csid->res->formats->nformats,
66 input_format->code);
67 num_bytes_per_line = input_format->width * format->bpp * format->spp / 8;
68 num_lines = input_format->height;
69
70 /* 31:24 V blank, 23:13 H blank, 3:2 num of active DT */
71 /* 1:0 VC */
72 val = ((CAMSS_CSID_TG_VC_CFG_V_BLANKING & 0xff) << 24) |
73 ((CAMSS_CSID_TG_VC_CFG_H_BLANKING & 0x7ff) << 13);
74 writel_relaxed(val, csid->base + CAMSS_CSID_TG_VC_CFG);
75
76 /* 28:16 bytes per lines, 12:0 num of lines */
77 val = ((num_bytes_per_line & 0x1fff) << 16) |
78 (num_lines & 0x1fff);
79 writel_relaxed(val, csid->base + CAMSS_CSID_TG_DT_n_CGG_0(0));
80
81 /* 5:0 data type */
82 val = format->data_type;
83 writel_relaxed(val, csid->base + CAMSS_CSID_TG_DT_n_CGG_1(0));
84
85 /* 2:0 output test pattern */
86 val = tg->mode - 1;
87 writel_relaxed(val, csid->base + CAMSS_CSID_TG_DT_n_CGG_2(0));
88 } else {
89 struct csid_phy_config *phy = &csid->phy;
90
91 input_format = &csid->fmt[MSM_CSID_PAD_SINK];
92 format = csid_get_fmt_entry(csid->res->formats->formats,
93 csid->res->formats->nformats,
94 input_format->code);
95
96 val = phy->lane_cnt - 1;
97 val |= phy->lane_assign << 4;
98
99 writel_relaxed(val, csid->base + CAMSS_CSID_CORE_CTRL_0);
100
101 val = phy->csiphy_id << 17;
102 val |= 0x9;
103
104 writel_relaxed(val, csid->base + CAMSS_CSID_CORE_CTRL_1);
105 }
106
107 /* Config LUT */
108
109 dt_shift = (cid % 4) * 8;
110 val = readl_relaxed(csid->base + CAMSS_CSID_CID_LUT_VC_n(vc));
111 val &= ~(0xff << dt_shift);
112 val |= format->data_type << dt_shift;
113 writel_relaxed(val, csid->base + CAMSS_CSID_CID_LUT_VC_n(vc));
114
115 val = CAMSS_CSID_CID_n_CFG_ISPIF_EN;
116 val |= CAMSS_CSID_CID_n_CFG_RDI_EN;
117 val |= format->decode_format << CAMSS_CSID_CID_n_CFG_DECODE_FORMAT_SHIFT;
118 val |= CAMSS_CSID_CID_n_CFG_RDI_MODE_RAW_DUMP;
119 writel_relaxed(val, csid->base + CAMSS_CSID_CID_n_CFG(cid));
120
121 if (tg->enabled) {
122 val = CAMSS_CSID_TG_CTRL_ENABLE;
123 writel_relaxed(val, csid->base + CAMSS_CSID_TG_CTRL);
124 }
125 } else {
126 if (tg->enabled) {
127 val = CAMSS_CSID_TG_CTRL_DISABLE;
128 writel_relaxed(val, csid->base + CAMSS_CSID_TG_CTRL);
129 }
130 }
131 }
132
csid_configure_testgen_pattern(struct csid_device * csid,s32 val)133 static int csid_configure_testgen_pattern(struct csid_device *csid, s32 val)
134 {
135 if (val > 0 && val <= csid->testgen.nmodes)
136 csid->testgen.mode = val;
137
138 return 0;
139 }
140
csid_isr(int irq,void * dev)141 static irqreturn_t csid_isr(int irq, void *dev)
142 {
143 struct csid_device *csid = dev;
144 u32 value;
145
146 value = readl_relaxed(csid->base + CAMSS_CSID_IRQ_STATUS);
147 writel_relaxed(value, csid->base + CAMSS_CSID_IRQ_CLEAR_CMD);
148
149 if ((value >> 11) & 0x1)
150 complete(&csid->reset_complete);
151
152 return IRQ_HANDLED;
153 }
154
csid_reset(struct csid_device * csid)155 static int csid_reset(struct csid_device *csid)
156 {
157 unsigned long time;
158
159 reinit_completion(&csid->reset_complete);
160
161 writel_relaxed(0x7fff, csid->base + CAMSS_CSID_RST_CMD);
162
163 time = wait_for_completion_timeout(&csid->reset_complete,
164 msecs_to_jiffies(CSID_RESET_TIMEOUT_MS));
165 if (!time) {
166 dev_err(csid->camss->dev, "CSID reset timeout\n");
167 return -EIO;
168 }
169
170 return 0;
171 }
172
csid_subdev_init(struct csid_device * csid)173 static void csid_subdev_init(struct csid_device *csid)
174 {
175 csid->testgen.modes = csid_testgen_modes;
176 csid->testgen.nmodes = CSID_PAYLOAD_MODE_NUM_SUPPORTED_GEN1;
177 }
178
179 const struct csid_hw_ops csid_ops_4_1 = {
180 .configure_stream = csid_configure_stream,
181 .configure_testgen_pattern = csid_configure_testgen_pattern,
182 .hw_version = csid_hw_version,
183 .isr = csid_isr,
184 .reset = csid_reset,
185 .src_pad_code = csid_src_pad_code,
186 .subdev_init = csid_subdev_init,
187 };
188