1 // SPDX-License-Identifier: MIT 2 // 3 // Copyright 2024 Advanced Micro Devices, Inc. 4 5 #ifndef __DML_DML_DCN4_SOC_BB__ 6 #define __DML_DML_DCN4_SOC_BB__ 7 8 #include "dml_top_soc_parameter_types.h" 9 10 static const struct dml2_soc_qos_parameters dml_dcn4_variant_a_soc_qos_params = { 11 .derate_table = { 12 .system_active_urgent = { 13 .dram_derate_percent_pixel = 22, 14 .dram_derate_percent_vm = 0, 15 .dram_derate_percent_pixel_and_vm = 0, 16 .fclk_derate_percent = 76, 17 .dcfclk_derate_percent = 100, 18 }, 19 .system_active_average = { 20 .dram_derate_percent_pixel = 17, 21 .dram_derate_percent_vm = 0, 22 .dram_derate_percent_pixel_and_vm = 0, 23 .fclk_derate_percent = 57, 24 .dcfclk_derate_percent = 75, 25 }, 26 .dcn_mall_prefetch_urgent = { 27 .dram_derate_percent_pixel = 40, 28 .dram_derate_percent_vm = 0, 29 .dram_derate_percent_pixel_and_vm = 0, 30 .fclk_derate_percent = 83, 31 .dcfclk_derate_percent = 100, 32 }, 33 .dcn_mall_prefetch_average = { 34 .dram_derate_percent_pixel = 33, 35 .dram_derate_percent_vm = 0, 36 .dram_derate_percent_pixel_and_vm = 0, 37 .fclk_derate_percent = 62, 38 .dcfclk_derate_percent = 83, 39 }, 40 .system_idle_average = { 41 .dram_derate_percent_pixel = 70, 42 .dram_derate_percent_vm = 0, 43 .dram_derate_percent_pixel_and_vm = 0, 44 .fclk_derate_percent = 83, 45 .dcfclk_derate_percent = 100, 46 }, 47 }, 48 .writeback = { 49 .base_latency_us = 12, 50 .scaling_factor_us = 0, 51 .scaling_factor_mhz = 0, 52 }, 53 .qos_params = { 54 .dcn4x = { 55 .df_qos_response_time_fclk_cycles = 300, 56 .max_round_trip_to_furthest_cs_fclk_cycles = 350, 57 .mall_overhead_fclk_cycles = 50, 58 .meta_trip_adder_fclk_cycles = 36, 59 .average_transport_distance_fclk_cycles = 257, 60 .umc_urgent_ramp_latency_margin = 50, 61 .umc_max_latency_margin = 30, 62 .umc_average_latency_margin = 20, 63 .fabric_max_transport_latency_margin = 20, 64 .fabric_average_transport_latency_margin = 10, 65 66 .per_uclk_dpm_params = { 67 { 68 .minimum_uclk_khz = 97 * 1000, 69 .urgent_ramp_uclk_cycles = 472, 70 .trip_to_memory_uclk_cycles = 827, 71 .meta_trip_to_memory_uclk_cycles = 827, 72 .maximum_latency_when_urgent_uclk_cycles = 72, 73 .average_latency_when_urgent_uclk_cycles = 61, 74 .maximum_latency_when_non_urgent_uclk_cycles = 827, 75 .average_latency_when_non_urgent_uclk_cycles = 118, 76 }, 77 }, 78 }, 79 }, 80 .qos_type = dml2_qos_param_type_dcn4x, 81 }; 82 83 static const struct dml2_soc_bb dml2_socbb_dcn401 = { 84 .clk_table = { 85 .uclk = { 86 .clk_values_khz = {97000}, 87 .num_clk_values = 1, 88 }, 89 .fclk = { 90 .clk_values_khz = {300000, 2500000}, 91 .num_clk_values = 2, 92 }, 93 .dcfclk = { 94 .clk_values_khz = {200000, 1564000}, 95 .num_clk_values = 2, 96 }, 97 .dispclk = { 98 .clk_values_khz = {100000, 2000000}, 99 .num_clk_values = 2, 100 }, 101 .dppclk = { 102 .clk_values_khz = {100000, 2000000}, 103 .num_clk_values = 2, 104 }, 105 .dtbclk = { 106 .clk_values_khz = {100000, 1564000}, 107 .num_clk_values = 2, 108 }, 109 .phyclk = { 110 .clk_values_khz = {810000, 810000}, 111 .num_clk_values = 2, 112 }, 113 .socclk = { 114 .clk_values_khz = {300000, 1200000}, 115 .num_clk_values = 2, 116 }, 117 .dscclk = { 118 .clk_values_khz = {666667, 666667}, 119 .num_clk_values = 2, 120 }, 121 .phyclk_d18 = { 122 .clk_values_khz = {625000, 625000}, 123 .num_clk_values = 2, 124 }, 125 .phyclk_d32 = { 126 .clk_values_khz = {625000, 625000}, 127 .num_clk_values = 2, 128 }, 129 .dram_config = { 130 .channel_width_bytes = 2, 131 .channel_count = 16, 132 .transactions_per_clock = 16, 133 }, 134 }, 135 136 .qos_parameters = { 137 .derate_table = { 138 .system_active_urgent = { 139 .dram_derate_percent_pixel = 22, 140 .dram_derate_percent_vm = 0, 141 .dram_derate_percent_pixel_and_vm = 0, 142 .fclk_derate_percent = 76, 143 .dcfclk_derate_percent = 100, 144 }, 145 .system_active_average = { 146 .dram_derate_percent_pixel = 15, 147 .dram_derate_percent_vm = 0, 148 .dram_derate_percent_pixel_and_vm = 0, 149 .fclk_derate_percent = 57, 150 .dcfclk_derate_percent = 75, 151 }, 152 .dcn_mall_prefetch_urgent = { 153 .dram_derate_percent_pixel = 40, 154 .dram_derate_percent_vm = 0, 155 .dram_derate_percent_pixel_and_vm = 0, 156 .fclk_derate_percent = 83, 157 .dcfclk_derate_percent = 100, 158 }, 159 .dcn_mall_prefetch_average = { 160 .dram_derate_percent_pixel = 30, 161 .dram_derate_percent_vm = 0, 162 .dram_derate_percent_pixel_and_vm = 0, 163 .fclk_derate_percent = 62, 164 .dcfclk_derate_percent = 83, 165 }, 166 .system_idle_average = { 167 .dram_derate_percent_pixel = 70, 168 .dram_derate_percent_vm = 0, 169 .dram_derate_percent_pixel_and_vm = 0, 170 .fclk_derate_percent = 83, 171 .dcfclk_derate_percent = 100, 172 }, 173 }, 174 .writeback = { 175 .base_latency_us = 0, 176 .scaling_factor_us = 0, 177 .scaling_factor_mhz = 0, 178 }, 179 .qos_params = { 180 .dcn4x = { 181 .df_qos_response_time_fclk_cycles = 300, 182 .max_round_trip_to_furthest_cs_fclk_cycles = 350, 183 .mall_overhead_fclk_cycles = 50, 184 .meta_trip_adder_fclk_cycles = 36, 185 .average_transport_distance_fclk_cycles = 260, 186 .umc_urgent_ramp_latency_margin = 50, 187 .umc_max_latency_margin = 30, 188 .umc_average_latency_margin = 20, 189 .fabric_max_transport_latency_margin = 20, 190 .fabric_average_transport_latency_margin = 10, 191 192 .per_uclk_dpm_params = { 193 { 194 // State 1 195 .minimum_uclk_khz = 0, 196 .urgent_ramp_uclk_cycles = 472, 197 .trip_to_memory_uclk_cycles = 827, 198 .meta_trip_to_memory_uclk_cycles = 827, 199 .maximum_latency_when_urgent_uclk_cycles = 72, 200 .average_latency_when_urgent_uclk_cycles = 72, 201 .maximum_latency_when_non_urgent_uclk_cycles = 827, 202 .average_latency_when_non_urgent_uclk_cycles = 117, 203 }, 204 { 205 // State 2 206 .minimum_uclk_khz = 0, 207 .urgent_ramp_uclk_cycles = 546, 208 .trip_to_memory_uclk_cycles = 848, 209 .meta_trip_to_memory_uclk_cycles = 848, 210 .maximum_latency_when_urgent_uclk_cycles = 146, 211 .average_latency_when_urgent_uclk_cycles = 146, 212 .maximum_latency_when_non_urgent_uclk_cycles = 848, 213 .average_latency_when_non_urgent_uclk_cycles = 133, 214 }, 215 { 216 // State 3 217 .minimum_uclk_khz = 0, 218 .urgent_ramp_uclk_cycles = 564, 219 .trip_to_memory_uclk_cycles = 853, 220 .meta_trip_to_memory_uclk_cycles = 853, 221 .maximum_latency_when_urgent_uclk_cycles = 164, 222 .average_latency_when_urgent_uclk_cycles = 164, 223 .maximum_latency_when_non_urgent_uclk_cycles = 853, 224 .average_latency_when_non_urgent_uclk_cycles = 136, 225 }, 226 { 227 // State 4 228 .minimum_uclk_khz = 0, 229 .urgent_ramp_uclk_cycles = 613, 230 .trip_to_memory_uclk_cycles = 869, 231 .meta_trip_to_memory_uclk_cycles = 869, 232 .maximum_latency_when_urgent_uclk_cycles = 213, 233 .average_latency_when_urgent_uclk_cycles = 213, 234 .maximum_latency_when_non_urgent_uclk_cycles = 869, 235 .average_latency_when_non_urgent_uclk_cycles = 149, 236 }, 237 { 238 // State 5 239 .minimum_uclk_khz = 0, 240 .urgent_ramp_uclk_cycles = 632, 241 .trip_to_memory_uclk_cycles = 874, 242 .meta_trip_to_memory_uclk_cycles = 874, 243 .maximum_latency_when_urgent_uclk_cycles = 232, 244 .average_latency_when_urgent_uclk_cycles = 232, 245 .maximum_latency_when_non_urgent_uclk_cycles = 874, 246 .average_latency_when_non_urgent_uclk_cycles = 153, 247 }, 248 { 249 // State 6 250 .minimum_uclk_khz = 0, 251 .urgent_ramp_uclk_cycles = 665, 252 .trip_to_memory_uclk_cycles = 885, 253 .meta_trip_to_memory_uclk_cycles = 885, 254 .maximum_latency_when_urgent_uclk_cycles = 265, 255 .average_latency_when_urgent_uclk_cycles = 265, 256 .maximum_latency_when_non_urgent_uclk_cycles = 885, 257 .average_latency_when_non_urgent_uclk_cycles = 161, 258 }, 259 { 260 // State 7 261 .minimum_uclk_khz = 0, 262 .urgent_ramp_uclk_cycles = 689, 263 .trip_to_memory_uclk_cycles = 895, 264 .meta_trip_to_memory_uclk_cycles = 895, 265 .maximum_latency_when_urgent_uclk_cycles = 289, 266 .average_latency_when_urgent_uclk_cycles = 289, 267 .maximum_latency_when_non_urgent_uclk_cycles = 895, 268 .average_latency_when_non_urgent_uclk_cycles = 167, 269 }, 270 { 271 // State 8 272 .minimum_uclk_khz = 0, 273 .urgent_ramp_uclk_cycles = 716, 274 .trip_to_memory_uclk_cycles = 902, 275 .meta_trip_to_memory_uclk_cycles = 902, 276 .maximum_latency_when_urgent_uclk_cycles = 316, 277 .average_latency_when_urgent_uclk_cycles = 316, 278 .maximum_latency_when_non_urgent_uclk_cycles = 902, 279 .average_latency_when_non_urgent_uclk_cycles = 174, 280 }, 281 }, 282 }, 283 }, 284 .qos_type = dml2_qos_param_type_dcn4x, 285 }, 286 287 .power_management_parameters = { 288 .dram_clk_change_blackout_us = 400, 289 .fclk_change_blackout_us = 0, 290 .g7_ppt_blackout_us = 0, 291 .stutter_enter_plus_exit_latency_us = 54, 292 .stutter_exit_latency_us = 41, 293 .z8_stutter_enter_plus_exit_latency_us = 0, 294 .z8_stutter_exit_latency_us = 0, 295 /* 296 .g6_temp_read_blackout_us = { 297 23.00, 298 10.00, 299 10.00, 300 8.00, 301 8.00, 302 5.00, 303 5.00, 304 5.00, 305 }, 306 */ 307 }, 308 309 .vmin_limit = { 310 .dispclk_khz = 600 * 1000, 311 }, 312 313 .dprefclk_mhz = 720, 314 .xtalclk_mhz = 100, 315 .pcie_refclk_mhz = 100, 316 .dchub_refclk_mhz = 50, 317 .mall_allocated_for_dcn_mbytes = 64, 318 .max_outstanding_reqs = 512, 319 .fabric_datapath_to_dcn_data_return_bytes = 64, 320 .return_bus_width_bytes = 64, 321 .hostvm_min_page_size_kbytes = 0, 322 .gpuvm_min_page_size_kbytes = 256, 323 .phy_downspread_percent = 0.38, 324 .dcn_downspread_percent = 0.38, 325 .dispclk_dppclk_vco_speed_mhz = 4500, 326 .do_urgent_latency_adjustment = 0, 327 .mem_word_bytes = 32, 328 .num_dcc_mcaches = 8, 329 .mcache_size_bytes = 2048, 330 .mcache_line_size_bytes = 32, 331 .max_fclk_for_uclk_dpm_khz = 1250 * 1000, 332 }; 333 334 static const struct dml2_ip_capabilities dml2_dcn401_max_ip_caps = { 335 .pipe_count = 4, 336 .otg_count = 4, 337 .num_dsc = 4, 338 .max_num_dp2p0_streams = 4, 339 .max_num_hdmi_frl_outputs = 1, 340 .max_num_dp2p0_outputs = 4, 341 .rob_buffer_size_kbytes = 192, 342 .config_return_buffer_size_in_kbytes = 1344, 343 .config_return_buffer_segment_size_in_kbytes = 64, 344 .meta_fifo_size_in_kentries = 22, 345 .compressed_buffer_segment_size_in_kbytes = 64, 346 .cursor_buffer_size = 24, 347 .max_flip_time_us = 80, 348 .max_flip_time_lines = 32, 349 .hostvm_mode = 0, 350 .subvp_drr_scheduling_margin_us = 100, 351 .subvp_prefetch_end_to_mall_start_us = 15, 352 .subvp_fw_processing_delay = 15, 353 .max_vactive_det_fill_delay_us = 400, 354 355 .fams2 = { 356 .max_allow_delay_us = 100 * 1000, 357 .scheduling_delay_us = 550, 358 .vertical_interrupt_ack_delay_us = 40, 359 .allow_programming_delay_us = 18, 360 .min_allow_width_us = 20, 361 .subvp_df_throttle_delay_us = 100, 362 .subvp_programming_delay_us = 200, 363 .subvp_prefetch_to_mall_delay_us = 18, 364 .drr_programming_delay_us = 35, 365 366 .lock_timeout_us = 5000, 367 .recovery_timeout_us = 5000, 368 .flip_programming_delay_us = 300, 369 }, 370 }; 371 372 #endif 373