1 /* mb93493-regs.h: MB93493 companion chip registers 2 * 3 * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved. 4 * Written by David Howells (dhowells@redhat.com) 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12 #ifndef _ASM_MB93493_REGS_H 13 #define _ASM_MB93493_REGS_H 14 15 #include <asm/mb-regs.h> 16 #include <asm/mb93493-irqs.h> 17 18 #define __addr_MB93493(X) ((volatile unsigned long *)(__region_CS3 + (X))) 19 #define __get_MB93493(X) ({ *(volatile unsigned long *)(__region_CS3 + (X)); }) 20 21 #define __set_MB93493(X,V) \ 22 do { \ 23 *(volatile unsigned long *)(__region_CS3 + (X)) = (V); mb(); \ 24 } while(0) 25 26 #define __get_MB93493_STSR(X) __get_MB93493(0x3c0 + (X) * 4) 27 #define __set_MB93493_STSR(X,V) __set_MB93493(0x3c0 + (X) * 4, (V)) 28 #define MB93493_STSR_EN 29 30 #define __addr_MB93493_IQSR(X) __addr_MB93493(0x3d0 + (X) * 4) 31 #define __get_MB93493_IQSR(X) __get_MB93493(0x3d0 + (X) * 4) 32 #define __set_MB93493_IQSR(X,V) __set_MB93493(0x3d0 + (X) * 4, (V)) 33 34 #define __get_MB93493_DQSR(X) __get_MB93493(0x3e0 + (X) * 4) 35 #define __set_MB93493_DQSR(X,V) __set_MB93493(0x3e0 + (X) * 4, (V)) 36 37 #define __get_MB93493_LBSER() __get_MB93493(0x3f0) 38 #define __set_MB93493_LBSER(V) __set_MB93493(0x3f0, (V)) 39 40 #define MB93493_LBSER_VDC 0x00010000 41 #define MB93493_LBSER_VCC 0x00020000 42 #define MB93493_LBSER_AUDIO 0x00040000 43 #define MB93493_LBSER_I2C_0 0x00080000 44 #define MB93493_LBSER_I2C_1 0x00100000 45 #define MB93493_LBSER_USB 0x00200000 46 #define MB93493_LBSER_GPIO 0x00800000 47 #define MB93493_LBSER_PCMCIA 0x01000000 48 49 #define __get_MB93493_LBSR() __get_MB93493(0x3fc) 50 #define __set_MB93493_LBSR(V) __set_MB93493(0x3fc, (V)) 51 52 /* 53 * video display controller 54 */ 55 #define __get_MB93493_VDC(X) __get_MB93493(MB93493_VDC_##X) 56 #define __set_MB93493_VDC(X,V) __set_MB93493(MB93493_VDC_##X, (V)) 57 58 #define MB93493_VDC_RCURSOR 0x140 /* cursor position */ 59 #define MB93493_VDC_RCT1 0x144 /* cursor colour 1 */ 60 #define MB93493_VDC_RCT2 0x148 /* cursor colour 2 */ 61 #define MB93493_VDC_RHDC 0x150 /* horizontal display period */ 62 #define MB93493_VDC_RH_MARGINS 0x154 /* horizontal margin sizes */ 63 #define MB93493_VDC_RVDC 0x158 /* vertical display period */ 64 #define MB93493_VDC_RV_MARGINS 0x15c /* vertical margin sizes */ 65 #define MB93493_VDC_RC 0x170 /* VDC control */ 66 #define MB93493_VDC_RCLOCK 0x174 /* clock divider, DMA req delay */ 67 #define MB93493_VDC_RBLACK 0x178 /* black insert sizes */ 68 #define MB93493_VDC_RS 0x17c /* VDC status */ 69 70 #define __addr_MB93493_VDC_BCI(X) ({ (volatile unsigned long *)(__region_CS3 + 0x000 + (X)); }) 71 #define __addr_MB93493_VDC_TPO(X) (__region_CS3 + 0x1c0 + (X)) 72 73 #define VDC_TPO_WIDTH 32 74 75 #define VDC_RC_DSR 0x00000080 /* VDC master reset */ 76 77 #define VDC_RS_IT 0x00060000 /* interrupt indicators */ 78 #define VDC_RS_IT_UNDERFLOW 0x00040000 /* - underflow event */ 79 #define VDC_RS_IT_VSYNC 0x00020000 /* - VSYNC event */ 80 #define VDC_RS_DFI 0x00010000 /* current interlace field number */ 81 #define VDC_RS_DFI_TOP 0x00000000 /* - top field */ 82 #define VDC_RS_DFI_BOTTOM 0x00010000 /* - bottom field */ 83 #define VDC_RS_DCSR 0x00000010 /* cursor state */ 84 #define VDC_RS_DCM 0x00000003 /* display mode */ 85 #define VDC_RS_DCM_DISABLED 0x00000000 /* - display disabled */ 86 #define VDC_RS_DCM_STOPPED 0x00000001 /* - VDC stopped */ 87 #define VDC_RS_DCM_FREERUNNING 0x00000002 /* - VDC free-running */ 88 #define VDC_RS_DCM_TRANSFERRING 0x00000003 /* - data being transferred to VDC */ 89 90 /* 91 * video capture controller 92 */ 93 #define __get_MB93493_VCC(X) __get_MB93493(MB93493_VCC_##X) 94 #define __set_MB93493_VCC(X,V) __set_MB93493(MB93493_VCC_##X, (V)) 95 96 #define MB93493_VCC_RREDUCT 0x104 /* reduction rate */ 97 #define MB93493_VCC_RHY 0x108 /* horizontal brightness filter coefficients */ 98 #define MB93493_VCC_RHC 0x10c /* horizontal colour-difference filter coefficients */ 99 #define MB93493_VCC_RHSIZE 0x110 /* horizontal cycle sizes */ 100 #define MB93493_VCC_RHBC 0x114 /* horizontal back porch size */ 101 #define MB93493_VCC_RVCC 0x118 /* vertical capture period */ 102 #define MB93493_VCC_RVBC 0x11c /* vertical back porch period */ 103 #define MB93493_VCC_RV 0x120 /* vertical filter coefficients */ 104 #define MB93493_VCC_RDTS 0x128 /* DMA transfer size */ 105 #define MB93493_VCC_RDTS_4B 0x01000000 /* 4-byte transfer */ 106 #define MB93493_VCC_RDTS_32B 0x03000000 /* 32-byte transfer */ 107 #define MB93493_VCC_RDTS_SHIFT 24 108 #define MB93493_VCC_RCC 0x130 /* VCC control */ 109 #define MB93493_VCC_RIS 0x134 /* VCC interrupt status */ 110 111 #define __addr_MB93493_VCC_TPI(X) (__region_CS3 + 0x180 + (X)) 112 113 #define VCC_RHSIZE_RHCC 0x000007ff 114 #define VCC_RHSIZE_RHCC_SHIFT 0 115 #define VCC_RHSIZE_RHTCC 0x0fff0000 116 #define VCC_RHSIZE_RHTCC_SHIFT 16 117 118 #define VCC_RVBC_RVBC 0x00003f00 119 #define VCC_RVBC_RVBC_SHIFT 8 120 121 #define VCC_RREDUCT_RHR 0x07ff0000 122 #define VCC_RREDUCT_RHR_SHIFT 16 123 #define VCC_RREDUCT_RVR 0x000007ff 124 #define VCC_RREDUCT_RVR_SHIFT 0 125 126 #define VCC_RCC_CE 0x00000001 /* VCC enable */ 127 #define VCC_RCC_CS 0x00000002 /* request video capture start */ 128 #define VCC_RCC_CPF 0x0000000c /* pixel format */ 129 #define VCC_RCC_CPF_YCBCR_16 0x00000000 /* - YCbCr 4:2:2 16-bit format */ 130 #define VCC_RCC_CPF_RGB 0x00000004 /* - RGB 4:4:4 format */ 131 #define VCC_RCC_CPF_YCBCR_24 0x00000008 /* - YCbCr 4:2:2 24-bit format */ 132 #define VCC_RCC_CPF_BT656 0x0000000c /* - ITU R-BT.656 format */ 133 #define VCC_RCC_CPF_SHIFT 2 134 #define VCC_RCC_CSR 0x00000080 /* request reset */ 135 #define VCC_RCC_HSIP 0x00000100 /* HSYNC polarity */ 136 #define VCC_RCC_HSIP_LOACT 0x00000000 /* - low active */ 137 #define VCC_RCC_HSIP_HIACT 0x00000100 /* - high active */ 138 #define VCC_RCC_VSIP 0x00000200 /* VSYNC polarity */ 139 #define VCC_RCC_VSIP_LOACT 0x00000000 /* - low active */ 140 #define VCC_RCC_VSIP_HIACT 0x00000200 /* - high active */ 141 #define VCC_RCC_CIE 0x00000800 /* interrupt enable */ 142 #define VCC_RCC_CFP 0x00001000 /* RGB pixel packing */ 143 #define VCC_RCC_CFP_4TO3 0x00000000 /* - pack 4 pixels into 3 words */ 144 #define VCC_RCC_CFP_1TO1 0x00001000 /* - pack 1 pixel into 1 words */ 145 #define VCC_RCC_CSM 0x00006000 /* interlace specification */ 146 #define VCC_RCC_CSM_ONEPASS 0x00002000 /* - non-interlaced */ 147 #define VCC_RCC_CSM_INTERLACE 0x00004000 /* - interlaced */ 148 #define VCC_RCC_CSM_SHIFT 13 149 #define VCC_RCC_ES 0x00008000 /* capture start polarity */ 150 #define VCC_RCC_ES_NEG 0x00000000 /* - negative edge */ 151 #define VCC_RCC_ES_POS 0x00008000 /* - positive edge */ 152 #define VCC_RCC_IFI 0x00080000 /* inferlace field evaluation reverse */ 153 #define VCC_RCC_FDTS 0x00300000 /* interlace field start */ 154 #define VCC_RCC_FDTS_3_8 0x00000000 /* - 3/8 of horizontal entire cycle */ 155 #define VCC_RCC_FDTS_1_4 0x00100000 /* - 1/4 of horizontal entire cycle */ 156 #define VCC_RCC_FDTS_7_16 0x00200000 /* - 7/16 of horizontal entire cycle */ 157 #define VCC_RCC_FDTS_SHIFT 20 158 #define VCC_RCC_MOV 0x00400000 /* test bit - always set to 1 */ 159 #define VCC_RCC_STP 0x00800000 /* request video capture stop */ 160 #define VCC_RCC_TO 0x01000000 /* input during top-field only */ 161 162 #define VCC_RIS_VSYNC 0x01000000 /* VSYNC interrupt */ 163 #define VCC_RIS_OV 0x02000000 /* overflow interrupt */ 164 #define VCC_RIS_BOTTOM 0x08000000 /* interlace bottom field */ 165 #define VCC_RIS_STARTED 0x10000000 /* capture started */ 166 167 /* 168 * I2C 169 */ 170 #define MB93493_I2C_BSR 0x340 /* bus status */ 171 #define MB93493_I2C_BCR 0x344 /* bus control */ 172 #define MB93493_I2C_CCR 0x348 /* clock control */ 173 #define MB93493_I2C_ADR 0x34c /* address */ 174 #define MB93493_I2C_DTR 0x350 /* data */ 175 #define MB93493_I2C_BC2R 0x35c /* bus control 2 */ 176 177 #define __addr_MB93493_I2C(port,X) (__region_CS3 + MB93493_I2C_##X + ((port)*0x20)) 178 #define __get_MB93493_I2C(port,X) __get_MB93493(MB93493_I2C_##X + ((port)*0x20)) 179 #define __set_MB93493_I2C(port,X,V) __set_MB93493(MB93493_I2C_##X + ((port)*0x20), (V)) 180 181 #define I2C_BSR_BB (1 << 7) 182 183 /* 184 * audio controller (I2S) registers 185 */ 186 #define __get_MB93493_I2S(X) __get_MB93493(MB93493_I2S_##X) 187 #define __set_MB93493_I2S(X,V) __set_MB93493(MB93493_I2S_##X, (V)) 188 189 #define MB93493_I2S_ALDR 0x300 /* L-channel data */ 190 #define MB93493_I2S_ARDR 0x304 /* R-channel data */ 191 #define MB93493_I2S_APDR 0x308 /* 16-bit packed data */ 192 #define MB93493_I2S_AISTR 0x310 /* status */ 193 #define MB93493_I2S_AICR 0x314 /* control */ 194 195 #define __addr_MB93493_I2S_ALDR(X) (__region_CS3 + MB93493_I2S_ALDR + (X)) 196 #define __addr_MB93493_I2S_ARDR(X) (__region_CS3 + MB93493_I2S_ARDR + (X)) 197 #define __addr_MB93493_I2S_APDR(X) (__region_CS3 + MB93493_I2S_APDR + (X)) 198 #define __addr_MB93493_I2S_ADR(X) (__region_CS3 + 0x320 + (X)) 199 200 #define I2S_AISTR_OTST 0x00000003 /* status of output data transfer */ 201 #define I2S_AISTR_OTR 0x00000010 /* output transfer request pending */ 202 #define I2S_AISTR_OUR 0x00000020 /* output FIFO underrun detected */ 203 #define I2S_AISTR_OOR 0x00000040 /* output FIFO overrun detected */ 204 #define I2S_AISTR_ODS 0x00000100 /* output DMA transfer size */ 205 #define I2S_AISTR_ODE 0x00000400 /* output DMA transfer request enable */ 206 #define I2S_AISTR_OTRIE 0x00001000 /* output transfer request interrupt enable */ 207 #define I2S_AISTR_OURIE 0x00002000 /* output FIFO underrun interrupt enable */ 208 #define I2S_AISTR_OORIE 0x00004000 /* output FIFO overrun interrupt enable */ 209 #define I2S_AISTR__OUT_MASK 0x00007570 210 #define I2S_AISTR_ITST 0x00030000 /* status of input data transfer */ 211 #define I2S_AISTR_ITST_SHIFT 16 212 #define I2S_AISTR_ITR 0x00100000 /* input transfer request pending */ 213 #define I2S_AISTR_IUR 0x00200000 /* input FIFO underrun detected */ 214 #define I2S_AISTR_IOR 0x00400000 /* input FIFO overrun detected */ 215 #define I2S_AISTR_IDS 0x01000000 /* input DMA transfer size */ 216 #define I2S_AISTR_IDE 0x04000000 /* input DMA transfer request enable */ 217 #define I2S_AISTR_ITRIE 0x10000000 /* input transfer request interrupt enable */ 218 #define I2S_AISTR_IURIE 0x20000000 /* input FIFO underrun interrupt enable */ 219 #define I2S_AISTR_IORIE 0x40000000 /* input FIFO overrun interrupt enable */ 220 #define I2S_AISTR__IN_MASK 0x75700000 221 222 #define I2S_AICR_MI 0x00000001 /* mono input requested */ 223 #define I2S_AICR_AMI 0x00000002 /* relation between LRCKI/FS1 and SDI */ 224 #define I2S_AICR_LRI 0x00000004 /* function of LRCKI pin */ 225 #define I2S_AICR_SDMI 0x00000070 /* format of input audio data */ 226 #define I2S_AICR_SDMI_SHIFT 4 227 #define I2S_AICR_CLI 0x00000080 /* input FIFO clearing control */ 228 #define I2S_AICR_IM 0x00000300 /* input state control */ 229 #define I2S_AICR_IM_SHIFT 8 230 #define I2S_AICR__IN_MASK 0x000003f7 231 #define I2S_AICR_MO 0x00001000 /* mono output requested */ 232 #define I2S_AICR_AMO 0x00002000 /* relation between LRCKO/FS0 and SDO */ 233 #define I2S_AICR_AMO_SHIFT 13 234 #define I2S_AICR_LRO 0x00004000 /* function of LRCKO pin */ 235 #define I2S_AICR_SDMO 0x00070000 /* format of output audio data */ 236 #define I2S_AICR_SDMO_SHIFT 16 237 #define I2S_AICR_CLO 0x00080000 /* output FIFO clearing control */ 238 #define I2S_AICR_OM 0x00100000 /* output state control */ 239 #define I2S_AICR__OUT_MASK 0x001f7000 240 #define I2S_AICR_DIV 0x03000000 /* frequency division rate */ 241 #define I2S_AICR_DIV_SHIFT 24 242 #define I2S_AICR_FL 0x20000000 /* frame length */ 243 #define I2S_AICR_FS 0x40000000 /* frame sync method */ 244 #define I2S_AICR_ME 0x80000000 /* master enable */ 245 246 /* 247 * PCMCIA 248 */ 249 #define __addr_MB93493_PCMCIA(X) ((volatile unsigned long *)(__region_CS5 + (X))) 250 251 /* 252 * GPIO 253 */ 254 #define __get_MB93493_GPIO_PDR(X) __get_MB93493(0x380 + (X) * 0xc0) 255 #define __set_MB93493_GPIO_PDR(X,V) __set_MB93493(0x380 + (X) * 0xc0, (V)) 256 257 #define __get_MB93493_GPIO_GPDR(X) __get_MB93493(0x384 + (X) * 0xc0) 258 #define __set_MB93493_GPIO_GPDR(X,V) __set_MB93493(0x384 + (X) * 0xc0, (V)) 259 260 #define __get_MB93493_GPIO_SIR(X) __get_MB93493(0x388 + (X) * 0xc0) 261 #define __set_MB93493_GPIO_SIR(X,V) __set_MB93493(0x388 + (X) * 0xc0, (V)) 262 263 #define __get_MB93493_GPIO_SOR(X) __get_MB93493(0x38c + (X) * 0xc0) 264 #define __set_MB93493_GPIO_SOR(X,V) __set_MB93493(0x38c + (X) * 0xc0, (V)) 265 266 #define __get_MB93493_GPIO_PDSR(X) __get_MB93493(0x390 + (X) * 0xc0) 267 #define __set_MB93493_GPIO_PDSR(X,V) __set_MB93493(0x390 + (X) * 0xc0, (V)) 268 269 #define __get_MB93493_GPIO_PDCR(X) __get_MB93493(0x394 + (X) * 0xc0) 270 #define __set_MB93493_GPIO_PDCR(X,V) __set_MB93493(0x394 + (X) * 0xc0, (V)) 271 272 #define __get_MB93493_GPIO_INTST(X) __get_MB93493(0x398 + (X) * 0xc0) 273 #define __set_MB93493_GPIO_INTST(X,V) __set_MB93493(0x398 + (X) * 0xc0, (V)) 274 275 #define __get_MB93493_GPIO_IEHL(X) __get_MB93493(0x39c + (X) * 0xc0) 276 #define __set_MB93493_GPIO_IEHL(X,V) __set_MB93493(0x39c + (X) * 0xc0, (V)) 277 278 #define __get_MB93493_GPIO_IELH(X) __get_MB93493(0x3a0 + (X) * 0xc0) 279 #define __set_MB93493_GPIO_IELH(X,V) __set_MB93493(0x3a0 + (X) * 0xc0, (V)) 280 281 #endif /* _ASM_MB93493_REGS_H */ 282