1 /*
2  * Copyright 2011 Tilera Corporation. All Rights Reserved.
3  *
4  *   This program is free software; you can redistribute it and/or
5  *   modify it under the terms of the GNU General Public License
6  *   as published by the Free Software Foundation, version 2.
7  *
8  *   This program is distributed in the hope that it will be useful, but
9  *   WITHOUT ANY WARRANTY; without even the implied warranty of
10  *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11  *   NON INFRINGEMENT.  See the GNU General Public License for
12  *   more details.
13  */
14 
15 #ifndef __ARCH_INTERRUPTS_H__
16 #define __ARCH_INTERRUPTS_H__
17 
18 /** Mask for an interrupt. */
19 #ifdef __ASSEMBLER__
20 /* Note: must handle breaking interrupts into high and low words manually. */
21 #define INT_MASK(intno) (1 << (intno))
22 #else
23 #define INT_MASK(intno) (1ULL << (intno))
24 #endif
25 
26 
27 /** Where a given interrupt executes */
28 #define INTERRUPT_VECTOR(i, pl) (0xFC000000 + ((pl) << 24) + ((i) << 8))
29 
30 /** Where to store a vector for a given interrupt. */
31 #define USER_INTERRUPT_VECTOR(i) INTERRUPT_VECTOR(i, 0)
32 
33 /** The base address of user-level interrupts. */
34 #define USER_INTERRUPT_VECTOR_BASE INTERRUPT_VECTOR(0, 0)
35 
36 
37 /** Additional synthetic interrupt. */
38 #define INT_BREAKPOINT (63)
39 
40 #define INT_MEM_ERROR    0
41 #define INT_SINGLE_STEP_3    1
42 #define INT_SINGLE_STEP_2    2
43 #define INT_SINGLE_STEP_1    3
44 #define INT_SINGLE_STEP_0    4
45 #define INT_IDN_COMPLETE    5
46 #define INT_UDN_COMPLETE    6
47 #define INT_ITLB_MISS    7
48 #define INT_ILL    8
49 #define INT_GPV    9
50 #define INT_IDN_ACCESS   10
51 #define INT_UDN_ACCESS   11
52 #define INT_SWINT_3   12
53 #define INT_SWINT_2   13
54 #define INT_SWINT_1   14
55 #define INT_SWINT_0   15
56 #define INT_ILL_TRANS   16
57 #define INT_UNALIGN_DATA   17
58 #define INT_DTLB_MISS   18
59 #define INT_DTLB_ACCESS   19
60 #define INT_IDN_FIREWALL   20
61 #define INT_UDN_FIREWALL   21
62 #define INT_TILE_TIMER   22
63 #define INT_AUX_TILE_TIMER   23
64 #define INT_IDN_TIMER   24
65 #define INT_UDN_TIMER   25
66 #define INT_IDN_AVAIL   26
67 #define INT_UDN_AVAIL   27
68 #define INT_IPI_3   28
69 #define INT_IPI_2   29
70 #define INT_IPI_1   30
71 #define INT_IPI_0   31
72 #define INT_PERF_COUNT   32
73 #define INT_AUX_PERF_COUNT   33
74 #define INT_INTCTRL_3   34
75 #define INT_INTCTRL_2   35
76 #define INT_INTCTRL_1   36
77 #define INT_INTCTRL_0   37
78 #define INT_BOOT_ACCESS   38
79 #define INT_WORLD_ACCESS   39
80 #define INT_I_ASID   40
81 #define INT_D_ASID   41
82 #define INT_DOUBLE_FAULT   42
83 
84 #define NUM_INTERRUPTS 43
85 
86 #ifndef __ASSEMBLER__
87 #define QUEUED_INTERRUPTS ( \
88     INT_MASK(INT_MEM_ERROR) | \
89     INT_MASK(INT_IDN_COMPLETE) | \
90     INT_MASK(INT_UDN_COMPLETE) | \
91     INT_MASK(INT_IDN_FIREWALL) | \
92     INT_MASK(INT_UDN_FIREWALL) | \
93     INT_MASK(INT_TILE_TIMER) | \
94     INT_MASK(INT_AUX_TILE_TIMER) | \
95     INT_MASK(INT_IDN_TIMER) | \
96     INT_MASK(INT_UDN_TIMER) | \
97     INT_MASK(INT_IDN_AVAIL) | \
98     INT_MASK(INT_UDN_AVAIL) | \
99     INT_MASK(INT_IPI_3) | \
100     INT_MASK(INT_IPI_2) | \
101     INT_MASK(INT_IPI_1) | \
102     INT_MASK(INT_IPI_0) | \
103     INT_MASK(INT_PERF_COUNT) | \
104     INT_MASK(INT_AUX_PERF_COUNT) | \
105     INT_MASK(INT_INTCTRL_3) | \
106     INT_MASK(INT_INTCTRL_2) | \
107     INT_MASK(INT_INTCTRL_1) | \
108     INT_MASK(INT_INTCTRL_0) | \
109     INT_MASK(INT_BOOT_ACCESS) | \
110     INT_MASK(INT_WORLD_ACCESS) | \
111     INT_MASK(INT_I_ASID) | \
112     INT_MASK(INT_D_ASID) | \
113     INT_MASK(INT_DOUBLE_FAULT) | \
114     0)
115 #define NONQUEUED_INTERRUPTS ( \
116     INT_MASK(INT_SINGLE_STEP_3) | \
117     INT_MASK(INT_SINGLE_STEP_2) | \
118     INT_MASK(INT_SINGLE_STEP_1) | \
119     INT_MASK(INT_SINGLE_STEP_0) | \
120     INT_MASK(INT_ITLB_MISS) | \
121     INT_MASK(INT_ILL) | \
122     INT_MASK(INT_GPV) | \
123     INT_MASK(INT_IDN_ACCESS) | \
124     INT_MASK(INT_UDN_ACCESS) | \
125     INT_MASK(INT_SWINT_3) | \
126     INT_MASK(INT_SWINT_2) | \
127     INT_MASK(INT_SWINT_1) | \
128     INT_MASK(INT_SWINT_0) | \
129     INT_MASK(INT_ILL_TRANS) | \
130     INT_MASK(INT_UNALIGN_DATA) | \
131     INT_MASK(INT_DTLB_MISS) | \
132     INT_MASK(INT_DTLB_ACCESS) | \
133     0)
134 #define CRITICAL_MASKED_INTERRUPTS ( \
135     INT_MASK(INT_MEM_ERROR) | \
136     INT_MASK(INT_SINGLE_STEP_3) | \
137     INT_MASK(INT_SINGLE_STEP_2) | \
138     INT_MASK(INT_SINGLE_STEP_1) | \
139     INT_MASK(INT_SINGLE_STEP_0) | \
140     INT_MASK(INT_IDN_COMPLETE) | \
141     INT_MASK(INT_UDN_COMPLETE) | \
142     INT_MASK(INT_IDN_FIREWALL) | \
143     INT_MASK(INT_UDN_FIREWALL) | \
144     INT_MASK(INT_TILE_TIMER) | \
145     INT_MASK(INT_AUX_TILE_TIMER) | \
146     INT_MASK(INT_IDN_TIMER) | \
147     INT_MASK(INT_UDN_TIMER) | \
148     INT_MASK(INT_IDN_AVAIL) | \
149     INT_MASK(INT_UDN_AVAIL) | \
150     INT_MASK(INT_IPI_3) | \
151     INT_MASK(INT_IPI_2) | \
152     INT_MASK(INT_IPI_1) | \
153     INT_MASK(INT_IPI_0) | \
154     INT_MASK(INT_PERF_COUNT) | \
155     INT_MASK(INT_AUX_PERF_COUNT) | \
156     INT_MASK(INT_INTCTRL_3) | \
157     INT_MASK(INT_INTCTRL_2) | \
158     INT_MASK(INT_INTCTRL_1) | \
159     INT_MASK(INT_INTCTRL_0) | \
160     0)
161 #define CRITICAL_UNMASKED_INTERRUPTS ( \
162     INT_MASK(INT_ITLB_MISS) | \
163     INT_MASK(INT_ILL) | \
164     INT_MASK(INT_GPV) | \
165     INT_MASK(INT_IDN_ACCESS) | \
166     INT_MASK(INT_UDN_ACCESS) | \
167     INT_MASK(INT_SWINT_3) | \
168     INT_MASK(INT_SWINT_2) | \
169     INT_MASK(INT_SWINT_1) | \
170     INT_MASK(INT_SWINT_0) | \
171     INT_MASK(INT_ILL_TRANS) | \
172     INT_MASK(INT_UNALIGN_DATA) | \
173     INT_MASK(INT_DTLB_MISS) | \
174     INT_MASK(INT_DTLB_ACCESS) | \
175     INT_MASK(INT_BOOT_ACCESS) | \
176     INT_MASK(INT_WORLD_ACCESS) | \
177     INT_MASK(INT_I_ASID) | \
178     INT_MASK(INT_D_ASID) | \
179     INT_MASK(INT_DOUBLE_FAULT) | \
180     0)
181 #define MASKABLE_INTERRUPTS ( \
182     INT_MASK(INT_MEM_ERROR) | \
183     INT_MASK(INT_SINGLE_STEP_3) | \
184     INT_MASK(INT_SINGLE_STEP_2) | \
185     INT_MASK(INT_SINGLE_STEP_1) | \
186     INT_MASK(INT_SINGLE_STEP_0) | \
187     INT_MASK(INT_IDN_COMPLETE) | \
188     INT_MASK(INT_UDN_COMPLETE) | \
189     INT_MASK(INT_IDN_FIREWALL) | \
190     INT_MASK(INT_UDN_FIREWALL) | \
191     INT_MASK(INT_TILE_TIMER) | \
192     INT_MASK(INT_AUX_TILE_TIMER) | \
193     INT_MASK(INT_IDN_TIMER) | \
194     INT_MASK(INT_UDN_TIMER) | \
195     INT_MASK(INT_IDN_AVAIL) | \
196     INT_MASK(INT_UDN_AVAIL) | \
197     INT_MASK(INT_IPI_3) | \
198     INT_MASK(INT_IPI_2) | \
199     INT_MASK(INT_IPI_1) | \
200     INT_MASK(INT_IPI_0) | \
201     INT_MASK(INT_PERF_COUNT) | \
202     INT_MASK(INT_AUX_PERF_COUNT) | \
203     INT_MASK(INT_INTCTRL_3) | \
204     INT_MASK(INT_INTCTRL_2) | \
205     INT_MASK(INT_INTCTRL_1) | \
206     INT_MASK(INT_INTCTRL_0) | \
207     0)
208 #define UNMASKABLE_INTERRUPTS ( \
209     INT_MASK(INT_ITLB_MISS) | \
210     INT_MASK(INT_ILL) | \
211     INT_MASK(INT_GPV) | \
212     INT_MASK(INT_IDN_ACCESS) | \
213     INT_MASK(INT_UDN_ACCESS) | \
214     INT_MASK(INT_SWINT_3) | \
215     INT_MASK(INT_SWINT_2) | \
216     INT_MASK(INT_SWINT_1) | \
217     INT_MASK(INT_SWINT_0) | \
218     INT_MASK(INT_ILL_TRANS) | \
219     INT_MASK(INT_UNALIGN_DATA) | \
220     INT_MASK(INT_DTLB_MISS) | \
221     INT_MASK(INT_DTLB_ACCESS) | \
222     INT_MASK(INT_BOOT_ACCESS) | \
223     INT_MASK(INT_WORLD_ACCESS) | \
224     INT_MASK(INT_I_ASID) | \
225     INT_MASK(INT_D_ASID) | \
226     INT_MASK(INT_DOUBLE_FAULT) | \
227     0)
228 #define SYNC_INTERRUPTS ( \
229     INT_MASK(INT_SINGLE_STEP_3) | \
230     INT_MASK(INT_SINGLE_STEP_2) | \
231     INT_MASK(INT_SINGLE_STEP_1) | \
232     INT_MASK(INT_SINGLE_STEP_0) | \
233     INT_MASK(INT_IDN_COMPLETE) | \
234     INT_MASK(INT_UDN_COMPLETE) | \
235     INT_MASK(INT_ITLB_MISS) | \
236     INT_MASK(INT_ILL) | \
237     INT_MASK(INT_GPV) | \
238     INT_MASK(INT_IDN_ACCESS) | \
239     INT_MASK(INT_UDN_ACCESS) | \
240     INT_MASK(INT_SWINT_3) | \
241     INT_MASK(INT_SWINT_2) | \
242     INT_MASK(INT_SWINT_1) | \
243     INT_MASK(INT_SWINT_0) | \
244     INT_MASK(INT_ILL_TRANS) | \
245     INT_MASK(INT_UNALIGN_DATA) | \
246     INT_MASK(INT_DTLB_MISS) | \
247     INT_MASK(INT_DTLB_ACCESS) | \
248     0)
249 #define NON_SYNC_INTERRUPTS ( \
250     INT_MASK(INT_MEM_ERROR) | \
251     INT_MASK(INT_IDN_FIREWALL) | \
252     INT_MASK(INT_UDN_FIREWALL) | \
253     INT_MASK(INT_TILE_TIMER) | \
254     INT_MASK(INT_AUX_TILE_TIMER) | \
255     INT_MASK(INT_IDN_TIMER) | \
256     INT_MASK(INT_UDN_TIMER) | \
257     INT_MASK(INT_IDN_AVAIL) | \
258     INT_MASK(INT_UDN_AVAIL) | \
259     INT_MASK(INT_IPI_3) | \
260     INT_MASK(INT_IPI_2) | \
261     INT_MASK(INT_IPI_1) | \
262     INT_MASK(INT_IPI_0) | \
263     INT_MASK(INT_PERF_COUNT) | \
264     INT_MASK(INT_AUX_PERF_COUNT) | \
265     INT_MASK(INT_INTCTRL_3) | \
266     INT_MASK(INT_INTCTRL_2) | \
267     INT_MASK(INT_INTCTRL_1) | \
268     INT_MASK(INT_INTCTRL_0) | \
269     INT_MASK(INT_BOOT_ACCESS) | \
270     INT_MASK(INT_WORLD_ACCESS) | \
271     INT_MASK(INT_I_ASID) | \
272     INT_MASK(INT_D_ASID) | \
273     INT_MASK(INT_DOUBLE_FAULT) | \
274     0)
275 #endif /* !__ASSEMBLER__ */
276 #endif /* !__ARCH_INTERRUPTS_H__ */
277