1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2/* 3 * Samsung's Exynos 2200 SoC device tree source 4 * 5 * Copyright (c) 2025, Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> 6 */ 7 8#include <dt-bindings/clock/samsung,exynos2200-cmu.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 compatible = "samsung,exynos2200"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 interrupt-parent = <&gic>; 17 18 aliases { 19 pinctrl0 = &pinctrl_alive; 20 pinctrl1 = &pinctrl_cmgp; 21 pinctrl2 = &pinctrl_hsi1; 22 pinctrl3 = &pinctrl_ufs; 23 pinctrl4 = &pinctrl_hsi1ufs; 24 pinctrl5 = &pinctrl_peric0; 25 pinctrl6 = &pinctrl_peric1; 26 pinctrl7 = &pinctrl_peric2; 27 pinctrl8 = &pinctrl_vts; 28 }; 29 30 xtcxo: clock-1 { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 clock-output-names = "oscclk"; 34 }; 35 36 ext_26m: clock-2 { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-output-names = "ext-26m"; 40 }; 41 42 ext_200m: clock-3 { 43 compatible = "fixed-clock"; 44 #clock-cells = <0>; 45 clock-output-names = "ext-200m"; 46 }; 47 48 cpus { 49 #address-cells = <1>; 50 #size-cells = <0>; 51 52 cpu-map { 53 cluster0 { 54 core0 { 55 cpu = <&cpu0>; 56 }; 57 58 core1 { 59 cpu = <&cpu1>; 60 }; 61 62 core2 { 63 cpu = <&cpu2>; 64 }; 65 66 core3 { 67 cpu = <&cpu3>; 68 }; 69 }; 70 71 cluster1 { 72 core0 { 73 cpu = <&cpu4>; 74 }; 75 76 core1 { 77 cpu = <&cpu5>; 78 }; 79 80 core2 { 81 cpu = <&cpu6>; 82 }; 83 }; 84 85 cluster2 { 86 core0 { 87 cpu = <&cpu7>; 88 }; 89 }; 90 }; 91 92 cpu0: cpu@0 { 93 device_type = "cpu"; 94 compatible = "arm,cortex-a510"; 95 reg = <0>; 96 capacity-dmips-mhz = <260>; 97 dynamic-power-coefficient = <189>; 98 enable-method = "psci"; 99 cpu-idle-states = <&little_cpu_sleep>; 100 }; 101 102 cpu1: cpu@100 { 103 device_type = "cpu"; 104 compatible = "arm,cortex-a510"; 105 reg = <0x100>; 106 capacity-dmips-mhz = <260>; 107 dynamic-power-coefficient = <189>; 108 enable-method = "psci"; 109 cpu-idle-states = <&little_cpu_sleep>; 110 }; 111 112 cpu2: cpu@200 { 113 device_type = "cpu"; 114 compatible = "arm,cortex-a510"; 115 reg = <0x200>; 116 capacity-dmips-mhz = <260>; 117 dynamic-power-coefficient = <189>; 118 enable-method = "psci"; 119 cpu-idle-states = <&little_cpu_sleep>; 120 }; 121 122 cpu3: cpu@300 { 123 device_type = "cpu"; 124 compatible = "arm,cortex-a510"; 125 reg = <0x300>; 126 capacity-dmips-mhz = <260>; 127 dynamic-power-coefficient = <189>; 128 enable-method = "psci"; 129 cpu-idle-states = <&little_cpu_sleep>; 130 }; 131 132 cpu4: cpu@400 { 133 device_type = "cpu"; 134 compatible = "arm,cortex-a710"; 135 reg = <0x400>; 136 capacity-dmips-mhz = <380>; 137 dynamic-power-coefficient = <560>; 138 enable-method = "psci"; 139 cpu-idle-states = <&big_cpu_sleep>; 140 }; 141 142 cpu5: cpu@500 { 143 device_type = "cpu"; 144 compatible = "arm,cortex-a710"; 145 reg = <0x500>; 146 capacity-dmips-mhz = <380>; 147 dynamic-power-coefficient = <560>; 148 enable-method = "psci"; 149 cpu-idle-states = <&big_cpu_sleep>; 150 }; 151 152 cpu6: cpu@600 { 153 device_type = "cpu"; 154 compatible = "arm,cortex-a710"; 155 reg = <0x600>; 156 capacity-dmips-mhz = <380>; 157 dynamic-power-coefficient = <560>; 158 enable-method = "psci"; 159 cpu-idle-states = <&big_cpu_sleep>; 160 }; 161 162 cpu7: cpu@700 { 163 device_type = "cpu"; 164 compatible = "arm,cortex-x2"; 165 reg = <0x700>; 166 capacity-dmips-mhz = <488>; 167 dynamic-power-coefficient = <765>; 168 enable-method = "psci"; 169 cpu-idle-states = <&prime_cpu_sleep>; 170 }; 171 172 idle-states { 173 entry-method = "psci"; 174 175 little_cpu_sleep: cpu-sleep-0 { 176 compatible = "arm,idle-state"; 177 idle-state-name = "c2"; 178 entry-latency-us = <70>; 179 exit-latency-us = <170>; 180 min-residency-us = <2000>; 181 arm,psci-suspend-param = <0x10000>; 182 }; 183 184 big_cpu_sleep: cpu-sleep-1 { 185 compatible = "arm,idle-state"; 186 idle-state-name = "c2"; 187 entry-latency-us = <235>; 188 exit-latency-us = <220>; 189 min-residency-us = <3500>; 190 arm,psci-suspend-param = <0x10000>; 191 }; 192 193 prime_cpu_sleep: cpu-sleep-2 { 194 compatible = "arm,idle-state"; 195 idle-state-name = "c2"; 196 entry-latency-us = <150>; 197 exit-latency-us = <190>; 198 min-residency-us = <2500>; 199 arm,psci-suspend-param = <0x10000>; 200 }; 201 }; 202 }; 203 204 pmu-a510 { 205 compatible = "arm,cortex-a510-pmu"; 206 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 207 }; 208 209 pmu-a710 { 210 compatible = "arm,cortex-a710-pmu"; 211 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 212 }; 213 214 pmu-x2 { 215 compatible = "arm,cortex-x2-pmu"; 216 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster2>; 217 }; 218 219 psci { 220 compatible = "arm,psci-1.0"; 221 method = "smc"; 222 }; 223 224 soc { 225 compatible = "simple-bus"; 226 ranges; 227 228 #address-cells = <2>; 229 #size-cells = <2>; 230 231 chipid@10000000 { 232 compatible = "samsung,exynos2200-chipid", 233 "samsung,exynos850-chipid"; 234 reg = <0x0 0x10000000 0x0 0x24>; 235 }; 236 237 cmu_peris: clock-controller@10020000 { 238 compatible = "samsung,exynos2200-cmu-peris"; 239 reg = <0x0 0x10020000 0x0 0x8000>; 240 #clock-cells = <1>; 241 242 clocks = <&cmu_top CLK_DOUT_TCXO_DIV3>, 243 <&cmu_top CLK_DOUT_CMU_PERIS_NOC>, 244 <&cmu_top CLK_DOUT_CMU_PERIS_GIC>; 245 clock-names = "tcxo_div3", 246 "noc", 247 "gic"; 248 }; 249 250 mct_peris: timer@10040000 { 251 compatible = "samsung,exynos2200-mct-peris", 252 "samsung,exynos4210-mct"; 253 reg = <0x0 0x10040000 0x0 0x800>; 254 clocks = <&cmu_top CLK_DOUT_TCXO_DIV3>, <&cmu_peris CLK_MOUT_PERIS_GIC>; 255 clock-names = "fin_pll", "mct"; 256 interrupts = <GIC_SPI 943 IRQ_TYPE_LEVEL_HIGH 0>, 257 <GIC_SPI 944 IRQ_TYPE_LEVEL_HIGH 0>, 258 <GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH 0>, 259 <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH 0>, 260 <GIC_SPI 947 IRQ_TYPE_LEVEL_HIGH 0>, 261 <GIC_SPI 948 IRQ_TYPE_LEVEL_HIGH 0>, 262 <GIC_SPI 949 IRQ_TYPE_LEVEL_HIGH 0>, 263 <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH 0>, 264 <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH 0>, 265 <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH 0>, 266 <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH 0>, 267 <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH 0>; 268 status = "disabled"; 269 }; 270 271 gic: interrupt-controller@10200000 { 272 compatible = "arm,gic-v3"; 273 reg = <0x0 0x10200000 0x0 0x10000>, /* GICD */ 274 <0x0 0x10240000 0x0 0x200000>; /* GICR * 8 */ 275 276 #interrupt-cells = <4>; 277 interrupt-controller; 278 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 279 280 ppi-partitions { 281 ppi_cluster0: interrupt-partition-0 { 282 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 283 }; 284 285 ppi_cluster1: interrupt-partition-1 { 286 affinity = <&cpu4 &cpu5 &cpu6>; 287 }; 288 289 ppi_cluster2: interrupt-partition-2 { 290 affinity = <&cpu7>; 291 }; 292 }; 293 }; 294 295 cmu_peric0: clock-controller@10400000 { 296 compatible = "samsung,exynos2200-cmu-peric0"; 297 reg = <0x0 0x10400000 0x0 0x8000>; 298 #clock-cells = <1>; 299 300 clocks = <&xtcxo>, 301 <&cmu_top CLK_DOUT_CMU_PERIC0_NOC>, 302 <&cmu_top CLK_DOUT_CMU_PERIC0_IP0>, 303 <&cmu_top CLK_DOUT_CMU_PERIC0_IP1>; 304 clock-names = "oscclk", "noc", "ip0", "ip1"; 305 }; 306 307 syscon_peric0: syscon@10420000 { 308 compatible = "samsung,exynos2200-peric0-sysreg", "syscon"; 309 reg = <0x0 0x10420000 0x0 0x2000>; 310 }; 311 312 pinctrl_peric0: pinctrl@10430000 { 313 compatible = "samsung,exynos2200-pinctrl"; 314 reg = <0x0 0x10430000 0x0 0x1000>; 315 }; 316 317 cmu_peric1: clock-controller@10700000 { 318 compatible = "samsung,exynos2200-cmu-peric1"; 319 reg = <0x0 0x10700000 0x0 0x8000>; 320 #clock-cells = <1>; 321 322 clocks = <&xtcxo>, 323 <&cmu_top CLK_DOUT_CMU_PERIC1_NOC>, 324 <&cmu_top CLK_DOUT_CMU_PERIC1_IP0>, 325 <&cmu_top CLK_DOUT_CMU_PERIC1_IP1>; 326 clock-names = "oscclk", "noc", "ip0", "ip1"; 327 }; 328 329 syscon_peric1: syscon@10720000 { 330 compatible = "samsung,exynos2200-peric1-sysreg", "syscon"; 331 reg = <0x0 0x10720000 0x0 0x2000>; 332 }; 333 334 pinctrl_peric1: pinctrl@10730000 { 335 compatible = "samsung,exynos2200-pinctrl"; 336 reg = <0x0 0x10730000 0x0 0x1000>; 337 }; 338 339 cmu_hsi0: clock-controller@10a00000 { 340 compatible = "samsung,exynos2200-cmu-hsi0"; 341 reg = <0x0 0x10a00000 0x0 0x8000>; 342 #clock-cells = <1>; 343 }; 344 345 usb32drd: phy@10aa0000 { 346 compatible = "samsung,exynos2200-usb32drd-phy"; 347 reg = <0x0 0x10aa0000 0x0 0x10000>; 348 349 clocks = <&cmu_hsi0 CLK_MOUT_HSI0_NOC>; 350 clock-names = "phy"; 351 352 #phy-cells = <1>; 353 phys = <&usb_hsphy>; 354 phy-names = "hs"; 355 356 samsung,pmu-syscon = <&pmu_system_controller>; 357 358 status = "disabled"; 359 }; 360 361 usb_hsphy: phy@10ab0000 { 362 compatible = "samsung,exynos2200-eusb2-phy"; 363 reg = <0x0 0x10ab0000 0x0 0x10000>; 364 365 clocks = <&cmu_hsi0 CLK_MOUT_HSI0_USB32DRD>, 366 <&cmu_hsi0 CLK_MOUT_HSI0_NOC>, 367 <&cmu_hsi0 CLK_DOUT_DIV_CLK_HSI0_EUSB>; 368 clock-names = "ref", "bus", "ctrl"; 369 370 #phy-cells = <0>; 371 372 status = "disabled"; 373 }; 374 375 usb: usb@10b00000 { 376 compatible = "samsung,exynos2200-dwusb3"; 377 ranges = <0x0 0x0 0x10b00000 0x10000>; 378 379 clocks = <&cmu_hsi0 CLK_MOUT_HSI0_NOC>; 380 clock-names = "link_aclk"; 381 382 #address-cells = <1>; 383 #size-cells = <1>; 384 385 status = "disabled"; 386 387 usb_dwc3: usb@0 { 388 compatible = "snps,dwc3"; 389 reg = <0x0 0x10000>; 390 391 clocks = <&cmu_hsi0 CLK_MOUT_HSI0_USB32DRD>; 392 clock-names = "ref"; 393 394 interrupts = <GIC_SPI 485 IRQ_TYPE_LEVEL_HIGH 0>; 395 396 phys = <&usb32drd 0>; 397 phy-names = "usb2-phy"; 398 399 snps,dis-u2-freeclk-exists-quirk; 400 snps,gfladj-refclk-lpm-sel-quirk; 401 snps,has-lpm-erratum; 402 snps,quirk-frame-length-adjustment = <0x20>; 403 snps,usb3_lpm_capable; 404 }; 405 }; 406 407 cmu_ufs: clock-controller@11000000 { 408 compatible = "samsung,exynos2200-cmu-ufs"; 409 reg = <0x0 0x11000000 0x0 0x8000>; 410 #clock-cells = <1>; 411 412 clocks = <&xtcxo>, 413 <&cmu_top CLK_DOUT_CMU_UFS_NOC>, 414 <&cmu_top CLK_MOUT_CMU_UFS_MMC_CARD>, 415 <&cmu_top CLK_DOUT_CMU_UFS_UFS_EMBD>; 416 clock-names = "oscclk", "noc", "mmc", "ufs"; 417 }; 418 419 syscon_ufs: syscon@11020000 { 420 compatible = "samsung,exynos2200-ufs-sysreg", "syscon"; 421 reg = <0x0 0x11020000 0x0 0x2000>; 422 }; 423 424 pinctrl_ufs: pinctrl@11040000 { 425 compatible = "samsung,exynos2200-pinctrl"; 426 reg = <0x0 0x11040000 0x0 0x1000>; 427 }; 428 429 pinctrl_hsi1ufs: pinctrl@11060000 { 430 compatible = "samsung,exynos2200-pinctrl"; 431 reg = <0x0 0x11060000 0x0 0x1000>; 432 }; 433 434 pinctrl_hsi1: pinctrl@11240000 { 435 compatible = "samsung,exynos2200-pinctrl"; 436 reg = <0x0 0x11240000 0x0 0x1000>; 437 }; 438 439 cmu_peric2: clock-controller@11c00000 { 440 compatible = "samsung,exynos2200-cmu-peric2"; 441 reg = <0x0 0x11c00000 0x0 0x8000>; 442 #clock-cells = <1>; 443 444 clocks = <&xtcxo>, 445 <&cmu_top CLK_DOUT_CMU_PERIC2_NOC>, 446 <&cmu_top CLK_DOUT_CMU_PERIC2_IP0>, 447 <&cmu_top CLK_DOUT_CMU_PERIC2_IP1>; 448 clock-names = "oscclk", "noc", "ip0", "ip1"; 449 }; 450 451 syscon_peric2: syscon@11c20000 { 452 compatible = "samsung,exynos2200-peric2-sysreg", "syscon"; 453 reg = <0x0 0x11c20000 0x0 0x4000>; 454 }; 455 456 pinctrl_peric2: pinctrl@11c30000 { 457 compatible = "samsung,exynos2200-pinctrl"; 458 reg = <0x0 0x11c30000 0x0 0x1000>; 459 }; 460 461 cmu_cmgp: clock-controller@14e00000 { 462 compatible = "samsung,exynos2200-cmu-cmgp"; 463 reg = <0x0 0x14e00000 0x0 0x8000>; 464 #clock-cells = <1>; 465 466 clocks = <&xtcxo>, 467 <&cmu_alive CLK_DOUT_ALIVE_CMGP_NOC>, 468 <&cmu_alive CLK_DOUT_ALIVE_CMGP_PERI>; 469 clock-names = "oscclk", "noc", "peri"; 470 }; 471 472 syscon_cmgp: syscon@14e20000 { 473 compatible = "samsung,exynos2200-cmgp-sysreg", "syscon"; 474 reg = <0x0 0x14e20000 0x0 0x2000>; 475 }; 476 477 pinctrl_cmgp: pinctrl@14e30000 { 478 compatible = "samsung,exynos2200-pinctrl"; 479 reg = <0x0 0x14e30000 0x0 0x1000>; 480 481 wakeup-interrupt-controller { 482 compatible = "samsung,exynos2200-wakeup-eint", 483 "samsung,exynos850-wakeup-eint", 484 "samsung,exynos7-wakeup-eint"; 485 }; 486 }; 487 488 cmu_vts: clock-controller@15300000 { 489 compatible = "samsung,exynos2200-cmu-vts"; 490 reg = <0x0 0x15300000 0x0 0x8000>; 491 #clock-cells = <1>; 492 493 clocks = <&xtcxo>, 494 <&cmu_top CLK_DOUT_CMU_VTS_DMIC>; 495 clock-names = "oscclk", "dmic"; 496 }; 497 498 pinctrl_vts: pinctrl@15320000 { 499 compatible = "samsung,exynos2200-pinctrl"; 500 reg = <0x0 0x15320000 0x0 0x1000>; 501 }; 502 503 cmu_alive: clock-controller@15800000 { 504 compatible = "samsung,exynos2200-cmu-alive"; 505 reg = <0x0 0x15800000 0x0 0x8000>; 506 #clock-cells = <1>; 507 508 clocks = <&xtcxo>, 509 <&cmu_top CLK_DOUT_CMU_ALIVE_NOC>; 510 clock-names = "oscclk", "noc"; 511 }; 512 513 pinctrl_alive: pinctrl@15850000 { 514 compatible = "samsung,exynos2200-pinctrl"; 515 reg = <0x0 0x15850000 0x0 0x1000>; 516 517 wakeup-interrupt-controller { 518 compatible = "samsung,exynos2200-wakeup-eint", 519 "samsung,exynos850-wakeup-eint", 520 "samsung,exynos7-wakeup-eint"; 521 }; 522 }; 523 524 pmu_system_controller: system-controller@15860000 { 525 compatible = "samsung,exynos2200-pmu", 526 "samsung,exynos7-pmu", "syscon"; 527 reg = <0x0 0x15860000 0x0 0x10000>; 528 529 reboot: syscon-reboot { 530 compatible = "syscon-reboot"; 531 offset = <0x3c00>; /* SYSTEM_CONFIGURATION */ 532 mask = <0x2>; /* SWRESET_SYSTEM */ 533 value = <0x2>; /* reset value */ 534 }; 535 }; 536 537 cmu_top: clock-controller@1a320000 { 538 compatible = "samsung,exynos2200-cmu-top"; 539 reg = <0x0 0x1a320000 0x0 0x8000>; 540 #clock-cells = <1>; 541 542 clocks = <&xtcxo>; 543 clock-names = "oscclk"; 544 }; 545 }; 546 547 timer { 548 compatible = "arm,armv8-timer"; 549 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 550 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 551 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 552 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 553 /* 554 * Non-updatable, broken stock Samsung bootloader does not 555 * configure CNTFRQ_EL0 556 */ 557 clock-frequency = <25600000>; 558 }; 559}; 560 561#include "exynos2200-pinctrl.dtsi" 562