1 /*
2 * QEMU Eyetech AmigaOne/Mai Logic Teron emulation
3 *
4 * Copyright (c) 2023 BALATON Zoltan
5 *
6 * This work is licensed under the GNU GPL license version 2 or later.
7 *
8 */
9
10 #include "qemu/osdep.h"
11 #include "qemu/units.h"
12 #include "qemu/datadir.h"
13 #include "qemu/log.h"
14 #include "qemu/error-report.h"
15 #include "qapi/error.h"
16 #include "hw/ppc/ppc.h"
17 #include "hw/boards.h"
18 #include "hw/loader.h"
19 #include "hw/pci-host/articia.h"
20 #include "hw/isa/vt82c686.h"
21 #include "hw/ide/pci.h"
22 #include "hw/i2c/smbus_eeprom.h"
23 #include "hw/ppc/ppc.h"
24 #include "system/block-backend.h"
25 #include "system/qtest.h"
26 #include "system/reset.h"
27 #include "kvm_ppc.h"
28 #include "elf.h"
29
30 #include <zlib.h> /* for crc32 */
31
32 #define BUS_FREQ_HZ 100000000
33
34 #define INITRD_MIN_ADDR 0x600000
35 #define INIT_RAM_ADDR 0x40000000
36
37 #define PCI_HIGH_ADDR 0x80000000
38 #define PCI_HIGH_SIZE 0x7d000000
39 #define PCI_LOW_ADDR 0xfd000000
40 #define PCI_LOW_SIZE 0xe0000
41
42 #define ARTICIA_ADDR 0xfe000000
43
44 /*
45 * Firmware binary available at
46 * https://www.hyperion-entertainment.com/index.php/downloads?view=files&parent=28
47 * then "tail -c 524288 updater.image >u-boot-amigaone.bin"
48 *
49 * BIOS emulator in firmware cannot run QEMU vgabios and hangs on it, use
50 * -device VGA,romfile=VGABIOS-lgpl-latest.bin
51 * from http://www.nongnu.org/vgabios/ instead.
52 */
53 #define PROM_ADDR 0xfff00000
54 #define PROM_SIZE (512 * KiB)
55
56 /* AmigaOS calls this routine from ROM, use this if no firmware loaded */
57 static const char dummy_fw[] = {
58 0x54, 0x63, 0xc2, 0x3e, /* srwi r3,r3,8 */
59 0x7c, 0x63, 0x18, 0xf8, /* not r3,r3 */
60 0x4e, 0x80, 0x00, 0x20, /* blr */
61 };
62
63 #define NVRAM_ADDR 0xfd0e0000
64 #define NVRAM_SIZE (4 * KiB)
65
66 static const char default_env[] =
67 "baudrate=115200\0"
68 "stdout=vga\0"
69 "stdin=ps2kbd\0"
70 "bootcmd=boota; menu; run menuboot_cmd\0"
71 "boot1=ide\0"
72 "boot2=cdrom\0"
73 "boota_timeout=3\0"
74 "ide_doreset=on\0"
75 "pci_irqa=9\0"
76 "pci_irqa_select=level\0"
77 "pci_irqb=10\0"
78 "pci_irqb_select=level\0"
79 "pci_irqc=11\0"
80 "pci_irqc_select=level\0"
81 "pci_irqd=7\0"
82 "pci_irqd_select=level\0"
83 "a1ide_irq=1111\0"
84 "a1ide_xfer=FFFF\0";
85 #define CRC32_DEFAULT_ENV 0xb5548481
86 #define CRC32_ALL_ZEROS 0x603b0489
87
88 #define TYPE_A1_NVRAM "a1-nvram"
89 OBJECT_DECLARE_SIMPLE_TYPE(A1NVRAMState, A1_NVRAM)
90
91 struct A1NVRAMState {
92 SysBusDevice parent_obj;
93
94 MemoryRegion mr;
95 BlockBackend *blk;
96 };
97
nvram_read(void * opaque,hwaddr addr,unsigned int size)98 static uint64_t nvram_read(void *opaque, hwaddr addr, unsigned int size)
99 {
100 /* read callback not used because of romd mode */
101 g_assert_not_reached();
102 }
103
nvram_write(void * opaque,hwaddr addr,uint64_t val,unsigned int size)104 static void nvram_write(void *opaque, hwaddr addr, uint64_t val,
105 unsigned int size)
106 {
107 A1NVRAMState *s = opaque;
108 uint8_t *p = memory_region_get_ram_ptr(&s->mr);
109
110 p[addr] = val;
111 if (s->blk && blk_pwrite(s->blk, addr, 1, &val, 0) < 0) {
112 error_report("%s: could not write %s", __func__, blk_name(s->blk));
113 }
114 }
115
116 static const MemoryRegionOps nvram_ops = {
117 .read = nvram_read,
118 .write = nvram_write,
119 .endianness = DEVICE_BIG_ENDIAN,
120 .impl = {
121 .min_access_size = 1,
122 .max_access_size = 1,
123 },
124 };
125
nvram_realize(DeviceState * dev,Error ** errp)126 static void nvram_realize(DeviceState *dev, Error **errp)
127 {
128 A1NVRAMState *s = A1_NVRAM(dev);
129 void *p;
130 uint32_t crc, *c;
131
132 memory_region_init_rom_device(&s->mr, NULL, &nvram_ops, s, "nvram",
133 NVRAM_SIZE, &error_fatal);
134 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mr);
135 c = p = memory_region_get_ram_ptr(&s->mr);
136 if (s->blk) {
137 if (blk_getlength(s->blk) != NVRAM_SIZE) {
138 error_setg(errp, "NVRAM backing file size must be %" PRId64 "bytes",
139 NVRAM_SIZE);
140 return;
141 }
142 blk_set_perm(s->blk, BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE,
143 BLK_PERM_ALL, &error_fatal);
144 if (blk_pread(s->blk, 0, NVRAM_SIZE, p, 0) < 0) {
145 error_setg(errp, "Cannot read NVRAM contents from backing file");
146 return;
147 }
148 }
149 crc = crc32(0, p + 4, NVRAM_SIZE - 4);
150 if (crc == CRC32_ALL_ZEROS) { /* If env is uninitialized set default */
151 *c = cpu_to_be32(CRC32_DEFAULT_ENV);
152 /* Also copies terminating \0 as env is terminated by \0\0 */
153 memcpy(p + 4, default_env, sizeof(default_env));
154 if (s->blk &&
155 blk_pwrite(s->blk, 0, sizeof(crc) + sizeof(default_env), p, 0) < 0
156 ) {
157 error_report("%s: could not write %s", __func__, blk_name(s->blk));
158 }
159 return;
160 }
161 if (*c == 0) {
162 *c = cpu_to_be32(crc32(0, p + 4, NVRAM_SIZE - 4));
163 if (s->blk && blk_pwrite(s->blk, 0, 4, p, 0) < 0) {
164 error_report("%s: could not write %s", __func__, blk_name(s->blk));
165 }
166 }
167 if (be32_to_cpu(*c) != crc) {
168 warn_report("NVRAM checksum mismatch");
169 }
170 }
171
172 static const Property nvram_properties[] = {
173 DEFINE_PROP_DRIVE("drive", A1NVRAMState, blk),
174 };
175
nvram_class_init(ObjectClass * oc,const void * data)176 static void nvram_class_init(ObjectClass *oc, const void *data)
177 {
178 DeviceClass *dc = DEVICE_CLASS(oc);
179
180 dc->realize = nvram_realize;
181 device_class_set_props(dc, nvram_properties);
182 }
183
184 static const TypeInfo nvram_types[] = {
185 {
186 .name = TYPE_A1_NVRAM,
187 .parent = TYPE_SYS_BUS_DEVICE,
188 .instance_size = sizeof(A1NVRAMState),
189 .class_init = nvram_class_init,
190 },
191 };
192 DEFINE_TYPES(nvram_types)
193
194 struct boot_info {
195 hwaddr entry;
196 hwaddr stack;
197 hwaddr bd_info;
198 hwaddr initrd_start;
199 hwaddr initrd_end;
200 hwaddr cmdline_start;
201 hwaddr cmdline_end;
202 };
203
204 /* Board info struct from U-Boot */
205 struct bd_info {
206 uint32_t bi_memstart;
207 uint32_t bi_memsize;
208 uint32_t bi_flashstart;
209 uint32_t bi_flashsize;
210 uint32_t bi_flashoffset;
211 uint32_t bi_sramstart;
212 uint32_t bi_sramsize;
213 uint32_t bi_bootflags;
214 uint32_t bi_ip_addr;
215 uint8_t bi_enetaddr[6];
216 uint16_t bi_ethspeed;
217 uint32_t bi_intfreq;
218 uint32_t bi_busfreq;
219 uint32_t bi_baudrate;
220 } QEMU_PACKED;
221
create_bd_info(hwaddr addr,ram_addr_t ram_size)222 static void create_bd_info(hwaddr addr, ram_addr_t ram_size)
223 {
224 struct bd_info *bd = g_new0(struct bd_info, 1);
225
226 bd->bi_memsize = cpu_to_be32(ram_size);
227 bd->bi_flashstart = cpu_to_be32(PROM_ADDR);
228 bd->bi_flashsize = cpu_to_be32(1); /* match what U-Boot detects */
229 bd->bi_bootflags = cpu_to_be32(1);
230 bd->bi_intfreq = cpu_to_be32(11.5 * BUS_FREQ_HZ);
231 bd->bi_busfreq = cpu_to_be32(BUS_FREQ_HZ);
232 bd->bi_baudrate = cpu_to_be32(115200);
233
234 cpu_physical_memory_write(addr, bd, sizeof(*bd));
235 }
236
amigaone_cpu_reset(void * opaque)237 static void amigaone_cpu_reset(void *opaque)
238 {
239 PowerPCCPU *cpu = opaque;
240 CPUPPCState *env = &cpu->env;
241
242 cpu_reset(CPU(cpu));
243 if (env->load_info) {
244 struct boot_info *bi = env->load_info;
245
246 env->gpr[1] = bi->stack;
247 env->gpr[2] = 1024;
248 env->gpr[3] = bi->bd_info;
249 env->gpr[4] = bi->initrd_start;
250 env->gpr[5] = bi->initrd_end;
251 env->gpr[6] = bi->cmdline_start;
252 env->gpr[7] = bi->cmdline_end;
253 env->nip = bi->entry;
254 }
255 cpu_ppc_tb_reset(env);
256 }
257
fix_spd_data(uint8_t * spd)258 static void fix_spd_data(uint8_t *spd)
259 {
260 uint32_t bank_size = 4 * MiB * spd[31];
261 uint32_t rows = bank_size / spd[13] / spd[17];
262 spd[3] = ctz32(rows) - spd[4];
263 }
264
amigaone_init(MachineState * machine)265 static void amigaone_init(MachineState *machine)
266 {
267 PowerPCCPU *cpu;
268 CPUPPCState *env;
269 MemoryRegion *rom, *pci_mem, *mr;
270 ssize_t sz;
271 PCIBus *pci_bus;
272 Object *via;
273 DeviceState *dev;
274 I2CBus *i2c_bus;
275 uint8_t *spd_data;
276 DriveInfo *di;
277 hwaddr loadaddr;
278 struct boot_info *bi = NULL;
279
280 /* init CPU */
281 cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
282 env = &cpu->env;
283 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
284 error_report("Incompatible CPU, only 6xx bus supported");
285 exit(1);
286 }
287 cpu_ppc_tb_init(env, BUS_FREQ_HZ / 4);
288 qemu_register_reset(amigaone_cpu_reset, cpu);
289
290 /* RAM */
291 if (machine->ram_size > 2 * GiB) {
292 error_report("RAM size more than 2 GiB is not supported");
293 exit(1);
294 }
295 memory_region_add_subregion(get_system_memory(), 0, machine->ram);
296 if (machine->ram_size < 1 * GiB + 32 * KiB) {
297 /* Firmware uses this area for startup */
298 mr = g_new(MemoryRegion, 1);
299 memory_region_init_ram(mr, NULL, "init-cache", 32 * KiB, &error_fatal);
300 memory_region_add_subregion(get_system_memory(), INIT_RAM_ADDR, mr);
301 }
302
303 /* nvram */
304 dev = qdev_new(TYPE_A1_NVRAM);
305 di = drive_get(IF_MTD, 0, 0);
306 if (di) {
307 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(di));
308 }
309 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
310 memory_region_add_subregion(get_system_memory(), NVRAM_ADDR,
311 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0));
312
313 /* allocate and load firmware */
314 rom = g_new(MemoryRegion, 1);
315 memory_region_init_rom(rom, NULL, "rom", PROM_SIZE, &error_fatal);
316 memory_region_add_subregion(get_system_memory(), PROM_ADDR, rom);
317 if (!machine->firmware) {
318 rom_add_blob_fixed("dummy-fw", dummy_fw, sizeof(dummy_fw),
319 PROM_ADDR + PROM_SIZE - 0x80);
320 } else {
321 g_autofree char *filename = qemu_find_file(QEMU_FILE_TYPE_BIOS,
322 machine->firmware);
323 if (!filename) {
324 error_report("Could not find firmware '%s'", machine->firmware);
325 exit(1);
326 }
327 sz = load_image_targphys(filename, PROM_ADDR, PROM_SIZE);
328 if (sz <= 0 || sz > PROM_SIZE) {
329 error_report("Could not load firmware '%s'", filename);
330 exit(1);
331 }
332 }
333
334 /* Articia S */
335 dev = sysbus_create_simple(TYPE_ARTICIA, ARTICIA_ADDR, NULL);
336
337 i2c_bus = I2C_BUS(qdev_get_child_bus(dev, "smbus"));
338 if (machine->ram_size > 512 * MiB) {
339 spd_data = spd_data_generate(SDR, machine->ram_size / 2);
340 } else {
341 spd_data = spd_data_generate(SDR, machine->ram_size);
342 }
343 fix_spd_data(spd_data);
344 smbus_eeprom_init_one(i2c_bus, 0x51, spd_data);
345 if (machine->ram_size > 512 * MiB) {
346 smbus_eeprom_init_one(i2c_bus, 0x52, spd_data);
347 }
348
349 pci_mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
350 mr = g_new(MemoryRegion, 1);
351 memory_region_init_alias(mr, OBJECT(dev), "pci-mem-low", pci_mem,
352 0, PCI_LOW_SIZE);
353 memory_region_add_subregion(get_system_memory(), PCI_LOW_ADDR, mr);
354 mr = g_new(MemoryRegion, 1);
355 memory_region_init_alias(mr, OBJECT(dev), "pci-mem-high", pci_mem,
356 PCI_HIGH_ADDR, PCI_HIGH_SIZE);
357 memory_region_add_subregion(get_system_memory(), PCI_HIGH_ADDR, mr);
358 pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0"));
359
360 /* VIA VT82c686B South Bridge (multifunction PCI device) */
361 via = OBJECT(pci_create_simple_multifunction(pci_bus, PCI_DEVFN(7, 0),
362 TYPE_VT82C686B_ISA));
363 object_property_add_alias(OBJECT(machine), "rtc-time",
364 object_resolve_path_component(via, "rtc"),
365 "date");
366 qdev_connect_gpio_out_named(DEVICE(via), "intr", 0,
367 qdev_get_gpio_in(DEVICE(cpu),
368 PPC6xx_INPUT_INT));
369 for (int i = 0; i < PCI_NUM_PINS; i++) {
370 qdev_connect_gpio_out(dev, i, qdev_get_gpio_in_named(DEVICE(via),
371 "pirq", i));
372 }
373 pci_ide_create_devs(PCI_DEVICE(object_resolve_path_component(via, "ide")));
374 pci_vga_init(pci_bus);
375
376 if (!machine->kernel_filename) {
377 return;
378 }
379
380 /* handle -kernel, -initrd, -append options and emulate U-Boot */
381 bi = g_new0(struct boot_info, 1);
382 cpu->env.load_info = bi;
383
384 loadaddr = MIN(machine->ram_size, 256 * MiB);
385 bi->bd_info = loadaddr - 8 * MiB;
386 create_bd_info(bi->bd_info, machine->ram_size);
387 bi->stack = bi->bd_info - 64 * KiB - 8;
388
389 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) {
390 size_t len = strlen(machine->kernel_cmdline);
391
392 loadaddr = bi->bd_info + 1 * MiB;
393 cpu_physical_memory_write(loadaddr, machine->kernel_cmdline, len + 1);
394 bi->cmdline_start = loadaddr;
395 bi->cmdline_end = loadaddr + len + 1; /* including terminating '\0' */
396 }
397
398 sz = load_elf(machine->kernel_filename, NULL, NULL, NULL,
399 &bi->entry, &loadaddr, NULL, NULL,
400 ELFDATA2MSB, PPC_ELF_MACHINE, 0, 0);
401 if (sz <= 0) {
402 sz = load_uimage(machine->kernel_filename, &bi->entry, &loadaddr,
403 NULL, NULL, NULL);
404 }
405 if (sz <= 0) {
406 error_report("Could not load kernel '%s'",
407 machine->kernel_filename);
408 exit(1);
409 }
410 loadaddr += sz;
411
412 if (machine->initrd_filename) {
413 loadaddr = ROUND_UP(loadaddr + 4 * MiB, 4 * KiB);
414 loadaddr = MAX(loadaddr, INITRD_MIN_ADDR);
415 sz = load_image_targphys(machine->initrd_filename, loadaddr,
416 bi->bd_info - loadaddr);
417 if (sz <= 0) {
418 error_report("Could not load initrd '%s'",
419 machine->initrd_filename);
420 exit(1);
421 }
422 bi->initrd_start = loadaddr;
423 bi->initrd_end = loadaddr + sz;
424 }
425 }
426
amigaone_machine_init(MachineClass * mc)427 static void amigaone_machine_init(MachineClass *mc)
428 {
429 mc->desc = "Eyetech AmigaOne/Mai Logic Teron";
430 mc->init = amigaone_init;
431 mc->block_default_type = IF_IDE;
432 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("7457_v1.2");
433 mc->default_display = "std";
434 mc->default_ram_id = "ram";
435 mc->default_ram_size = 512 * MiB;
436 }
437
438 DEFINE_MACHINE("amigaone", amigaone_machine_init)
439