1=========================== 2 drm/i915 Intel GFX Driver 3=========================== 4 5The drm/i915 driver supports all (with the exception of some very early 6models) integrated GFX chipsets with both Intel display and rendering 7blocks. This excludes a set of SoC platforms with an SGX rendering unit, 8those have basic support through the gma500 drm driver. 9 10Core Driver Infrastructure 11========================== 12 13This section covers core driver infrastructure used by both the display 14and the GEM parts of the driver. 15 16Runtime Power Management 17------------------------ 18 19.. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c 20 :doc: runtime pm 21 22.. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c 23 :internal: 24 25.. kernel-doc:: drivers/gpu/drm/i915/intel_uncore.c 26 :internal: 27 28Interrupt Handling 29------------------ 30 31.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c 32 :doc: interrupt handling 33 34.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c 35 :functions: intel_irq_init intel_irq_init_hw intel_hpd_init 36 37.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c 38 :functions: intel_irq_suspend 39 40.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c 41 :functions: intel_irq_resume 42 43Intel GVT-g Guest Support(vGPU) 44------------------------------- 45 46.. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c 47 :doc: Intel GVT-g guest support 48 49.. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c 50 :internal: 51 52Intel GVT-g Host Support(vGPU device model) 53------------------------------------------- 54 55.. kernel-doc:: drivers/gpu/drm/i915/intel_gvt.c 56 :doc: Intel GVT-g host support 57 58.. kernel-doc:: drivers/gpu/drm/i915/intel_gvt.c 59 :internal: 60 61Workarounds 62----------- 63 64.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_workarounds.c 65 :doc: Hardware workarounds 66 67Display Hardware Handling 68========================= 69 70This section covers everything related to the display hardware including 71the mode setting infrastructure, plane, sprite and cursor handling and 72display, output probing and related topics. 73 74Mode Setting Infrastructure 75--------------------------- 76 77The i915 driver is thus far the only DRM driver which doesn't use the 78common DRM helper code to implement mode setting sequences. Thus it has 79its own tailor-made infrastructure for executing a display configuration 80change. 81 82Frontbuffer Tracking 83-------------------- 84 85.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c 86 :doc: frontbuffer tracking 87 88.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.h 89 :internal: 90 91.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c 92 :internal: 93 94Display FIFO Underrun Reporting 95------------------------------- 96 97.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fifo_underrun.c 98 :doc: fifo underrun handling 99 100.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fifo_underrun.c 101 :internal: 102 103Plane Configuration 104------------------- 105 106This section covers plane configuration and composition with the primary 107plane, sprites, cursors and overlays. This includes the infrastructure 108to do atomic vsync'ed updates of all this state and also tightly coupled 109topics like watermark setup and computation, framebuffer compression and 110panel self refresh. 111 112Atomic Plane Helpers 113-------------------- 114 115.. kernel-doc:: drivers/gpu/drm/i915/display/intel_plane.c 116 :doc: atomic plane helpers 117 118.. kernel-doc:: drivers/gpu/drm/i915/display/intel_plane.c 119 :internal: 120 121Asynchronous Page Flip 122---------------------- 123 124.. kernel-doc:: drivers/gpu/drm/i915/display/intel_display.c 125 :doc: asynchronous flip implementation 126 127Output Probing 128-------------- 129 130This section covers output probing and related infrastructure like the 131hotplug interrupt storm detection and mitigation code. Note that the 132i915 driver still uses most of the common DRM helper code for output 133probing, so those sections fully apply. 134 135Hotplug 136------- 137 138.. kernel-doc:: drivers/gpu/drm/i915/display/intel_hotplug.c 139 :doc: Hotplug 140 141.. kernel-doc:: drivers/gpu/drm/i915/display/intel_hotplug.c 142 :internal: 143 144High Definition Audio 145--------------------- 146 147.. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c 148 :doc: High Definition Audio over HDMI and Display Port 149 150.. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c 151 :internal: 152 153.. kernel-doc:: include/drm/intel/i915_component.h 154 :internal: 155 156Intel HDMI LPE Audio Support 157---------------------------- 158 159.. kernel-doc:: drivers/gpu/drm/i915/display/intel_lpe_audio.c 160 :doc: LPE Audio integration for HDMI or DP playback 161 162.. kernel-doc:: drivers/gpu/drm/i915/display/intel_lpe_audio.c 163 :internal: 164 165Panel Self Refresh PSR (PSR/SRD) 166-------------------------------- 167 168.. kernel-doc:: drivers/gpu/drm/i915/display/intel_psr.c 169 :doc: Panel Self Refresh (PSR/SRD) 170 171.. kernel-doc:: drivers/gpu/drm/i915/display/intel_psr.c 172 :internal: 173 174Frame Buffer Compression (FBC) 175------------------------------ 176 177.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fbc.c 178 :doc: Frame Buffer Compression (FBC) 179 180.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fbc.c 181 :internal: 182 183Display Refresh Rate Switching (DRRS) 184------------------------------------- 185 186.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c 187 :doc: Display Refresh Rate Switching (DRRS) 188 189.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c 190 :internal: 191 192DPIO 193---- 194 195.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpio_phy.c 196 :doc: DPIO 197 198DMC Firmware Support 199-------------------- 200 201.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc.c 202 :doc: DMC Firmware Support 203 204.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc.c 205 :internal: 206 207DMC Flip Queue 208-------------------- 209 210.. kernel-doc:: drivers/gpu/drm/i915/display/intel_flipq.c 211 :doc: DMC Flip Queue 212 213DMC wakelock support 214-------------------- 215 216.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc_wl.c 217 :doc: DMC wakelock support 218 219Video BIOS Table (VBT) 220---------------------- 221 222.. kernel-doc:: drivers/gpu/drm/i915/display/intel_bios.c 223 :doc: Video BIOS Table (VBT) 224 225.. kernel-doc:: drivers/gpu/drm/i915/display/intel_bios.c 226 :internal: 227 228.. kernel-doc:: drivers/gpu/drm/i915/display/intel_vbt_defs.h 229 :internal: 230 231Display clocks 232-------------- 233 234.. kernel-doc:: drivers/gpu/drm/i915/display/intel_cdclk.c 235 :doc: CDCLK / RAWCLK 236 237.. kernel-doc:: drivers/gpu/drm/i915/display/intel_cdclk.c 238 :internal: 239 240Display PLLs 241------------ 242 243.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.c 244 :doc: Display PLLs 245 246.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.c 247 :internal: 248 249.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.h 250 :internal: 251 252Display State Buffer 253-------------------- 254 255.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c 256 :doc: DSB 257 258.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c 259 :internal: 260 261GT Programming 262============== 263 264Multicast/Replicated (MCR) Registers 265------------------------------------ 266 267.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_gt_mcr.c 268 :doc: GT Multicast/Replicated (MCR) Register Support 269 270.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_gt_mcr.c 271 :internal: 272 273Memory Management and Command Submission 274======================================== 275 276This sections covers all things related to the GEM implementation in the 277i915 driver. 278 279Intel GPU Basics 280---------------- 281 282An Intel GPU has multiple engines. There are several engine types: 283 284- Render Command Streamer (RCS). An engine for rendering 3D and 285 performing compute. 286- Blitting Command Streamer (BCS). An engine for performing blitting and/or 287 copying operations. 288- Video Command Streamer. An engine used for video encoding and decoding. Also 289 sometimes called 'BSD' in hardware documentation. 290- Video Enhancement Command Streamer (VECS). An engine for video enhancement. 291 Also sometimes called 'VEBOX' in hardware documentation. 292- Compute Command Streamer (CCS). An engine that has access to the media and 293 GPGPU pipelines, but not the 3D pipeline. 294- Graphics Security Controller (GSCCS). A dedicated engine for internal 295 communication with GSC controller on security related tasks like 296 High-bandwidth Digital Content Protection (HDCP), Protected Xe Path (PXP), 297 and HuC firmware authentication. 298 299The Intel GPU family is a family of integrated GPU's using Unified 300Memory Access. For having the GPU "do work", user space will feed the 301GPU batch buffers via one of the ioctls `DRM_IOCTL_I915_GEM_EXECBUFFER2` 302or `DRM_IOCTL_I915_GEM_EXECBUFFER2_WR`. Most such batchbuffers will 303instruct the GPU to perform work (for example rendering) and that work 304needs memory from which to read and memory to which to write. All memory 305is encapsulated within GEM buffer objects (usually created with the ioctl 306`DRM_IOCTL_I915_GEM_CREATE`). An ioctl providing a batchbuffer for the GPU 307to create will also list all GEM buffer objects that the batchbuffer reads 308and/or writes. For implementation details of memory management see 309`GEM BO Management Implementation Details`_. 310 311The i915 driver allows user space to create a context via the ioctl 312`DRM_IOCTL_I915_GEM_CONTEXT_CREATE` which is identified by a 32-bit 313integer. Such a context should be viewed by user-space as -loosely- 314analogous to the idea of a CPU process of an operating system. The i915 315driver guarantees that commands issued to a fixed context are to be 316executed so that writes of a previously issued command are seen by 317reads of following commands. Actions issued between different contexts 318(even if from the same file descriptor) are NOT given that guarantee 319and the only way to synchronize across contexts (even from the same 320file descriptor) is through the use of fences. At least as far back as 321Gen4, also have that a context carries with it a GPU HW context; 322the HW context is essentially (most of at least) the state of a GPU. 323In addition to the ordering guarantees, the kernel will restore GPU 324state via HW context when commands are issued to a context, this saves 325user space the need to restore (most of at least) the GPU state at the 326start of each batchbuffer. The non-deprecated ioctls to submit batchbuffer 327work can pass that ID (in the lower bits of drm_i915_gem_execbuffer2::rsvd1) 328to identify what context to use with the command. 329 330The GPU has its own memory management and address space. The kernel 331driver maintains the memory translation table for the GPU. For older 332GPUs (i.e. those before Gen8), there is a single global such translation 333table, a global Graphics Translation Table (GTT). For newer generation 334GPUs each context has its own translation table, called Per-Process 335Graphics Translation Table (PPGTT). Of important note, is that although 336PPGTT is named per-process it is actually per context. When user space 337submits a batchbuffer, the kernel walks the list of GEM buffer objects 338used by the batchbuffer and guarantees that not only is the memory of 339each such GEM buffer object resident but it is also present in the 340(PP)GTT. If the GEM buffer object is not yet placed in the (PP)GTT, 341then it is given an address. Two consequences of this are: the kernel 342needs to edit the batchbuffer submitted to write the correct value of 343the GPU address when a GEM BO is assigned a GPU address and the kernel 344might evict a different GEM BO from the (PP)GTT to make address room 345for another GEM BO. Consequently, the ioctls submitting a batchbuffer 346for execution also include a list of all locations within buffers that 347refer to GPU-addresses so that the kernel can edit the buffer correctly. 348This process is dubbed relocation. 349 350Locking Guidelines 351------------------ 352 353.. note:: 354 This is a description of how the locking should be after 355 refactoring is done. Does not necessarily reflect what the locking 356 looks like while WIP. 357 358#. All locking rules and interface contracts with cross-driver interfaces 359 (dma-buf, dma_fence) need to be followed. 360 361#. No struct_mutex anywhere in the code 362 363#. dma_resv will be the outermost lock (when needed) and ww_acquire_ctx 364 is to be hoisted at highest level and passed down within i915_gem_ctx 365 in the call chain 366 367#. While holding lru/memory manager (buddy, drm_mm, whatever) locks 368 system memory allocations are not allowed 369 370 * Enforce this by priming lockdep (with fs_reclaim). If we 371 allocate memory while holding these looks we get a rehash 372 of the shrinker vs. struct_mutex saga, and that would be 373 real bad. 374 375#. Do not nest different lru/memory manager locks within each other. 376 Take them in turn to update memory allocations, relying on the object’s 377 dma_resv ww_mutex to serialize against other operations. 378 379#. The suggestion for lru/memory managers locks is that they are small 380 enough to be spinlocks. 381 382#. All features need to come with exhaustive kernel selftests and/or 383 IGT tests when appropriate 384 385#. All LMEM uAPI paths need to be fully restartable (_interruptible() 386 for all locks/waits/sleeps) 387 388 * Error handling validation through signal injection. 389 Still the best strategy we have for validating GEM uAPI 390 corner cases. 391 Must be excessively used in the IGT, and we need to check 392 that we really have full path coverage of all error cases. 393 394 * -EDEADLK handling with ww_mutex 395 396GEM BO Management Implementation Details 397---------------------------------------- 398 399.. kernel-doc:: drivers/gpu/drm/i915/i915_vma_types.h 400 :doc: Virtual Memory Address 401 402Buffer Object Eviction 403---------------------- 404 405This section documents the interface functions for evicting buffer 406objects to make space available in the virtual gpu address spaces. Note 407that this is mostly orthogonal to shrinking buffer objects caches, which 408has the goal to make main memory (shared with the gpu through the 409unified memory architecture) available. 410 411.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_evict.c 412 :internal: 413 414Buffer Object Memory Shrinking 415------------------------------ 416 417This section documents the interface function for shrinking memory usage 418of buffer object caches. Shrinking is used to make main memory 419available. Note that this is mostly orthogonal to evicting buffer 420objects, which has the goal to make space in gpu virtual address spaces. 421 422.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_shrinker.c 423 :internal: 424 425Batchbuffer Parsing 426------------------- 427 428.. kernel-doc:: drivers/gpu/drm/i915/i915_cmd_parser.c 429 :doc: batch buffer command parser 430 431.. kernel-doc:: drivers/gpu/drm/i915/i915_cmd_parser.c 432 :internal: 433 434User Batchbuffer Execution 435-------------------------- 436 437.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_context_types.h 438 439.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 440 :doc: User command execution 441 442Scheduling 443---------- 444.. kernel-doc:: drivers/gpu/drm/i915/i915_scheduler_types.h 445 :functions: i915_sched_engine 446 447Logical Rings, Logical Ring Contexts and Execlists 448-------------------------------------------------- 449 450.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_execlists_submission.c 451 :doc: Logical Rings, Logical Ring Contexts and Execlists 452 453Global GTT views 454---------------- 455 456.. kernel-doc:: drivers/gpu/drm/i915/i915_vma_types.h 457 :doc: Global GTT views 458 459.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_gtt.c 460 :internal: 461 462GTT Fences and Swizzling 463------------------------ 464 465.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c 466 :internal: 467 468Global GTT Fence Handling 469~~~~~~~~~~~~~~~~~~~~~~~~~ 470 471.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c 472 :doc: fence register handling 473 474Hardware Tiling and Swizzling Details 475~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 476 477.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c 478 :doc: tiling swizzling details 479 480Object Tiling IOCTLs 481-------------------- 482 483.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_tiling.c 484 :internal: 485 486.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_tiling.c 487 :doc: buffer object tiling 488 489Protected Objects 490----------------- 491 492.. kernel-doc:: drivers/gpu/drm/i915/pxp/intel_pxp.c 493 :doc: PXP 494 495.. kernel-doc:: drivers/gpu/drm/i915/pxp/intel_pxp_types.h 496 497Microcontrollers 498================ 499 500Starting from gen9, three microcontrollers are available on the HW: the 501graphics microcontroller (GuC), the HEVC/H.265 microcontroller (HuC) and the 502display microcontroller (DMC). The driver is responsible for loading the 503firmwares on the microcontrollers; the GuC and HuC firmwares are transferred 504to WOPCM using the DMA engine, while the DMC firmware is written through MMIO. 505 506WOPCM 507----- 508 509WOPCM Layout 510~~~~~~~~~~~~ 511 512.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_wopcm.c 513 :doc: WOPCM Layout 514 515GuC 516--- 517 518.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c 519 :doc: GuC 520 521.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.h 522 523GuC Firmware Layout 524~~~~~~~~~~~~~~~~~~~ 525 526.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h 527 :doc: Firmware Layout 528 529GuC Memory Management 530~~~~~~~~~~~~~~~~~~~~~ 531 532.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c 533 :doc: GuC Memory Management 534.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c 535 :functions: intel_guc_allocate_vma 536 537 538GuC-specific firmware loader 539~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 540 541.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c 542 :internal: 543 544GuC-based command submission 545~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 546 547.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 548 :doc: GuC-based command submission 549 550GuC ABI 551~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 552 553.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h 554.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h 555.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h 556.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h 557.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h 558 559HuC 560--- 561.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c 562 :doc: HuC 563.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c 564 :functions: intel_huc_auth 565 566HuC Memory Management 567~~~~~~~~~~~~~~~~~~~~~ 568 569.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c 570 :doc: HuC Memory Management 571 572HuC Firmware Layout 573~~~~~~~~~~~~~~~~~~~ 574The HuC FW layout is the same as the GuC one, see `GuC Firmware Layout`_ 575 576DMC 577--- 578See `DMC Firmware Support`_ 579 580Tracing 581======= 582 583This sections covers all things related to the tracepoints implemented 584in the i915 driver. 585 586i915_ppgtt_create and i915_ppgtt_release 587---------------------------------------- 588 589.. kernel-doc:: drivers/gpu/drm/i915/i915_trace.h 590 :doc: i915_ppgtt_create and i915_ppgtt_release tracepoints 591 592i915_context_create and i915_context_free 593----------------------------------------- 594 595.. kernel-doc:: drivers/gpu/drm/i915/i915_trace.h 596 :doc: i915_context_create and i915_context_free tracepoints 597 598Perf 599==== 600 601Overview 602-------- 603.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 604 :doc: i915 Perf Overview 605 606Comparison with Core Perf 607------------------------- 608.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 609 :doc: i915 Perf History and Comparison with Core Perf 610 611i915 Driver Entry Points 612------------------------ 613 614This section covers the entrypoints exported outside of i915_perf.c to 615integrate with drm/i915 and to handle the `DRM_I915_PERF_OPEN` ioctl. 616 617.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 618 :functions: i915_perf_init 619.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 620 :functions: i915_perf_fini 621.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 622 :functions: i915_perf_register 623.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 624 :functions: i915_perf_unregister 625.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 626 :functions: i915_perf_open_ioctl 627.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 628 :functions: i915_perf_release 629.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 630 :functions: i915_perf_add_config_ioctl 631.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 632 :functions: i915_perf_remove_config_ioctl 633 634i915 Perf Stream 635---------------- 636 637This section covers the stream-semantics-agnostic structures and functions 638for representing an i915 perf stream FD and associated file operations. 639 640.. kernel-doc:: drivers/gpu/drm/i915/i915_perf_types.h 641 :functions: i915_perf_stream 642.. kernel-doc:: drivers/gpu/drm/i915/i915_perf_types.h 643 :functions: i915_perf_stream_ops 644 645.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 646 :functions: read_properties_unlocked 647.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 648 :functions: i915_perf_open_ioctl_locked 649.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 650 :functions: i915_perf_destroy_locked 651.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 652 :functions: i915_perf_read 653.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 654 :functions: i915_perf_ioctl 655.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 656 :functions: i915_perf_enable_locked 657.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 658 :functions: i915_perf_disable_locked 659.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 660 :functions: i915_perf_poll 661.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 662 :functions: i915_perf_poll_locked 663 664i915 Perf Observation Architecture Stream 665----------------------------------------- 666 667.. kernel-doc:: drivers/gpu/drm/i915/i915_perf_types.h 668 :functions: i915_oa_ops 669 670.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 671 :functions: i915_oa_stream_init 672.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 673 :functions: i915_oa_read 674.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 675 :functions: i915_oa_stream_enable 676.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 677 :functions: i915_oa_stream_disable 678.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 679 :functions: i915_oa_wait_unlocked 680.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 681 :functions: i915_oa_poll_wait 682 683Other i915 Perf Internals 684------------------------- 685 686This section simply includes all other currently documented i915 perf internals, 687in no particular order, but may include some more minor utilities or platform 688specific details than found in the more high-level sections. 689 690.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 691 :internal: 692 :no-identifiers: 693 i915_perf_init 694 i915_perf_fini 695 i915_perf_register 696 i915_perf_unregister 697 i915_perf_open_ioctl 698 i915_perf_release 699 i915_perf_add_config_ioctl 700 i915_perf_remove_config_ioctl 701 read_properties_unlocked 702 i915_perf_open_ioctl_locked 703 i915_perf_destroy_locked 704 i915_perf_read i915_perf_ioctl 705 i915_perf_enable_locked 706 i915_perf_disable_locked 707 i915_perf_poll i915_perf_poll_locked 708 i915_oa_stream_init i915_oa_read 709 i915_oa_stream_enable 710 i915_oa_stream_disable 711 i915_oa_wait_unlocked 712 i915_oa_poll_wait 713 714Style 715===== 716 717The drm/i915 driver codebase has some style rules in addition to (and, in some 718cases, deviating from) the kernel coding style. 719 720Register macro definition style 721------------------------------- 722 723The style guide for ``i915_reg.h``. 724 725.. kernel-doc:: drivers/gpu/drm/i915/i915_reg.h 726 :doc: The i915 register macro definition style guide 727 728.. _i915-usage-stats: 729 730i915 DRM client usage stats implementation 731========================================== 732 733The drm/i915 driver implements the DRM client usage stats specification as 734documented in :ref:`drm-client-usage-stats`. 735 736Example of the output showing the implemented key value pairs and entirety of 737the currently possible format options: 738 739:: 740 741 pos: 0 742 flags: 0100002 743 mnt_id: 21 744 drm-driver: i915 745 drm-pdev: 0000:00:02.0 746 drm-client-id: 7 747 drm-engine-render: 9288864723 ns 748 drm-engine-copy: 2035071108 ns 749 drm-engine-video: 0 ns 750 drm-engine-capacity-video: 2 751 drm-engine-video-enhance: 0 ns 752 753Possible `drm-engine-` key names are: `render`, `copy`, `video` and 754`video-enhance`. 755