| /qemu/tcg/s390x/ |
| H A D | tcg-target.h | ed5234735af0c9ddc120ba2297e47714c5126abd Thu Dec 16 19:17:46 UTC 2021 Richard Henderson <richard.henderson@linaro.org> tcg: Add opcodes for vector nand, nor, eqv
We've had placeholders for these opcodes for a while,
and should have support on ppc, s390x and avx512 hosts.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|
| /qemu/tcg/ |
| H A D | tcg-op-vec.c | ed5234735af0c9ddc120ba2297e47714c5126abd Thu Dec 16 19:17:46 UTC 2021 Richard Henderson <richard.henderson@linaro.org> tcg: Add opcodes for vector nand, nor, eqv
We've had placeholders for these opcodes for a while,
and should have support on ppc, s390x and avx512 hosts.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|
| H A D | optimize.c | ed5234735af0c9ddc120ba2297e47714c5126abd Thu Dec 16 19:17:46 UTC 2021 Richard Henderson <richard.henderson@linaro.org> tcg: Add opcodes for vector nand, nor, eqv
We've had placeholders for these opcodes for a while,
and should have support on ppc, s390x and avx512 hosts.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|
| H A D | tcg.c | ed5234735af0c9ddc120ba2297e47714c5126abd Thu Dec 16 19:17:46 UTC 2021 Richard Henderson <richard.henderson@linaro.org> tcg: Add opcodes for vector nand, nor, eqv
We've had placeholders for these opcodes for a while,
and should have support on ppc, s390x and avx512 hosts.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|
| /qemu/include/tcg/ |
| H A D | tcg-opc.h | ed5234735af0c9ddc120ba2297e47714c5126abd Thu Dec 16 19:17:46 UTC 2021 Richard Henderson <richard.henderson@linaro.org> tcg: Add opcodes for vector nand, nor, eqv
We've had placeholders for these opcodes for a while,
and should have support on ppc, s390x and avx512 hosts.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|
| H A D | tcg.h | ed5234735af0c9ddc120ba2297e47714c5126abd Thu Dec 16 19:17:46 UTC 2021 Richard Henderson <richard.henderson@linaro.org> tcg: Add opcodes for vector nand, nor, eqv
We've had placeholders for these opcodes for a while,
and should have support on ppc, s390x and avx512 hosts.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|
| /qemu/tcg/ppc/ |
| H A D | tcg-target.h | ed5234735af0c9ddc120ba2297e47714c5126abd Thu Dec 16 19:17:46 UTC 2021 Richard Henderson <richard.henderson@linaro.org> tcg: Add opcodes for vector nand, nor, eqv
We've had placeholders for these opcodes for a while,
and should have support on ppc, s390x and avx512 hosts.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|
| /qemu/tcg/arm/ |
| H A D | tcg-target.h | ed5234735af0c9ddc120ba2297e47714c5126abd Thu Dec 16 19:17:46 UTC 2021 Richard Henderson <richard.henderson@linaro.org> tcg: Add opcodes for vector nand, nor, eqv
We've had placeholders for these opcodes for a while,
and should have support on ppc, s390x and avx512 hosts.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|
| /qemu/tcg/aarch64/ |
| H A D | tcg-target.h | ed5234735af0c9ddc120ba2297e47714c5126abd Thu Dec 16 19:17:46 UTC 2021 Richard Henderson <richard.henderson@linaro.org> tcg: Add opcodes for vector nand, nor, eqv
We've had placeholders for these opcodes for a while,
and should have support on ppc, s390x and avx512 hosts.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|
| /qemu/tcg/i386/ |
| H A D | tcg-target.h | ed5234735af0c9ddc120ba2297e47714c5126abd Thu Dec 16 19:17:46 UTC 2021 Richard Henderson <richard.henderson@linaro.org> tcg: Add opcodes for vector nand, nor, eqv
We've had placeholders for these opcodes for a while,
and should have support on ppc, s390x and avx512 hosts.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|