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| H A D | riscv_aclint.c | d42df0ea5dd58cfda5e1466487f93b5b90a67594 Wed Apr 20 08:08:58 UTC 2022 Frank Chang <frank.chang@sifive.com> hw/intc: Support 32/64-bit mtimecmp and mtime accesses in RISC-V ACLINT
RISC-V privilege spec defines that:
* In RV32, memory-mapped writes to mtimecmp modify only one 32-bit part
of the register.
* For RV64, naturally aligned 64-bit memory accesses to the mtime and
mtimecmp registers are additionally supported and are atomic.
It's possible to perform both 32/64-bit read/write accesses to both
mtimecmp and mtime registers.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Message-Id: <20220420080901.14655-3-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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