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| H A D | svm.h | d30973c39a3fd2f8f8a1e694fb9b6d055166fcc1 Thu Sep 16 18:45:51 UTC 2021 Wei Huang <wei.huang2@amd.com> svm: Fix MBZ reserved bits of AMD CR4 register
According to AMD APM, Volume 2: System Programming (Rev. 3.37, March 2021),
CR4 register is defined to have the following MBZ reserved bits:
* Bit 12 - 15
* Bit 19
* Bit 24 - 63
Additionally Bit 12 will be used by LA57 in future CPUs. Fix the CR4
reserved bit definition to match with APM and prevent potential test_cr4()
failures.
Reported-by: Babu Moger <Babu.Moger@amd.com>
Signed-off-by: Wei Huang <wei.huang2@amd.com>
Tested-by: Babu Moger <Babu.Moger@amd.com>
Message-Id: <20210916184551.119561-1-wei.huang2@amd.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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| H A D | svm_tests.c | d30973c39a3fd2f8f8a1e694fb9b6d055166fcc1 Thu Sep 16 18:45:51 UTC 2021 Wei Huang <wei.huang2@amd.com> svm: Fix MBZ reserved bits of AMD CR4 register
According to AMD APM, Volume 2: System Programming (Rev. 3.37, March 2021),
CR4 register is defined to have the following MBZ reserved bits:
* Bit 12 - 15
* Bit 19
* Bit 24 - 63
Additionally Bit 12 will be used by LA57 in future CPUs. Fix the CR4
reserved bit definition to match with APM and prevent potential test_cr4()
failures.
Reported-by: Babu Moger <Babu.Moger@amd.com>
Signed-off-by: Wei Huang <wei.huang2@amd.com>
Tested-by: Babu Moger <Babu.Moger@amd.com>
Message-Id: <20210916184551.119561-1-wei.huang2@amd.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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