Searched hist:be46e0bf142d75c1978801d5d2c2394e7dfa304d (Results 1 – 2 of 2) sorted by relevance
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| H A D | riscv.h | be46e0bf142d75c1978801d5d2c2394e7dfa304d Wed Oct 16 16:57:15 UTC 2024 Richard Henderson <richard.henderson@linaro.org> disas/riscv: Fix vsetivli disassembly
The first immediate field is unsigned, whereas operand_vimm
extracts a signed value. There is no need to mask the result
with 'u'; just print the immediate with 'i'.
Fixes: 07f4964d178 ("disas/riscv.c: rvv: Add disas support for vector instructions")
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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| H A D | riscv.c | be46e0bf142d75c1978801d5d2c2394e7dfa304d Wed Oct 16 16:57:15 UTC 2024 Richard Henderson <richard.henderson@linaro.org> disas/riscv: Fix vsetivli disassembly
The first immediate field is unsigned, whereas operand_vimm
extracts a signed value. There is no need to mask the result
with 'u'; just print the immediate with 'i'.
Fixes: 07f4964d178 ("disas/riscv.c: rvv: Add disas support for vector instructions")
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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