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/qemu/include/hw/ppc/
H A Dspapr_xive.hb2e22477166a7f8a32b95317dea747f8af7a807f Tue Dec 11 22:38:17 UTC 2018 Cédric Le Goater <clg@kaod.org> spapr: add a 'reset' method to the sPAPR IRQ backend

For the time being, the XIVE reset handler updates the OS CAM line of
the vCPU as it is done under a real hypervisor when a vCPU is
scheduled to run on a HW thread. This will let the XIVE presenter
engine find a match among the NVTs dispatched on the HW threads.

This handler will become even more useful when we introduce the
machine supporting both interrupt modes, XIVE and XICS. In this
machine, the interrupt mode is chosen by the CAS negotiation process
and activated after a reset.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
[dwg: Fix style nits]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
H A Dspapr_irq.hb2e22477166a7f8a32b95317dea747f8af7a807f Tue Dec 11 22:38:17 UTC 2018 Cédric Le Goater <clg@kaod.org> spapr: add a 'reset' method to the sPAPR IRQ backend

For the time being, the XIVE reset handler updates the OS CAM line of
the vCPU as it is done under a real hypervisor when a vCPU is
scheduled to run on a HW thread. This will let the XIVE presenter
engine find a match among the NVTs dispatched on the HW threads.

This handler will become even more useful when we introduce the
machine supporting both interrupt modes, XIVE and XICS. In this
machine, the interrupt mode is chosen by the CAS negotiation process
and activated after a reset.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
[dwg: Fix style nits]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
/qemu/hw/ppc/
H A Dspapr_irq.cb2e22477166a7f8a32b95317dea747f8af7a807f Tue Dec 11 22:38:17 UTC 2018 Cédric Le Goater <clg@kaod.org> spapr: add a 'reset' method to the sPAPR IRQ backend

For the time being, the XIVE reset handler updates the OS CAM line of
the vCPU as it is done under a real hypervisor when a vCPU is
scheduled to run on a HW thread. This will let the XIVE presenter
engine find a match among the NVTs dispatched on the HW threads.

This handler will become even more useful when we introduce the
machine supporting both interrupt modes, XIVE and XICS. In this
machine, the interrupt mode is chosen by the CAS negotiation process
and activated after a reset.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
[dwg: Fix style nits]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
H A Dspapr.cb2e22477166a7f8a32b95317dea747f8af7a807f Tue Dec 11 22:38:17 UTC 2018 Cédric Le Goater <clg@kaod.org> spapr: add a 'reset' method to the sPAPR IRQ backend

For the time being, the XIVE reset handler updates the OS CAM line of
the vCPU as it is done under a real hypervisor when a vCPU is
scheduled to run on a HW thread. This will let the XIVE presenter
engine find a match among the NVTs dispatched on the HW threads.

This handler will become even more useful when we introduce the
machine supporting both interrupt modes, XIVE and XICS. In this
machine, the interrupt mode is chosen by the CAS negotiation process
and activated after a reset.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
[dwg: Fix style nits]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
/qemu/hw/intc/
H A Dspapr_xive.cb2e22477166a7f8a32b95317dea747f8af7a807f Tue Dec 11 22:38:17 UTC 2018 Cédric Le Goater <clg@kaod.org> spapr: add a 'reset' method to the sPAPR IRQ backend

For the time being, the XIVE reset handler updates the OS CAM line of
the vCPU as it is done under a real hypervisor when a vCPU is
scheduled to run on a HW thread. This will let the XIVE presenter
engine find a match among the NVTs dispatched on the HW threads.

This handler will become even more useful when we introduce the
machine supporting both interrupt modes, XIVE and XICS. In this
machine, the interrupt mode is chosen by the CAS negotiation process
and activated after a reset.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
[dwg: Fix style nits]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>