Searched hist:"9 a31b8d0ad86e12920e01bd4c01516be9f75337e" (Results 1 – 2 of 2) sorted by relevance
| /qemu/fpu/ |
| H A D | softfloat-specialize.c.inc | 9a31b8d0ad86e12920e01bd4c01516be9f75337e Wed Dec 11 15:30:55 UTC 2024 Peter Maydell <peter.maydell@linaro.org> target/sparc: Set FloatInfZeroNaNRule explicitly
Set the FloatInfZeroNaNRule explicitly for the SPARC target,
so we can remove the ifdef from pickNaNMulAdd().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241202131347.498124-10-peter.maydell@linaro.org
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| /qemu/target/sparc/ |
| H A D | cpu.c | 9a31b8d0ad86e12920e01bd4c01516be9f75337e Wed Dec 11 15:30:55 UTC 2024 Peter Maydell <peter.maydell@linaro.org> target/sparc: Set FloatInfZeroNaNRule explicitly
Set the FloatInfZeroNaNRule explicitly for the SPARC target,
so we can remove the ifdef from pickNaNMulAdd().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241202131347.498124-10-peter.maydell@linaro.org
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