Searched hist:"76 d855f0580148d8f07f1c0aa96f33cad382e6cc" (Results 1 – 2 of 2) sorted by relevance
| /linux/arch/arm64/boot/dts/ti/ |
| H A D | k3-am62p-j722s-common-wakeup.dtsi | 76d855f0580148d8f07f1c0aa96f33cad382e6cc Tue Oct 08 13:20:52 UTC 2024 Bryan Brattlof <bb@ti.com> arm64: dts: ti: k3-am62p: add opp frequencies
One power management technique available to the Cortex-A53s is their
ability to dynamically scale their frequency across the device's
Operating Performance Points (OPP)
The OPPs available for the Cortex-A53s on the AM62Px can vary based on
the silicon variant used. The SoC variant is encoded into the
WKUP_MMR0_WKUP0_CTRL_MMR0_JTAG_USER_ID register which is used to limit
the OPP entries the SoC supports. A table of all these variants can be
found in its data sheet[0] for the AM62Px processor family.
Add the OPP table into the SoC's fdti file along with the syscon node to
describe the WKUP_MMR0_WKUP0_CTRL_MMR0_JTAG_USER_ID register to detect
the SoC variant.
[0] https://www.ti.com/lit/ds/symlink/am62p-q1.pdf
Signed-off-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
Link: https://lore.kernel.org/r/20241008132052.407994-4-d-gole@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
| H A D | k3-am62p5.dtsi | 76d855f0580148d8f07f1c0aa96f33cad382e6cc Tue Oct 08 13:20:52 UTC 2024 Bryan Brattlof <bb@ti.com> arm64: dts: ti: k3-am62p: add opp frequencies
One power management technique available to the Cortex-A53s is their
ability to dynamically scale their frequency across the device's
Operating Performance Points (OPP)
The OPPs available for the Cortex-A53s on the AM62Px can vary based on
the silicon variant used. The SoC variant is encoded into the
WKUP_MMR0_WKUP0_CTRL_MMR0_JTAG_USER_ID register which is used to limit
the OPP entries the SoC supports. A table of all these variants can be
found in its data sheet[0] for the AM62Px processor family.
Add the OPP table into the SoC's fdti file along with the syscon node to
describe the WKUP_MMR0_WKUP0_CTRL_MMR0_JTAG_USER_ID register to detect
the SoC variant.
[0] https://www.ti.com/lit/ds/symlink/am62p-q1.pdf
Signed-off-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
Link: https://lore.kernel.org/r/20241008132052.407994-4-d-gole@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|