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| H A D | riscv_aclint.c | 70b78d4e71494c90d2ccb40381336bc9b9a22f79 Tue Jun 30 20:12:11 UTC 2020 Alistair Francis <alistair.francis@wdc.com> hw/riscv: Allow 64 bit access to SiFive CLINT
Commit 5d971f9e672507210e77d020d89e0e89165c8fc9
"memory: Revert "memory: accept mismatching sizes in
memory_region_access_valid"" broke most RISC-V boards as they do 64 bit
accesses to the CLINT and QEMU would trigger a fault. Fix this failure
by allowing 8 byte accesses.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
Message-Id: <122b78825b077e4dfd39b444d3a46fe894a7804c.1593547870.git.alistair.francis@wdc.com>
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