Searched hist:"6 b56bb6dbce5cfa185c34c0519ab8015f30699f7" (Results 1 – 4 of 4) sorted by relevance
| /qemu/include/hw/pci-host/ |
| H A D | pnv_phb4.h | 6b56bb6dbce5cfa185c34c0519ab8015f30699f7 Sat Nov 16 10:19:19 UTC 2024 Nicholas Piggin <npiggin@gmail.com> ppc/pnv/phb4: Add pervasive chiplet support to PHB4/5
Each non-core chiplet on a chip has a "pervasive chiplet" unit and its
xscom register set. This adds support for PHB4/5.
skiboot reads the CPLT_CONF1 register in __phb4/5_get_max_link_width(),
which shows up as unimplemented xscom reads. Set a value in PCI CONF1
register's link-width field to demonstrate skiboot doing something
interesting with it.
In the bigger picture, it might be better to model the pervasive
chiplet type as parent that each non-core chiplet model derives from.
For now this is enough to get the PHB registers implemented and working
for skiboot, and provides a second example (after the N1 chiplet) that
will help if the design is reworked as such.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
|
| /qemu/hw/pci-host/ |
| H A D | pnv_phb4_pec.c | 6b56bb6dbce5cfa185c34c0519ab8015f30699f7 Sat Nov 16 10:19:19 UTC 2024 Nicholas Piggin <npiggin@gmail.com> ppc/pnv/phb4: Add pervasive chiplet support to PHB4/5
Each non-core chiplet on a chip has a "pervasive chiplet" unit and its
xscom register set. This adds support for PHB4/5.
skiboot reads the CPLT_CONF1 register in __phb4/5_get_max_link_width(),
which shows up as unimplemented xscom reads. Set a value in PCI CONF1
register's link-width field to demonstrate skiboot doing something
interesting with it.
In the bigger picture, it might be better to model the pervasive
chiplet type as parent that each non-core chiplet model derives from.
For now this is enough to get the PHB registers implemented and working
for skiboot, and provides a second example (after the N1 chiplet) that
will help if the design is reworked as such.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
|
| /qemu/include/hw/ppc/ |
| H A D | pnv_xscom.h | 6b56bb6dbce5cfa185c34c0519ab8015f30699f7 Sat Nov 16 10:19:19 UTC 2024 Nicholas Piggin <npiggin@gmail.com> ppc/pnv/phb4: Add pervasive chiplet support to PHB4/5
Each non-core chiplet on a chip has a "pervasive chiplet" unit and its
xscom register set. This adds support for PHB4/5.
skiboot reads the CPLT_CONF1 register in __phb4/5_get_max_link_width(),
which shows up as unimplemented xscom reads. Set a value in PCI CONF1
register's link-width field to demonstrate skiboot doing something
interesting with it.
In the bigger picture, it might be better to model the pervasive
chiplet type as parent that each non-core chiplet model derives from.
For now this is enough to get the PHB registers implemented and working
for skiboot, and provides a second example (after the N1 chiplet) that
will help if the design is reworked as such.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
|
| /qemu/hw/ppc/ |
| H A D | pnv.c | 6b56bb6dbce5cfa185c34c0519ab8015f30699f7 Sat Nov 16 10:19:19 UTC 2024 Nicholas Piggin <npiggin@gmail.com> ppc/pnv/phb4: Add pervasive chiplet support to PHB4/5
Each non-core chiplet on a chip has a "pervasive chiplet" unit and its
xscom register set. This adds support for PHB4/5.
skiboot reads the CPLT_CONF1 register in __phb4/5_get_max_link_width(),
which shows up as unimplemented xscom reads. Set a value in PCI CONF1
register's link-width field to demonstrate skiboot doing something
interesting with it.
In the bigger picture, it might be better to model the pervasive
chiplet type as parent that each non-core chiplet model derives from.
For now this is enough to get the PHB registers implemented and working
for skiboot, and provides a second example (after the N1 chiplet) that
will help if the design is reworked as such.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
|