Searched hist:"57 a3a6226529e60ef4eb5e11b577f2e532a72acc" (Results 1 – 3 of 3) sorted by relevance
| /qemu/include/hw/timer/ |
| H A D | ibex_timer.h | 57a3a6226529e60ef4eb5e11b577f2e532a72acc Mon Aug 30 05:35:15 UTC 2021 Alistair Francis <alistair.francis@wdc.com> hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines
Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V
CPU GPIO lines to set the timer MIP bits.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 84d5b1d5783d2e79eee69a2f7ac480cc0c070db3.1630301632.git.alistair.francis@wdc.com
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| /qemu/hw/timer/ |
| H A D | ibex_timer.c | 57a3a6226529e60ef4eb5e11b577f2e532a72acc Mon Aug 30 05:35:15 UTC 2021 Alistair Francis <alistair.francis@wdc.com> hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines
Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V
CPU GPIO lines to set the timer MIP bits.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 84d5b1d5783d2e79eee69a2f7ac480cc0c070db3.1630301632.git.alistair.francis@wdc.com
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| /qemu/hw/riscv/ |
| H A D | opentitan.c | 57a3a6226529e60ef4eb5e11b577f2e532a72acc Mon Aug 30 05:35:15 UTC 2021 Alistair Francis <alistair.francis@wdc.com> hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines
Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V
CPU GPIO lines to set the timer MIP bits.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 84d5b1d5783d2e79eee69a2f7ac480cc0c070db3.1630301632.git.alistair.francis@wdc.com
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