Searched hist:"454 c2201005b5f47a76116ab529c923e194ec615" (Results 1 – 2 of 2) sorted by relevance
| /qemu/disas/ |
| H A D | riscv.c | 454c2201005b5f47a76116ab529c923e194ec615 Tue May 23 09:35:34 UTC 2023 Weiwei Li <liweiwei@iscas.ac.cn> target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info
Pass RISCVCPUConfig as disassemble_info.target_info to support disas
of conflict instructions related to specific extensions.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230523093539.203909-4-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
|
| /qemu/target/riscv/ |
| H A D | cpu.c | 454c2201005b5f47a76116ab529c923e194ec615 Tue May 23 09:35:34 UTC 2023 Weiwei Li <liweiwei@iscas.ac.cn> target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info
Pass RISCVCPUConfig as disassemble_info.target_info to support disas
of conflict instructions related to specific extensions.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230523093539.203909-4-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
|