Searched hist:"434 c609bef445e0dd13d514c5b12f8e47a73cd1d" (Results 1 – 2 of 2) sorted by relevance
| /qemu/disas/ |
| H A D | riscv.h | 434c609bef445e0dd13d514c5b12f8e47a73cd1d Thu Oct 26 15:18:19 UTC 2023 Max Chou <max.chou@sifive.com> disas/riscv: Add rv_codec_vror_vi for vror.vi
Add rv_codec_vror_vi for the vector crypto instruction - vror.vi.
The rotate amount of vror.vi is defined by combining seperated bits.
Signed-off-by: Max Chou <max.chou@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231026151828.754279-13-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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| H A D | riscv.c | 434c609bef445e0dd13d514c5b12f8e47a73cd1d Thu Oct 26 15:18:19 UTC 2023 Max Chou <max.chou@sifive.com> disas/riscv: Add rv_codec_vror_vi for vror.vi
Add rv_codec_vror_vi for the vector crypto instruction - vror.vi.
The rotate amount of vror.vi is defined by combining seperated bits.
Signed-off-by: Max Chou <max.chou@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231026151828.754279-13-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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