Searched hist:"28 ca4689ae94a27a6a337546425cda30d0e885c3" (Results 1 – 2 of 2) sorted by relevance
| /qemu/include/hw/timer/ |
| H A D | ibex_timer.h | 28ca4689ae94a27a6a337546425cda30d0e885c3 Mon Jan 10 05:16:06 UTC 2022 Wilfred Mallawa <wilfred.mallawa@wdc.com> hw: timer: ibex_timer: Fixup reading w/o register
This change fixes a bug where a write only register is read.
As per https://docs.opentitan.org/hw/ip/rv_timer/doc/#register-table
the 'INTR_TEST0' register is write only.
Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20220110051606.4031241-1-alistair.francis@opensource.wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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| /qemu/hw/timer/ |
| H A D | ibex_timer.c | 28ca4689ae94a27a6a337546425cda30d0e885c3 Mon Jan 10 05:16:06 UTC 2022 Wilfred Mallawa <wilfred.mallawa@wdc.com> hw: timer: ibex_timer: Fixup reading w/o register
This change fixes a bug where a write only register is read.
As per https://docs.opentitan.org/hw/ip/rv_timer/doc/#register-table
the 'INTR_TEST0' register is write only.
Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20220110051606.4031241-1-alistair.francis@opensource.wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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