| /qemu/include/qemu/ |
| H A D | cacheflush.h | 1da8de39a39c55560cb4bf0cea94d598fea035cd Sat Dec 12 16:38:21 UTC 2020 Richard Henderson <richard.henderson@linaro.org> util: Enhance flush_icache_range with separate data pointer
We are shortly going to have a split rw/rx jit buffer. Depending
on the host, we need to flush the dcache at the rw data pointer and
flush the icache at the rx code pointer.
For now, the two passed pointers are identical, so there is no
effective change in behaviour.
Reviewed-by: Joelle van Dyne <j@getutm.app>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|
| /qemu/util/ |
| H A D | cacheflush.c | 1da8de39a39c55560cb4bf0cea94d598fea035cd Sat Dec 12 16:38:21 UTC 2020 Richard Henderson <richard.henderson@linaro.org> util: Enhance flush_icache_range with separate data pointer
We are shortly going to have a split rw/rx jit buffer. Depending
on the host, we need to flush the dcache at the rw data pointer and
flush the icache at the rx code pointer.
For now, the two passed pointers are identical, so there is no
effective change in behaviour.
Reviewed-by: Joelle van Dyne <j@getutm.app>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|
| /qemu/tcg/sparc64/ |
| H A D | tcg-target.c.inc | 1da8de39a39c55560cb4bf0cea94d598fea035cd Sat Dec 12 16:38:21 UTC 2020 Richard Henderson <richard.henderson@linaro.org> util: Enhance flush_icache_range with separate data pointer
We are shortly going to have a split rw/rx jit buffer. Depending
on the host, we need to flush the dcache at the rw data pointer and
flush the icache at the rx code pointer.
For now, the two passed pointers are identical, so there is no
effective change in behaviour.
Reviewed-by: Joelle van Dyne <j@getutm.app>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|
| /qemu/tcg/mips/ |
| H A D | tcg-target.c.inc | 1da8de39a39c55560cb4bf0cea94d598fea035cd Sat Dec 12 16:38:21 UTC 2020 Richard Henderson <richard.henderson@linaro.org> util: Enhance flush_icache_range with separate data pointer
We are shortly going to have a split rw/rx jit buffer. Depending
on the host, we need to flush the dcache at the rw data pointer and
flush the icache at the rx code pointer.
For now, the two passed pointers are identical, so there is no
effective change in behaviour.
Reviewed-by: Joelle van Dyne <j@getutm.app>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|
| /qemu/tcg/aarch64/ |
| H A D | tcg-target.c.inc | 1da8de39a39c55560cb4bf0cea94d598fea035cd Sat Dec 12 16:38:21 UTC 2020 Richard Henderson <richard.henderson@linaro.org> util: Enhance flush_icache_range with separate data pointer
We are shortly going to have a split rw/rx jit buffer. Depending
on the host, we need to flush the dcache at the rw data pointer and
flush the icache at the rx code pointer.
For now, the two passed pointers are identical, so there is no
effective change in behaviour.
Reviewed-by: Joelle van Dyne <j@getutm.app>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|
| /qemu/tcg/ppc/ |
| H A D | tcg-target.c.inc | 1da8de39a39c55560cb4bf0cea94d598fea035cd Sat Dec 12 16:38:21 UTC 2020 Richard Henderson <richard.henderson@linaro.org> util: Enhance flush_icache_range with separate data pointer
We are shortly going to have a split rw/rx jit buffer. Depending
on the host, we need to flush the dcache at the rw data pointer and
flush the icache at the rx code pointer.
For now, the two passed pointers are identical, so there is no
effective change in behaviour.
Reviewed-by: Joelle van Dyne <j@getutm.app>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|
| /qemu/system/ |
| H A D | physmem.c | 1da8de39a39c55560cb4bf0cea94d598fea035cd Sat Dec 12 16:38:21 UTC 2020 Richard Henderson <richard.henderson@linaro.org> util: Enhance flush_icache_range with separate data pointer
We are shortly going to have a split rw/rx jit buffer. Depending
on the host, we need to flush the dcache at the rw data pointer and
flush the icache at the rx code pointer.
For now, the two passed pointers are identical, so there is no
effective change in behaviour.
Reviewed-by: Joelle van Dyne <j@getutm.app>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|
| /qemu/tcg/ |
| H A D | tcg.c | 1da8de39a39c55560cb4bf0cea94d598fea035cd Sat Dec 12 16:38:21 UTC 2020 Richard Henderson <richard.henderson@linaro.org> util: Enhance flush_icache_range with separate data pointer
We are shortly going to have a split rw/rx jit buffer. Depending
on the host, we need to flush the dcache at the rw data pointer and
flush the icache at the rx code pointer.
For now, the two passed pointers are identical, so there is no
effective change in behaviour.
Reviewed-by: Joelle van Dyne <j@getutm.app>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|