Searched hist:"1 c77c410b684e987b8c3cd2e02e0460c7e008778" (Results 1 – 2 of 2) sorted by relevance
| /qemu/include/hw/intc/ |
| H A D | riscv_aclint.h | 1c77c410b684e987b8c3cd2e02e0460c7e008778 Fri Mar 02 12:31:12 UTC 2018 Michael Clark <mjc@sifive.com> SiFive RISC-V CLINT Block
The CLINT (Core Local Interruptor) device provides real-time clock, timer
and interprocessor interrupts based on SiFive's CLINT specification.
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu>
Signed-off-by: Stefan O'Rear <sorear2@gmail.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
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| /qemu/hw/intc/ |
| H A D | riscv_aclint.c | 1c77c410b684e987b8c3cd2e02e0460c7e008778 Fri Mar 02 12:31:12 UTC 2018 Michael Clark <mjc@sifive.com> SiFive RISC-V CLINT Block
The CLINT (Core Local Interruptor) device provides real-time clock, timer
and interprocessor interrupts based on SiFive's CLINT specification.
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu>
Signed-off-by: Stefan O'Rear <sorear2@gmail.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
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