Searched hist:"01 b1361f84d55a86be486323836a29488b52e3a6" (Results 1 – 2 of 2) sorted by relevance
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| H A D | riscv.h | 01b1361f84d55a86be486323836a29488b52e3a6 Mon Jun 12 11:10:30 UTC 2023 Christoph Müllner <christoph.muellner@vrull.eu> disas/riscv: Make rv_op_illegal a shared enum value
The enum value 'rv_op_illegal' does not represent an
instruction, but is a catch-all value in case we have
no match in the decoder. Let's make the value a shared
one, so that other compile units can reuse it.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230612111034.3955227-5-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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| H A D | riscv.c | 01b1361f84d55a86be486323836a29488b52e3a6 Mon Jun 12 11:10:30 UTC 2023 Christoph Müllner <christoph.muellner@vrull.eu> disas/riscv: Make rv_op_illegal a shared enum value
The enum value 'rv_op_illegal' does not represent an
instruction, but is a catch-all value in case we have
no match in the decoder. Let's make the value a shared
one, so that other compile units can reuse it.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230612111034.3955227-5-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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