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Searched +full:zynqmp +full:- +full:pcap +full:- +full:fpga (Results 1 – 7 of 7) sorted by relevance

/linux-6.15/Documentation/devicetree/bindings/fpga/
Dxlnx,zynqmp-pcap-fpga.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xlnx,zynqmp-pcap-fpga.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Zynq Ultrascale MPSoC FPGA Manager
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
13 Device Tree Bindings for Zynq Ultrascale MPSoC FPGA Manager.
14 The ZynqMP SoC uses the PCAP (Processor Configuration Port) to
20 const: xlnx,zynqmp-pcap-fpga
23 - compatible
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/linux-6.15/Documentation/devicetree/bindings/firmware/xilinx/
Dxlnx,zynqmp-firmware.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
12 description: The zynqmp-firmware node describes the interface to platform
13 firmware. ZynqMP has an interface to communicate with secure firmware.
17 power management service, FPGA service and other platform management
23 - description: For implementations complying for Zynq Ultrascale+ MPSoC.
24 const: xlnx,zynqmp-firmware
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/linux-6.15/drivers/fpga/
Dzynqmp-fpga.c1 // SPDX-License-Identifier: GPL-2.0+
6 #include <linux/dma-mapping.h>
7 #include <linux/fpga/fpga-mgr.h>
13 #include <linux/firmware/xlnx-zynqmp.h>
19 * struct zynqmp_fpga_priv - Private data structure
34 priv = mgr->priv; in zynqmp_fpga_ops_write_init()
35 priv->flags = info->flags; in zynqmp_fpga_ops_write_init()
49 priv = mgr->priv; in zynqmp_fpga_ops_write()
51 kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr, GFP_KERNEL); in zynqmp_fpga_ops_write()
53 return -ENOMEM; in zynqmp_fpga_ops_write()
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # FPGA framework configuration
6 menuconfig FPGA config
7 tristate "FPGA Configuration Framework"
10 kernel. The FPGA framework adds an FPGA manager class and FPGA
13 if FPGA
16 tristate "Altera SOCFPGA FPGA Manager"
19 FPGA manager driver support for Altera SOCFPGA.
26 FPGA manager driver support for Altera Arria10 SoCFPGA.
41 tristate "Altera FPGA Passive Serial over SPI"
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/linux-6.15/Documentation/ABI/testing/
Dsysfs-driver-zynqmp-fpga1 What: /sys/bus/platform/drivers/zynqmp_fpga_manager/firmware:zynqmp-firmware:pcap/status
5 Description: (RO) Read fpga status.
7 of the FPGA device. Each bit position in the status value is
9 https://docs.xilinx.com/v/u/en-US/ug570-ultrascale-configuration
24 BIT(4) 0: Start-up sequence has not finished
25 1: Start-up sequence has finished
27 BIT(5) 0: All I/Os are placed in High-Z state
30 BIT(6) 0: Flip-flops and block RAM are write disabled
31 1: Flip-flops and block RAM are write enabled
54 BIT(17) System Monitor over-temperature if set
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/linux-6.15/arch/arm64/boot/dts/xilinx/
Dzynqmp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP
5 * (C) Copyright 2014 - 2021, Xilinx, Inc.
15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
19 #include <dt-bindings/power/xlnx-zynqmp-power.h>
20 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
21 #include <dt-bindings/thermal/thermal.h>
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/linux-6.15/drivers/firmware/xilinx/
Dzynqmp.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2022 Xilinx, Inc.
6 * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc.
14 #include <linux/arm-smccc.h>
27 #include <linux/firmware/xlnx-zynqmp.h>
28 #include <linux/firmware/xlnx-event-manager.h>
29 #include "zynqmp-debug.h"
36 /* BOOT_PIN_CTRL- Used to control the mode pins after boot */
38 /* BOOT_PIN_CTRL_MASK- out_val[11:8], out_en[3:0] */
53 * struct zynqmp_devinfo - Structure for Zynqmp device instance
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