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/qemu/hw/usb/
H A Dhcd-xhci.c2 * USB xHCI controller emulation
32 #include "hcd-xhci.h"
272 XHCIState *xhci; member
305 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid,
308 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid,
311 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v);
312 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v);
425 bool xhci_get_flag(XHCIState *xhci, enum xhci_flags bit) in xhci_get_flag() argument
427 return xhci->flags & (1 << bit); in xhci_get_flag()
430 void xhci_set_flag(XHCIState *xhci, enum xhci_flags bit) in xhci_set_flag() argument
[all …]
H A Dhcd-xhci-sysbus.c2 * USB xHCI controller for system-bus interface
15 #include "hcd-xhci-sysbus.h"
19 static bool xhci_sysbus_intr_raise(XHCIState *xhci, int n, bool level) in xhci_sysbus_intr_raise() argument
21 XHCISysbusState *s = container_of(xhci, XHCISysbusState, xhci); in xhci_sysbus_intr_raise()
32 device_cold_reset(DEVICE(&s->xhci)); in xhci_sysbus_reset()
39 object_property_set_link(OBJECT(&s->xhci), "host", OBJECT(s), NULL); in xhci_sysbus_realize()
40 if (!qdev_realize(DEVICE(&s->xhci), NULL, errp)) { in xhci_sysbus_realize()
43 s->irq = g_new0(qemu_irq, s->xhci.numintrs); in xhci_sysbus_realize()
45 s->xhci.numintrs); in xhci_sysbus_realize()
46 if (s->xhci.dma_mr) { in xhci_sysbus_realize()
[all …]
H A Dhcd-xhci-pci.c2 * USB xHCI controller with PCI bus emulation
9 * SPDX-sourceInfo: Moved the pci specific content for hcd-xhci.c to
10 * hcd-xhci-pci.c
31 #include "hcd-xhci-pci.h"
38 static void xhci_pci_intr_update(XHCIState *xhci, int n, bool enable) in xhci_pci_intr_update() argument
40 XHCIPciState *s = container_of(xhci, XHCIPciState, xhci); in xhci_pci_intr_update()
46 if (enable == !!xhci->intr[n].msix_used) { in xhci_pci_intr_update()
52 xhci->intr[n].msix_used = true; in xhci_pci_intr_update()
56 xhci->intr[n].msix_used = false; in xhci_pci_intr_update()
60 static bool xhci_pci_intr_raise(XHCIState *xhci, int n, bool level) in xhci_pci_intr_raise() argument
[all …]
H A Dhcd-xhci.h2 * USB xHCI controller emulation
27 #include "hw/usb/xhci.h"
30 OBJECT_DECLARE_SIMPLE_TYPE(XHCIState, XHCI)
124 XHCIState *xhci; member
229 bool xhci_get_flag(XHCIState *xhci, enum xhci_flags bit);
230 void xhci_set_flag(XHCIState *xhci, enum xhci_flags bit);
H A Dhcd-xhci-pci.h2 * USB xHCI controller emulation
29 #include "hcd-xhci.h"
31 #define TYPE_XHCI_PCI "pci-xhci"
40 XHCIState xhci; member
H A Dhcd-xhci-nec.c2 * USB xHCI controller emulation
28 #include "hcd-xhci-pci.h"
49 pci->xhci.numintrs = nec->intrs; in nec_xhci_instance_init()
50 pci->xhci.numslots = nec->slots; in nec_xhci_instance_init()
H A Dhcd-xhci-sysbus.h2 * USB xHCI controller for system-bus interface
15 #include "hcd-xhci.h"
26 XHCIState xhci; member
H A Dmeson.build22 system_ss.add(when: 'CONFIG_USB_XHCI', if_true: files('hcd-xhci.c'))
23 system_ss.add(when: 'CONFIG_USB_XHCI_PCI', if_true: files('hcd-xhci-pci.c'))
24 system_ss.add(when: 'CONFIG_USB_XHCI_SYSBUS', if_true: files('hcd-xhci-sysbus.c'))
25 system_ss.add(when: 'CONFIG_USB_XHCI_NEC', if_true: files('hcd-xhci-nec.c'))
H A Dxlnx-versal-usb2-ctrl-regs.c85 * TODO: This should also clear USBSTS.HSE field in USB XHCI register. in ir_status_postw()
/qemu/tests/qtest/
H A Dusb-hcd-xhci-test.c2 * QTest testcase for USB xHCI controller
16 usb_test_hotplug(global_qtest, "xhci", "1", NULL); in test_xhci_hotplug()
52 qtest_add_func("/xhci/pci/hotplug", test_xhci_hotplug); in main()
54 qtest_add_func("/xhci/pci/hotplug/usb-uas", test_usb_uas_hotplug); in main()
57 qtest_add_func("/xhci/pci/hotplug/usb-ccid", test_usb_ccid_hotplug); in main()
60 qtest_start("-device nec-usb-xhci,id=xhci" in main()
/qemu/include/hw/usb/
H A Dxhci.h4 #define TYPE_XHCI "base-xhci"
5 #define TYPE_NEC_XHCI "nec-usb-xhci"
6 #define TYPE_QEMU_XHCI "qemu-xhci"
7 #define TYPE_XHCI_SYSBUS "sysbus-xhci"
H A Dhcd-dwc3.h30 #include "hw/usb/hcd-xhci.h"
31 #include "hw/usb/hcd-xhci-sysbus.h"
/qemu/tests/functional/
H A Dtest_aarch64_raspi4.py48 # '-device', 'qemu-xhci,bus=pcie.1,id=xhci',
49 # '-device', 'usb-kbd,bus=xhci.0',
80 # '-device', 'qemu-xhci,bus=pcie.1,id=xhci',
81 # '-device', 'usb-kbd,bus=xhci.0',
H A Dtest_ppc64_powernv.py96 '-device', 'nec-usb-xhci,bus=bridge1,addr=0x2')
H A Dtest_ppc64_tuxrun.py36 self.vm.add_args('-device', '{"driver":"qemu-xhci","p2":15,"p3":15,'
H A Dtest_ppc64_hv.py117 # Alpine 3.21 kernel seems to crash in XHCI USB driver.
/qemu/docs/system/devices/
H A Dusb.rst4 QEMU can emulate a PCI UHCI, OHCI, EHCI or XHCI USB controller. You can
12 XHCI controller support
15 QEMU has XHCI host adapter support. The XHCI hardware design is much
16 more virtualization-friendly when compared to EHCI and UHCI, thus XHCI
18 supports XHCI (which should be the case for any operating system
21 |qemu_system| -device qemu-xhci
23 XHCI supports USB 1.1, USB 2.0 and USB 3.0 devices, so this is the
117 example shows it connected to an XHCI USB controller and with
124 -device nec-usb-xhci,id=xhci \\
125 -device usb-storage,bus=xhci.0,drive=stick
[all …]
/qemu/docs/
H A Dmultiseat.txt32 -device nec-usb-xhci,bus=head.2,addr=0f.0,id=usb.2 \
37 xhci (usb) controller to the bridge. Then it adds a usb keyboard and
38 usb mouse, both connected to the xhci and linked to the display.
52 ... instead of xhci and usb hid devices.
/qemu/tests/qtest/fuzz/
H A Dgeneric_fuzz_configs.h145 .name = "xhci",
148 "-device qemu-xhci,id=xhci -device usb-tablet,bus=xhci.0 "
155 .objects = "*usb* *uhci* *xhci*",
/qemu/docs/system/arm/
H A Dsbsa.rst26 - System bus XHCI controller
91 The USB controller is an XHCI device, not EHCI.
/qemu/hw/i386/
H A Dmicrovm-dt.c42 #include "hw/usb/xhci.h"
90 const char compat[] = "generic-xhci"; in dt_add_xhci()
284 /* xhci */ in dt_setup_sys_bus()
/qemu/docs/system/
H A Dtarget-i386-desc.rst.inc36 - PCI UHCI, OHCI, EHCI or XHCI USB controller and a virtual USB-1.1
/qemu/include/hw/i386/
H A Dmicrovm.h43 * 10 | pci lnk | xhci (usb=on)
/qemu/docs/specs/
H A Dpci-ids.rst88 PCI xhci usb host adapter
/qemu/hw/vmapple/
H A Dvmapple.c41 #include "hw/usb/hcd-xhci-pci.h"
566 * macOS XHCI driver attempts to schedule events onto even rings 1 & 2
568 * mapping in the XHCI controller works around the problem.

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