Home
last modified time | relevance | path

Searched full:x3 (Results 1 – 25 of 2466) sorted by relevance

12345678910>>...99

/src/sys/arm/freescale/imx/
H A Dimx6_ccmreg.h40 #define SSI_CLK_SEL_M 0x3
80 #define CCGR0_AIPS_TZ1 (0x3 << 0)
81 #define CCGR0_AIPS_TZ2 (0x3 << 2)
82 #define CCGR0_ABPHDMA (0x3 << 4)
84 #define CCGR1_ECSPI1 (0x3 << 0)
85 #define CCGR1_ECSPI2 (0x3 << 2)
86 #define CCGR1_ECSPI3 (0x3 << 4)
87 #define CCGR1_ECSPI4 (0x3 << 6)
88 #define CCGR1_ECSPI5 (0x3 << 8)
89 #define CCGR1_ENET (0x3 << 10)
[all …]
/src/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-serdes.h16 #define J721E_SERDES0_LANE0_IP4_UNUSED 0x3
21 #define J721E_SERDES0_LANE1_IP4_UNUSED 0x3
26 #define J721E_SERDES1_LANE0_SGMII_LANE0 0x3
31 #define J721E_SERDES1_LANE1_SGMII_LANE1 0x3
36 #define J721E_SERDES2_LANE0_SGMII_LANE0 0x3
41 #define J721E_SERDES2_LANE1_SGMII_LANE1 0x3
46 #define J721E_SERDES3_LANE0_IP4_UNUSED 0x3
51 #define J721E_SERDES3_LANE1_IP4_UNUSED 0x3
56 #define J721E_SERDES4_LANE0_IP4_UNUSED 0x3
61 #define J721E_SERDES4_LANE1_IP4_UNUSED 0x3
[all …]
/src/sys/contrib/device-tree/include/dt-bindings/mux/
H A Dti-serdes.h22 #define J721E_SERDES0_LANE0_IP4_UNUSED 0x3
27 #define J721E_SERDES0_LANE1_IP4_UNUSED 0x3
32 #define J721E_SERDES1_LANE0_SGMII_LANE0 0x3
37 #define J721E_SERDES1_LANE1_SGMII_LANE1 0x3
42 #define J721E_SERDES2_LANE0_SGMII_LANE0 0x3
47 #define J721E_SERDES2_LANE1_SGMII_LANE1 0x3
52 #define J721E_SERDES3_LANE0_IP4_UNUSED 0x3
57 #define J721E_SERDES3_LANE1_IP4_UNUSED 0x3
62 #define J721E_SERDES4_LANE0_IP4_UNUSED 0x3
67 #define J721E_SERDES4_LANE1_IP4_UNUSED 0x3
[all …]
/src/contrib/bearssl/src/symcipher/
H A Daes_x86ni_cbcdec.c66 __m128i x0, x1, x2, x3, e0, e1, e2, e3; in br_aes_x86ni_cbcdec_run() local
72 x3 = _mm_loadu_si128((void *)(buf + 48)); in br_aes_x86ni_cbcdec_run()
80 x3 = x2; in br_aes_x86ni_cbcdec_run()
83 x3 = x1; in br_aes_x86ni_cbcdec_run()
88 x3 = x0; in br_aes_x86ni_cbcdec_run()
94 e3 = x3; in br_aes_x86ni_cbcdec_run()
98 x3 = _mm_xor_si128(x3, sk[0]); in br_aes_x86ni_cbcdec_run()
102 x3 = _mm_aesdec_si128(x3, sk[1]); in br_aes_x86ni_cbcdec_run()
106 x3 = _mm_aesdec_si128(x3, sk[2]); in br_aes_x86ni_cbcdec_run()
110 x3 = _mm_aesdec_si128(x3, sk[3]); in br_aes_x86ni_cbcdec_run()
[all …]
H A Daes_x86ni_ctr.c69 __m128i x0, x1, x2, x3; in br_aes_x86ni_ctr_run() local
74 x3 = _mm_insert_epi32(ivx, br_bswap32(cc + 3), 3); in br_aes_x86ni_ctr_run()
78 x3 = _mm_xor_si128(x3, sk[0]); in br_aes_x86ni_ctr_run()
82 x3 = _mm_aesenc_si128(x3, sk[1]); in br_aes_x86ni_ctr_run()
86 x3 = _mm_aesenc_si128(x3, sk[2]); in br_aes_x86ni_ctr_run()
90 x3 = _mm_aesenc_si128(x3, sk[3]); in br_aes_x86ni_ctr_run()
94 x3 = _mm_aesenc_si128(x3, sk[4]); in br_aes_x86ni_ctr_run()
98 x3 = _mm_aesenc_si128(x3, sk[5]); in br_aes_x86ni_ctr_run()
102 x3 = _mm_aesenc_si128(x3, sk[6]); in br_aes_x86ni_ctr_run()
106 x3 = _mm_aesenc_si128(x3, sk[7]); in br_aes_x86ni_ctr_run()
[all …]
H A Daes_pwr8_ctrcbc.c231 #define BLOCK_ENCRYPT_X4_128(x0, x1, x2, x3) \ argument
235 vxor(x3, x3, 0) \
239 vcipher(x3, x3, 1) \
243 vcipher(x3, x3, 2) \
247 vcipher(x3, x3, 3) \
251 vcipher(x3, x3, 4) \
255 vcipher(x3, x3, 5) \
259 vcipher(x3, x3, 6) \
263 vcipher(x3, x3, 7) \
267 vcipher(x3, x3, 8) \
[all …]
/src/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx7ulp-pinfunc.h41 #define IMX7ULP_PAD_PTC4__LPSPI2_PCS1 0x0010 0x02a0 0x3 0x1
49 #define IMX7ULP_PAD_PTC5__LPSPI2_PCS2 0x0014 0x02a4 0x3 0x1
57 #define IMX7ULP_PAD_PTC6__LPSPI2_PCS3 0x0018 0x02a8 0x3 0x1
71 #define IMX7ULP_PAD_PTC8__LPSPI2_SIN 0x0020 0x02b0 0x3 0x1
79 #define IMX7ULP_PAD_PTC9__LPSPI2_SOUT 0x0024 0x02b4 0x3 0x1
87 #define IMX7ULP_PAD_PTC10__LPSPI2_SCK 0x0028 0x02ac 0x3 0x1
95 #define IMX7ULP_PAD_PTC11__LPSPI2_PCS0 0x002c 0x029c 0x3 0x1
102 #define IMX7ULP_PAD_PTC12__LPSPI3_PCS1 0x0030 0x0314 0x3 0x1
110 #define IMX7ULP_PAD_PTC13__LPSPI3_PCS2 0x0034 0x0318 0x3 0x1
119 #define IMX7ULP_PAD_PTC14__LPSPI3_PCS3 0x0038 0x031c 0x3 0x1
[all …]
H A Dimx7d-pinfunc.h17 #define MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
22 #define MX7D_PAD_LPSR_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
27 #define MX7D_PAD_LPSR_GPIO1_IO02__CCM_ENET_REF_CLK1 0x0008 0x0038 0x0564 0x2 0x3
28 #define MX7D_PAD_LPSR_GPIO1_IO02__SAI2_MCLK 0x0008 0x0038 0x0000 0x3 0x0
31 #define MX7D_PAD_LPSR_GPIO1_IO02__USB_OTG1_ID 0x0008 0x0038 0x0734 0x7 0x3
34 #define MX7D_PAD_LPSR_GPIO1_IO03__CCM_ENET_REF_CLK2 0x000C 0x003C 0x0570 0x2 0x3
35 #define MX7D_PAD_LPSR_GPIO1_IO03__SAI3_MCLK 0x000C 0x003C 0x0000 0x3 0x0
38 #define MX7D_PAD_LPSR_GPIO1_IO03__USB_OTG2_ID 0x000C 0x003C 0x0730 0x7 0x3
42 #define MX7D_PAD_LPSR_GPIO1_IO04__UART5_DCE_CTS 0x0010 0x0040 0x0000 0x3 0x0
43 #define MX7D_PAD_LPSR_GPIO1_IO04__UART5_DTE_RTS 0x0010 0x0040 0x0710 0x3 0x4
[all …]
H A Dimxrt1050-pinfunc.h20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
27 #define MXRT1050_IOMUXC_GPIO_EMC_01_XBAR_INOUT3 0x018 0x208 0x610 0x3 0x0
34 #define MXRT1050_IOMUXC_GPIO_EMC_02_XBAR_INOUT4 0x01C 0x20C 0x614 0x3 0x0
41 #define MXRT1050_IOMUXC_GPIO_EMC_03_XBAR_INOUT5 0x020 0x210 0x618 0x3 0x0
48 #define MXRT1050_IOMUXC_GPIO_EMC_04_XBAR_INOUT6 0x024 0x214 0x61C 0x3 0x0
55 #define MXRT1050_IOMUXC_GPIO_EMC_05_XBAR_INOUT7 0x028 0x218 0x620 0x3 0x0
62 #define MXRT1050_IOMUXC_GPIO_EMC_06_XBAR_INOUT8 0x02C 0x21C 0x624 0x3 0x0
69 #define MXRT1050_IOMUXC_GPIO_EMC_07_XBAR_INOUT9 0x030 0x220 0x628 0x3 0x0
76 #define MXRT1050_IOMUXC_GPIO_EMC_08_XBAR_INOUT17 0x034 0x224 0x62C 0x3 0x0
83 #define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXCAN2_TX 0x038 0x228 0x000 0x3 0x0
[all …]
H A Dimx6sl-pinfunc.h16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
24 #define MX6SL_PAD_AUD_RXC__FEC_TX_CLK 0x050 0x2a8 0x70c 0x3 0x0
32 #define MX6SL_PAD_AUD_RXD__FEC_RX_ER 0x054 0x2ac 0x708 0x3 0x0
39 #define MX6SL_PAD_AUD_RXFS__FEC_MDIO 0x058 0x2b0 0x6f4 0x3 0x0
47 #define MX6SL_PAD_AUD_TXC__FEC_RX_DV 0x05c 0x2b4 0x704 0x3 0x0
54 #define MX6SL_PAD_AUD_TXD__FEC_TX_DATA0 0x060 0x2b8 0x000 0x3 0x0
61 #define MX6SL_PAD_AUD_TXFS__FEC_RX_DATA1 0x064 0x2bc 0x6fc 0x3 0x0
68 #define MX6SL_PAD_ECSPI1_MISO__EPDC_BDR0 0x068 0x358 0x000 0x3 0x0
75 #define MX6SL_PAD_ECSPI1_MOSI__EPDC_VCOM1 0x06c 0x35c 0x000 0x3 0x0
82 #define MX6SL_PAD_ECSPI1_SCLK__EPDC_VCOM0 0x070 0x360 0x000 0x3 0x0
[all …]
H A Dimx51-pinfunc.h18 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
23 #define MX51_PAD_EIM_D17__UART2_RXD 0x060 0x3f4 0x9ec 0x3 0x0
29 #define MX51_PAD_EIM_D18__UART2_TXD 0x064 0x3f8 0x000 0x3 0x0
37 #define MX51_PAD_EIM_D19__UART2_RTS 0x068 0x3fc 0x9e8 0x3 0x1
47 #define MX51_PAD_EIM_D21__SRTC_ALARM_DEB 0x070 0x404 0x000 0x3 0x0
62 #define MX51_PAD_EIM_D24__UART3_CTS 0x07c 0x410 0x000 0x3 0x0
67 #define MX51_PAD_EIM_D25__UART3_RXD 0x080 0x414 0x9f4 0x3 0x0
71 #define MX51_PAD_EIM_D26__UART2_RTS 0x084 0x418 0x9e8 0x4 0x3
72 #define MX51_PAD_EIM_D26__UART3_TXD 0x084 0x418 0x000 0x3 0x0
78 #define MX51_PAD_EIM_D27__UART3_RTS 0x088 0x41c 0x9f0 0x3 0x3
[all …]
H A Dimx53-pinfunc.h16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
65 #define MX53_PAD_KEY_COL3__SPDIF_IN1 0x03c 0x364 0x870 0x3 0x0
73 #define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK 0x040 0x368 0x768 0x3 0x0
81 #define MX53_PAD_KEY_COL4__IPU_SISG_4 0x044 0x36c 0x000 0x3 0x0
88 #define MX53_PAD_KEY_ROW4__IPU_SISG_5 0x048 0x370 0x000 0x3 0x0
119 #define MX53_PAD_DI0_PIN4__ESDHC1_WP 0x05c 0x388 0x7fc 0x3 0x0
126 #define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 0x060 0x38c 0x000 0x3 0x0
133 #define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 0x064 0x390 0x000 0x3 0x0
140 #define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 0x068 0x394 0x000 0x3 0x0
147 #define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 0x06c 0x398 0x000 0x3 0x0
[all …]
/src/lib/libpmc/pmu-events/arch/x86/amdzen5/
H A Dl3-cache.json30 "SliceId": "0x3",
31 "ThreadMask": "0x3",
41 "SliceId": "0x3",
42 "ThreadMask": "0x3",
52 "SliceId": "0x3",
53 "ThreadMask": "0x3",
63 "SliceId": "0x3",
64 "ThreadMask": "0x3",
74 "SliceId": "0x3",
75 "ThreadMask": "0x3",
[all …]
/src/lib/libpmc/pmu-events/arch/x86/amdzen6/
H A Dl3-cache.json30 "SliceId": "0x3",
31 "ThreadMask": "0x3",
41 "SliceId": "0x3",
42 "ThreadMask": "0x3",
52 "SliceId": "0x3",
53 "ThreadMask": "0x3",
63 "SliceId": "0x3",
64 "ThreadMask": "0x3",
74 "SliceId": "0x3",
75 "ThreadMask": "0x3",
[all …]
/src/lib/libc/aarch64/string/
H A Dtimingsafe_memcmp.S57 bfi x3, x5, #32, #32 // join words in little endian
59 rev x3, x3 // swap word order
61 cmp x3, x4
62 csetm w0, lo // x0 = x3 >= w4 ? 0 : -1
63 csinc w0, w0, wzr, ls // x0 = x3 <=> w4 ? 1 : 0 : -1
66 .L0916: ldr x3, [x0]
71 cmp x3, x4 // mismatch in first pair?
72 csel x3, x3, x5, ne // use second pair if first pair equal
74 rev x3, x3
76 cmp x3, x4
[all …]
/src/sys/dev/qlnx/qlnxe/
H A Decore_hsi_roce.h134 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3 /* Use roce_flavor enum */
184 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3 /* Use roce_flavor enum */
366 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_MASK 0x3
503 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */
505 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
507 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
541 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */
543 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
545 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
587 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK 0x3 /* timer0cf */
[all …]
H A Decore_hsi_rdma.h61 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */
63 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */
65 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK 0x3 /* cf2special */
118 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */
120 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */
122 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3 /* cf2 */
186 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK 0x3 /* timer0cf */
189 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK 0x3 /* timer1cf */
191 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK 0x3 /* timer2cf */
193 #define E4_USTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
[all …]
H A Decore_hsi_iscsi.h106 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
108 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
110 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
112 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 /* timer_stop_all */
115 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
117 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
119 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
121 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
124 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
126 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
[all …]
/src/sys/crypto/openssl/aarch64/
H A Decp_sm2p256-armv8.S81 mov x3,x7
96 tst x3,#1
125 mov x3,x7
140 tst x3,#1
175 mov x3,x7
191 csel x7,x7,x3,cs
206 mov x3,x7
222 csel x7,x7,x3,cs
260 mov x3,x7
266 subs x3,x3,x11
[all …]
/src/lib/libc/tests/net/getaddrinfo/data/
H A Dno_host_v4v6_prefer_v4.exp31 arg: flags 0x3 family 0 socktype 0 protocol 0 addrlen 0 host (empty) serv http
32 ai1: flags 0x3 family 28 socktype 2 protocol 17 addrlen 28 host :: serv http
33 ai2: flags 0x3 family 28 socktype 1 protocol 6 addrlen 28 host :: serv http
34 ai3: flags 0x3 family 28 socktype 5 protocol 132 addrlen 28 host :: serv http
35 ai4: flags 0x3 family 2 socktype 2 protocol 17 addrlen 16 host 0.0.0.0 serv http
36 ai5: flags 0x3 family 2 socktype 1 protocol 6 addrlen 16 host 0.0.0.0 serv http
37 ai6: flags 0x3 family 2 socktype 5 protocol 132 addrlen 16 host 0.0.0.0 serv http
39 arg: flags 0x3 family 0 socktype 0 protocol 0 addrlen 0 host (empty) serv echo
40 ai1: flags 0x3 family 28 socktype 2 protocol 17 addrlen 28 host :: serv echo
41 ai2: flags 0x3 family 28 socktype 1 protocol 6 addrlen 28 host :: serv echo
[all …]
H A Dno_host_v4v6.exp31 arg: flags 0x3 family 0 socktype 0 protocol 0 addrlen 0 host (empty) serv http
32 ai1: flags 0x3 family 28 socktype 2 protocol 17 addrlen 28 host :: serv http
33 ai2: flags 0x3 family 28 socktype 1 protocol 6 addrlen 28 host :: serv http
34 ai3: flags 0x3 family 28 socktype 5 protocol 132 addrlen 28 host :: serv http
35 ai4: flags 0x3 family 2 socktype 2 protocol 17 addrlen 16 host 0.0.0.0 serv http
36 ai5: flags 0x3 family 2 socktype 1 protocol 6 addrlen 16 host 0.0.0.0 serv http
37 ai6: flags 0x3 family 2 socktype 5 protocol 132 addrlen 16 host 0.0.0.0 serv http
39 arg: flags 0x3 family 0 socktype 0 protocol 0 addrlen 0 host (empty) serv echo
40 ai1: flags 0x3 family 28 socktype 2 protocol 17 addrlen 28 host :: serv echo
41 ai2: flags 0x3 family 28 socktype 1 protocol 6 addrlen 28 host :: serv echo
[all …]
H A Dno_host_v4_only.exp31 arg: flags 0x3 family 0 socktype 0 protocol 0 addrlen 0 host (empty) serv http
32 ai1: flags 0x3 family 28 socktype 2 protocol 17 addrlen 28 host :: serv http
33 ai2: flags 0x3 family 28 socktype 1 protocol 6 addrlen 28 host :: serv http
34 ai3: flags 0x3 family 28 socktype 5 protocol 132 addrlen 28 host :: serv http
35 ai4: flags 0x3 family 2 socktype 2 protocol 17 addrlen 16 host 0.0.0.0 serv http
36 ai5: flags 0x3 family 2 socktype 1 protocol 6 addrlen 16 host 0.0.0.0 serv http
37 ai6: flags 0x3 family 2 socktype 5 protocol 132 addrlen 16 host 0.0.0.0 serv http
39 arg: flags 0x3 family 0 socktype 0 protocol 0 addrlen 0 host (empty) serv echo
40 ai1: flags 0x3 family 28 socktype 2 protocol 17 addrlen 28 host :: serv echo
41 ai2: flags 0x3 family 28 socktype 1 protocol 6 addrlen 28 host :: serv echo
[all …]
/src/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mp-pinfunc.h48 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
52 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
56 #define MX8MP_IOMUXC_GPIO1_IO02__ISP_FLASH_TRIG_0 0x01C 0x27C 0x000 0x3 0x0
61 #define MX8MP_IOMUXC_GPIO1_IO03__ISP_PRELIGHT_TRIG_0 0x020 0x280 0x000 0x3 0x0
65 #define MX8MP_IOMUXC_GPIO1_IO04__ISP_SHUTTER_OPEN_0 0x024 0x284 0x000 0x3 0x0
69 #define MX8MP_IOMUXC_GPIO1_IO05__ISP_FL_TRIG_1 0x028 0x288 0x5D8 0x3 0x0
73 #define MX8MP_IOMUXC_GPIO1_IO06__ISP_SHUTTER_TRIG_1 0x02C 0x28C 0x5E0 0x3 0x0
78 #define MX8MP_IOMUXC_GPIO1_IO07__ISP_FLASH_TRIG_1 0x030 0x290 0x000 0x3 0x0
84 #define MX8MP_IOMUXC_GPIO1_IO08__ISP_PRELIGHT_TRIG_1 0x034 0x294 0x000 0x3 0x0
90 #define MX8MP_IOMUXC_GPIO1_IO09__ISP_SHUTTER_OPEN_1 0x038 0x298 0x000 0x3 0x0
[all …]
/src/sys/arm64/arm64/
H A Dbus_space_asm.S59 * x3 = The kernel address.
65 strb w1, [x3], #1
80 * x3 = The kernel address.
86 strh w1, [x3], #2
101 * x3 = The kernel address.
107 str w1, [x3], #4
122 * x3 = The kernel address.
128 str x1, [x3], #8
143 * x3 = The kernel address.
149 strb w1, [x3], #1
[all …]
/src/contrib/netbsd-tests/lib/libc/net/getaddrinfo/
H A Dno_host_v4v6.exp25 arg: flags 0x3 family 0 socktype 0 protocol 0 addrlen 0 host (empty) serv http
26 ai1: flags 0x3 family 24 socktype 2 protocol 17 addrlen 28 host :: serv http
27 ai2: flags 0x3 family 24 socktype 1 protocol 6 addrlen 28 host :: serv http
28 ai3: flags 0x3 family 2 socktype 2 protocol 17 addrlen 16 host 0.0.0.0 serv http
29 ai4: flags 0x3 family 2 socktype 1 protocol 6 addrlen 16 host 0.0.0.0 serv http
31 arg: flags 0x3 family 0 socktype 0 protocol 0 addrlen 0 host (empty) serv echo
32 ai1: flags 0x3 family 24 socktype 2 protocol 17 addrlen 28 host :: serv echo
33 ai2: flags 0x3 family 24 socktype 1 protocol 6 addrlen 28 host :: serv echo
34 ai3: flags 0x3 family 2 socktype 2 protocol 17 addrlen 16 host 0.0.0.0 serv echo
35 ai4: flags 0x3 family 2 socktype 1 protocol 6 addrlen 16 host 0.0.0.0 serv echo
[all …]

12345678910>>...99