Home
last modified time | relevance | path

Searched full:which (Results 1 – 25 of 1666) sorted by relevance

12345678910>>...67

/qemu/target/hexagon/idef-parser/
H A DREADME.rst42 and other data structures which hold information about the disassemblation
46 with a unique identifier, in this case ``A2_add``, which allows to distinguish
47 variants of the same instruction, and expresses the class to which the
59 - Keep track of which registers, among the declared one, have been
75 As you may notice, the description code modifies the registers which have been
116 which takes instruction semantics in ``semantics_generated.pyinc`` to C-like
118 ``J2_jumpr`` instruction which jumps to an address stored in a register
142 carried out by the ``prepare`` script which runs the C preprocessor on
157 declared anywhere, but rather a symbol which is easy to match in
174 executes the ``main`` function at the end of the ``idef-parser.y`` file, which
[all …]
/qemu/docs/devel/
H A Dtcg-icount.rst10 TCG has long supported a feature known as icount which allows for
27 At its heart icount is simply a count of executed instructions which
30 which represents the amount of elapsed time in the system since
39 vCPU icount_decr field which shared with the machinery for handling
56 might potentially trigger an I/O event, at which point we will need an
70 MMIO isn't the only type of operation for which we might need a
73 to be handled by the individual translators which have the knowledge
74 of which operations are I/O operations.
79 point before the generation of the code which actually does
H A Dmulti-thread-tcg.rst82 translation buffer which contains code running on all cores. Any
106 which when full will force a flush of all translations and start from
129 Any TranslationBlocks which have been patched to jump directly to the
140 The global page table (l1_map) which provides a multi-level look-up
141 for PageDesc structures which contain pointers to the start of a
165 which is designed for concurrent safe lookup.
177 handled with a per-vCPU TLB structure which once populated will allow
179 translated code. It is possible to set flags in the TLB address which
220 some architectures which only need flushes completed by a barrier
284 also implicit memory ordering semantics which comes with each guest
[all …]
H A Dreset.rst11 have to care about others; in particular, problems of order (which object is
14 The main object types which implement this interface are DeviceClass
20 This section documents the APIs which "users" of a resettable object should use
36 warm or bus resets) which may keep certain parts untouched.
39 This is called for a reset which is being done to put the system into a
42 this the same as ``RESET_TYPE_COLD``. The main exception is devices which
44 value on each cold reset, such as RNG seed information, and which they
67 Devices which implement reset methods must treat any unknown ``ResetType``
102 between resetting a bus and resetting the controller bridge which owns it.
130 group which is being reset has had its *enter* phase executed. At this point
[all …]
H A Dloads-stores.rst51 files which are built per-target.
53 There are also functions which take the size as an argument:
57 which performs an unsigned load of ``sz`` bytes from ``ptr``
62 which stores ``val`` to ``ptr`` as an ``{endian}`` order value
77 known as a "mmu index" which controls how that virtual address is
78 translated, plus a ``MemOp`` which contains alignment requirements
88 (e.g. for an alignment fault or MMU fault) which will result in
98 function, which is a return address into the generated code\ [#gpc]_.
250 There are wrapper functions that are to be used which also take care of
274 These functions are a wrapper for ``cpu_ld*_code`` which also perform
[all …]
/qemu/include/hw/arm/
H A Darmsse.h14 * hardware, which include the IoT Kit and the SSE-050, SSE-100 and
16 * - the Arm IoT Kit which is documented in
18 * - the SSE-200 which is documented in
28 * a bus fabric which arranges that some parts of the address
33 * an optional CryptoCell (which we do not model)
54 * + QOM properties "CPU0_FPU", "CPU0_DSP", "CPU1_FPU" and "CPU1_DSP" which
60 * which set the number of MPU regions on the CPUs. If there is only one
63 * which are wired to its NVIC lines 32 .. n+32
65 * CPU 1, which are wired to its NVIC lines 32 .. n+32
66 * + sysbus MMIO region 0 is the "AHB Slave Expansion" which allows
[all …]
/qemu/docs/
H A Dbypass-iommu.txt7 devices in the system can only support go through vIOMMU or not, which
46 - a default host bridge which bypass SMMUv3
47 - a pxb host bridge which go through SMMUv3
48 - a pxb host bridge which bypass SMMUv3
60 - a default host bridge which bypass iommu
61 - a pxb host bridge which go through iommu
62 - a pxb host bridge which bypass iommu
79 RID mapping for devices which do not bypass iommu.
82 of devices which do not bypass iommu, then fill the DMAR drhd struct with
/qemu/include/user/
H A Dsafe-syscall.h52 * to code which needs to modify the data structures used by the
54 * all syscalls which change the thread's signal mask.
59 * for which we need to either return EINTR or arrange for the guest
60 * syscall to be restarted. This category includes both syscalls which
62 * which only restart if there is no handler (kernel returns -ERESTARTNOHAND
63 * or -ERESTART_RESTARTBLOCK), and the most common kind which restart
65 * -ERESTARTSYS). System calls which are only interruptible in some
80 * OK; any which might really block must be via safe_syscall(); for those
81 * which are only technically blocking (ie which we know in practice won't
/qemu/tests/tcg/hppa/
H A Dstby.c16 const char *which, const char *insn, int ofs) in check() argument
22 which, insn, ofs, s->a); in check()
27 which, insn, ofs, s->c); in check()
32 which, insn, ofs, s->b, e); in check()
46 check(&s, E, which, INSN, OFS); \
49 static void test(const char *which) in test() argument
/qemu/docs/system/i386/
H A Dxen.rst9 channel (Xen PV interrupt) delivery. This allows guests which expect to be
50 Xen PIRQs represent an emulated physical interrupt, either GSI or MSI, which
55 of PCI devices (and none which are limited to 32-bit addressing) it may be
59 Xen grant tables are the means by which a Xen guest grants access to its
61 grant tables which are 8 bytes in size, each page (each frame) of the grant
85 The Xen network device is ``xen-net-device``, which becomes the default NIC
95 kernel, which then unplugs the IDE and continues with the Xen PV block device.
116 PV Grub image) as the ``-initrd`` image, which actually just means the first
133 with an actual initramfs, which would need to listed as a second multiboot
/qemu/tests/functional/qemu_test/
H A Ddecorators.py10 from .cmd import which
22 if not which(cmd):
76 Decorator to skip execution of tests which are likely
78 which process untrusted code, unless the
89 Decorator to skip execution of tests which need large
103 Decorator to skip execution of tests which have a really long
/qemu/docs/system/
H A Dtarget-arm.rst18 then built into machines which can vary still further even if they use
25 As well as the more common "A-profile" CPUs (which have MMUs and will
27 Cortex-M4 and Cortex-M33 (which are microcontrollers used in very
35 For QEMU's Arm system emulation, you must specify which board
51 extract the filesystem and use that with a different kernel which
57 ``virt`` board. This is a platform which doesn't correspond to any
68 by the title text of each file, which isn't the same ordering
H A Dintroduction.rst44 includes a wide number of VirtIO devices which are specifically tuned
53 which allows for construction of complex storage topology which can be
71 :ref:`gdbstub<GDB usage>` which allows users to connect GDB and debug
77 QEMU provides a rich and complex API which can be overwhelming to
133 a ``host`` cpu option which simply passes through your host CPU
137 default is TCG, which is purely emulated, so you must specify an
152 In the following example we first define a ``virt`` machine which is a
164 We then define the 4 vCPUs using the ``max`` option which gives us all
H A Ddevice-emulation.rst26 A front end is often paired with a back end, which describes how the
48 which would be a bar device (with the ID of baz) which is attached to
49 the first foo bus (foo.0) at address 1. The foo device which provides
59 devices will be backed by a ``--chardev`` which can redirect the data
61 by ``--blockdev`` which will specify how blocks are handled, for
H A Dbootindex.rst5 which order it should look for a bootable OS on which devices.
11 The ``bootindex`` properties are used to determine the order in which
14 boot priority. There is no particular order in which devices with no
51 Some firmware has limitations on which devices can be considered for
56 8 total devices, any number of which may be disks or virtio-net devices.
H A Dtarget-openrisc.rst10 (the original OpenRISC instruction level simulator) which QEMU supports. For
20 For QEMU's OpenRISC system emulation, you must specify which board model you
37 different kernel which boots on a system that QEMU does emulate.)
42 is a platform which doesn't correspond to any real hardware and is designed for
52 by the title text of each file, which isn't the same ordering
/qemu/tests/qemu-iotests/
H A D11542 # This test relies on refcounts being 64 bits wide (which does not work with
51 # number of clusters which can be described by a single refblock; therefore, at
56 # 512/8 = 64 clusters, therefore the L1 table should cover 128 clusters, which
59 # 8192 * 512/8 = 524,288 clusters which cover a space of 256 MB.
66 # which has a guest disk size of 256 MB.
76 # indeed all the clusters are allocated, which is done by qemu-img check.
/qemu/include/hw/xen/interface/arch-x86/
H A Dxen-x86_64.h74 * int HYPERVISOR_set_segment_base(unsigned int which, unsigned long base)
75 * @which == SEGBASE_* ; @base == 64-bit base address
118 #define __DECL_REG_LOHI(which) union { \ argument
119 uint64_t r ## which ## x; \
120 uint32_t e ## which ## x; \
121 uint16_t which ## x; \
123 uint8_t which ## l; \
124 uint8_t which ## h; \
H A Dxen-x86_32.h99 #define __DECL_REG_LO8(which) union { \ argument
100 uint32_t e ## which ## x; \
101 uint16_t which ## x; \
103 uint8_t which ## l; \
104 uint8_t which ## h; \
113 #define __DECL_REG_LO8(which) uint32_t e ## which ## x argument
/qemu/qapi/
H A Dstats.json72 # The kinds of objects on which one can request statistics.
92 # @provider: provider for which to return statistics.
116 # which to request statistics and optionally the required subset of
122 # @providers: which providers to request statistics from, and
123 # optionally which named values to return within each provider
168 # @qom-path: Path to the object for which the statistics are returned,
213 # @base: base for the multiple of @unit in which the statistic is
219 # @exponent: exponent for the multiple of @unit in which the statistic
/qemu/include/hw/timer/
H A Dsse-counter.h13 * This is a model of the "System counter" which is documented in
26 * consumer device should have a QOM link property which the board
64 * These functions are the interface by which a consumer of
94 * @notifier: Notifier which is notified on counter changes
100 * Devices which consume the timestamp counter can use this as
/qemu/include/hw/misc/
H A Dtz-msc.h18 * The MSC sits in front of a device which can be a bus master (such as
30 * the MPS2 FPGA images it is always tied high, which is awkward to
42 * + Property "idau": an object implementing IDAUInterface, which defines which
43 * addresses should be treated as secure and which as non-secure.
/qemu/docs/specs/
H A Dppc-spapr-hcalls.rst9 which is what PowerVM, the IBM proprietary hypervisor, adheres to.
14 calls which are mostly used as a private interface between the firmware
17 All those hypercalls start at hcall number 0xf000 which correspond
30 "firmware" blob in the guest is a small stub of a few instructions which
65 of memory (supports overlap of source and destination) and XOR which
/qemu/tests/tcg/multiarch/linux/
H A Dlinux-shmat-maps.c25 * The original bug required a non-NULL address, which skipped the in main()
26 * mmap_find_vma step, which could result in a host mapping smaller in main()
32 * Because we are now running the testcase for all guests for which in main()
35 * continue with a system supplied address, which should never fail. in main()
/qemu/include/hw/
H A Dloader.h138 * which will be populated with various load information. @bigendian and
202 * LOAD_UIMAGE_LOADADDR_INVALID (images which do not specify a load
300 * Returns: pointer into the data which backs the matching ROM blob,
303 * This function looks for a ROM blob which covers the specified range
305 * @as. This is useful for code which runs as part of board
306 * initialization or CPU reset which wants to read data that is part
308 * which runs before the ROM loader's reset function has copied the
312 * the specified address, but also for blobs which were loaded to an
315 * which is aliased to also appear at 0x1000_0000, rom_ptr_for_as()
317 * loaded at 0x0000_0000 or 0x1000_0000. Contrast rom_ptr(), which
[all …]

12345678910>>...67