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/qemu/include/migration/
H A Dregister.h37 * @f: QEMUFile where to send the data
61 * @f: QEMUFile where to send the data
85 * @f: QEMUFile where to send the data
98 * where the final data will be flushed at the end of postcopy via
101 * @f: QEMUFile where to send the data
112 * in configurations where multifd device state transfer is supported
181 * @f: QEMUFile where to send the data
198 * @f: QEMUFile where to send the data
258 * @f: QEMUFile where to receive the data
286 * @f: QEMUFile where to receive the data
/qemu/rust/qemu-api/src/
H A Dvmstate.rs329 ($type:ty where $base:tt: VMState $($where:tt)*) => {
330 unsafe impl<$base> VMState for $type where $base: VMState $($where)* {
341 impl_vmstate_transparent!(std::cell::Cell<T> where T: VMState);
342 impl_vmstate_transparent!(std::cell::UnsafeCell<T> where T: VMState);
343 impl_vmstate_transparent!(std::pin::Pin<T> where T: VMState);
344 impl_vmstate_transparent!(crate::cell::BqlCell<T> where T: VMState);
345 impl_vmstate_transparent!(crate::cell::BqlRefCell<T> where T: VMState);
346 impl_vmstate_transparent!(crate::cell::Opaque<T> where T: VMState);
400 ($type:ty where $base:tt: VMState $($where:tt)*) => {
401 unsafe impl<$base> VMState for $type where $base: VMState $($where)* {
[all …]
H A Dirq.rs49 where
57 unsafe impl<T> Sync for InterruptSource<T> where c_int: From<T> {}
78 where
H A Dqom.rs269 /// [`ParentField<T>`](ParentField), where `T` is the parent type
339 /// where `T` is the concrete subclass that is being initialized.
363 where
369 where in as_ptr()
386 where in as_mut_ptr()
396 /// Trait that adds extra functionality for `&T` where `T` is a QOM
399 where
407 where in upcast()
420 where in downcast()
431 where in dynamic_cast()
[all …]
/qemu/include/hw/ppc/
H A Dspapr_ovec.h11 * where each vector entry can be one or more bytes.
14 * structure, where each entry is stored in little-endian so that the
15 * byte ordering reflects that of the documentation, but where each bit
17 * a byte value where the MSB is the left-most bit. Thus, each
/qemu/tests/qtest/libqos/
H A Dvirtio-9p-client.h92 /* file ID of directory from where walk should start (optional) */
328 /* low level variant of directory where new one shall be created */
330 /* high-level variant of directory where new one shall be created */
361 /* low-level variant of directory where new file shall be created */
363 /* high-level variant of directory where new file shall be created */
396 /* low-level variant of directory where symlink shall be created */
398 /* high-level variant of directory where symlink shall be created */
402 /* where symlink will point to (required) */
428 /* low-level variant of directory where hard link shall be created */
430 /* high-level variant of directory where hard link shall be created */
[all …]
/qemu/docs/interop/
H A Dqmp-spec.rst34 Where DATA-STRUCTURE-NAME is any valid JSON data structure, as defined
75 Where:
107 Where:
171 Where:
190 Where:
216 Where:
238 state where it can't parse additional commands. To get it back into
347 error, the Server enters Command mode where capabilities changes take
403 recommended that you prefix your downstream names with ``__RFQDN_`` where
H A Dlive-block-operations.rst150 ``node-name`` (where possible, because ``block-commit`` does not yet, as
175 out where appropriate) when discussing various primitives::
179 Where [A] is the original base image; [B] and [C] are intermediate
254 into it (where live QEMU writes go to)::
276 streaming" of [B] into [C], the resulting image chain will be (where
286 active layer, where 'node-D' is the current active image (by default
299 For `Case-2`_, merge contents of the images [B] and [C] into [D], where
305 images [B] into [C], where [C] ends up referring to [A] as its backing
333 image in a disk image chain where live QEMU will be writing to, into the
337 Again, starting afresh with our example disk image chain, where live
[all …]
/qemu/docs/about/
H A Dindex.rst8 :ref:`System Emulation`, where it provides a virtual model of an
15 where QEMU can launch processes compiled for one CPU on another CPU.
/qemu/docs/devel/
H A Dmulti-thread-tcg.rst28 We introduce a new running mode where each vCPU will run on its own
30 combinations where the host memory model is able to accommodate the
68 The hot-path avoids using locks where possible. The tb_jmp_cache is
157 where tb is the destination block of a jump. Each origin block keeps a
336 pair where the strex instruction will return a flag indicating a
358 problem so far common guests have not implemented patterns where
362 The code also includes a fall-back for cases where multi-threaded TCG
H A Dstyle.rst29 where they have been irreversibly coded into the syntax.
48 There are several places where indent is necessary:
150 to have a consistent prefix to show where they came from. For example,
423 where `MSVC has a different way to lay them out than GCC
424 <https://gcc.gnu.org/onlinedocs/gcc/x86-Type-Attributes.html>`_, or where
432 We also suggest avoiding bitfields even in structures where the exact
458 anyway. There may be some start-up cases where failing is unreasonable
461 Care should be taken to avoid introducing places where the guest could
465 approach. However for larger allocations where we could realistically
555 argument...) However there are a few areas where we allow ourselves to
[all …]
/qemu/qapi/
H A Dsockets.json63 # closed. Only supported for TCP sockets on systems where TCP_KEEPCNT
69 # where TCP_KEEPIDLE socket option is defined (this includes Linux,
74 # supported for TCP sockets on systems where TCP_KEEPINTVL is defined (this
146 # contexts where no monitor context is active.
/qemu/docs/specs/
H A Dedu.rst45 Value is in the form ``0xRRrr00edu`` where:
79 Where to perform the DMA from.
82 Where to perform the DMA to.
/qemu/scripts/coccinelle/
H A Dqobject.cocci1 // Use QDict macros where they make sense
28 // Use QList macros where they make sense
/qemu/tests/tcg/hexagon/
H A Dmem_noshuf_exception.c24 * handle the case where the store raises an exception. In that case, the
31 * We also check that a predicated load where the predicate is false doesn't
97 * Check that a predicated load where the predicate is false doesn't in main()
/qemu/docs/system/
H A Dmanaged-startup.rst25 where additional queries and configuration can be performed via QMP
28 QMP monitor, where the commands do not depend on an initialized
H A Dgeneric-loader.rst37 The number of the CPU's address space where the data should be
85 The memory address where the file should be loaded. This is required
91 memory address where the raw file is loaded or the entry point
/qemu/include/hw/i386/
H A Dsgx-epc.h33 * @addr: starting guest physical address, where @SGXEPCDevice is mapped.
48 * @base: address in guest physical address space where EPC regions start
/qemu/include/hw/misc/
H A Dmps2-scc.h25 * bit 0. Boards where this bit controls memory remapping should
27 * Boards where bit 0 has no special function should leave the GPIO
/qemu/target/arm/tcg/
H A Dneon-ls.decode22 # Encodings for Neon load/store instructions where the T32 encoding
24 # More specifically, this file covers instructions where the A32 encoding is
/qemu/include/hw/dma/
H A Dxlnx_dpdma.h65 * xlnx_dpdma_set_host_data_location: Set the location in the host memory where
71 * @p The buffer where to store the data.
/qemu/docs/devel/testing/
H A Dblkdebug.rst83 exercises the code path where ``BlockAIOCB`` fails and the
113 There are cases where more power is needed to match a particular I/O request in
120 How do we match the 2nd ``write_aio`` but not the first? This is where state
/qemu/migration/
H A Dpostcopy-ram.h29 * Initialise postcopy-ram, setting the RAM to a state where we can go into
36 * At the end of a migration where postcopy_ram_incoming_init was called.
89 * Corner cases are where either thread finishes early and/or errors.
/qemu/hw/pci-host/
H A Dversatile.c29 * PCI_INTERRUPT_LINE register to see where the guest thinks
33 * a slot where broken and correct interrupt mapping would differ.
46 * QEMU) the PCI host device is at slot 0 rather than where
270 * since slot 2 is where we expect this IRQ. in pci_vpb_broken_irq()
338 * board wiring, where the FPGA's P_nINTA input is connected to in pci_vpb_map_irq()
341 * further round from where you might expect. in pci_vpb_map_irq()
/qemu/docs/system/devices/
H A Dvirtio-pmem.rst34 where:
62 to perform fsync/msync. This is different from a real nvdimm backend where

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