xref: /linux/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml (revision ab93e0dd72c37d378dd936f031ffb83ff2bd87ce) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sar2130p-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SAR2130P Display MDSS
8
9maintainers:
10  - Dmitry Baryshkov <lumag@kernel.org>
11
12description:
13  SAR2310P MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14  DPU display controller, DSI and DP interfaces etc.
15
16$ref: /schemas/display/msm/mdss-common.yaml#
17
18properties:
19  compatible:
20    const: qcom,sar2130p-mdss
21
22  clocks:
23    items:
24      - description: Display MDSS AHB
25      - description: Display AHB
26      - description: Display hf AXI
27      - description: Display core
28
29  iommus:
30    maxItems: 1
31
32  interconnects:
33    items:
34      - description: Interconnect path from mdp0 port to the data bus
35      - description: Interconnect path from CPU to the reg bus
36
37  interconnect-names:
38    items:
39      - const: mdp0-mem
40      - const: cpu-cfg
41
42patternProperties:
43  "^display-controller@[0-9a-f]+$":
44    type: object
45    additionalProperties: true
46    properties:
47      compatible:
48        const: qcom,sar2130p-dpu
49
50  "^displayport-controller@[0-9a-f]+$":
51    type: object
52    additionalProperties: true
53    properties:
54      compatible:
55        contains:
56          const: qcom,sar2130p-dp
57
58  "^dsi@[0-9a-f]+$":
59    type: object
60    additionalProperties: true
61    properties:
62      compatible:
63        contains:
64          const: qcom,sar2130p-dsi-ctrl
65
66  "^phy@[0-9a-f]+$":
67    type: object
68    additionalProperties: true
69    properties:
70      compatible:
71        const: qcom,sar2130p-dsi-phy-5nm
72
73required:
74  - compatible
75
76unevaluatedProperties: false
77
78examples:
79  - |
80    #include <dt-bindings/interrupt-controller/arm-gic.h>
81    #include <dt-bindings/power/qcom,rpmhpd.h>
82    #include <dt-bindings/phy/phy-qcom-qmp.h>
83
84    display-subsystem@ae00000 {
85        compatible = "qcom,sar2130p-mdss";
86        reg = <0x0ae00000 0x1000>;
87        reg-names = "mdss";
88
89        interconnects = <&mmss_noc_master_mdp &mc_virt_slave_ebi1>,
90                        <&gem_noc_master_appss_proc &config_noc_slave_display_cfg>;
91        interconnect-names = "mdp0-mem", "cpu-cfg";
92
93        resets = <&dispcc_disp_cc_mdss_core_bcr>;
94
95        power-domains = <&dispcc_mdss_gdsc>;
96
97        clocks = <&dispcc_disp_cc_mdss_ahb_clk>,
98                 <&gcc_gcc_disp_ahb_clk>,
99                 <&gcc_gcc_disp_hf_axi_clk>,
100                 <&dispcc_disp_cc_mdss_mdp_clk>;
101        clock-names = "iface", "bus", "nrt_bus", "core";
102
103        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
104        interrupt-controller;
105        #interrupt-cells = <1>;
106
107        iommus = <&apps_smmu 0x1c00 0x2>;
108
109        #address-cells = <1>;
110        #size-cells = <1>;
111        ranges;
112
113        display-controller@ae01000 {
114            compatible = "qcom,sar2130p-dpu";
115            reg = <0x0ae01000 0x8f000>,
116                  <0x0aeb0000 0x2008>;
117            reg-names = "mdp", "vbif";
118
119            clocks = <&gcc_gcc_disp_ahb_clk>,
120                     <&gcc_gcc_disp_hf_axi_clk>,
121                     <&dispcc_disp_cc_mdss_ahb_clk>,
122                     <&dispcc_disp_cc_mdss_mdp_lut_clk>,
123                     <&dispcc_disp_cc_mdss_mdp_clk>,
124                     <&dispcc_disp_cc_mdss_vsync_clk>;
125            clock-names = "bus",
126                          "nrt_bus",
127                          "iface",
128                          "lut",
129                          "core",
130                          "vsync";
131
132            assigned-clocks = <&dispcc_disp_cc_mdss_vsync_clk>;
133            assigned-clock-rates = <19200000>;
134
135            operating-points-v2 = <&mdp_opp_table>;
136            power-domains = <&rpmhpd RPMHPD_MMCX>;
137
138            interrupt-parent = <&mdss>;
139            interrupts = <0>;
140
141            ports {
142                #address-cells = <1>;
143                #size-cells = <0>;
144
145                port@0 {
146                    reg = <0>;
147
148                    dpu_intf0_out: endpoint {
149                        remote-endpoint = <&mdss_dp0_in>;
150                    };
151                };
152
153                port@1 {
154                    reg = <1>;
155
156                    dpu_intf1_out: endpoint {
157                        remote-endpoint = <&mdss_dsi0_in>;
158                    };
159                };
160
161                port@2 {
162                    reg = <2>;
163
164                    dpu_intf2_out: endpoint {
165                        remote-endpoint = <&mdss_dsi1_in>;
166                    };
167                };
168            };
169
170            mdp_opp_table: opp-table {
171                compatible = "operating-points-v2";
172
173                opp-200000000 {
174                    opp-hz = /bits/ 64 <200000000>;
175                    required-opps = <&rpmhpd_opp_low_svs>;
176                };
177
178                opp-325000000 {
179                    opp-hz = /bits/ 64 <325000000>;
180                    required-opps = <&rpmhpd_opp_svs>;
181                };
182
183                opp-375000000 {
184                    opp-hz = /bits/ 64 <375000000>;
185                    required-opps = <&rpmhpd_opp_svs_l1>;
186                };
187
188                opp-514000000 {
189                    opp-hz = /bits/ 64 <514000000>;
190                    required-opps = <&rpmhpd_opp_nom>;
191                };
192            };
193        };
194
195        displayport-controller@ae90000 {
196            compatible = "qcom,sar2130p-dp",
197                         "qcom,sm8350-dp";
198            reg = <0xae90000 0x200>,
199                  <0xae90200 0x200>,
200                  <0xae90400 0xc00>,
201                  <0xae91000 0x400>,
202                  <0xae91400 0x400>;
203
204            interrupt-parent = <&mdss>;
205            interrupts = <12>;
206            clocks = <&dispcc_disp_cc_mdss_ahb_clk>,
207                     <&dispcc_disp_cc_mdss_dptx0_aux_clk>,
208                     <&dispcc_disp_cc_mdss_dptx0_link_clk>,
209                     <&dispcc_disp_cc_mdss_dptx0_link_intf_clk>,
210                     <&dispcc_disp_cc_mdss_dptx0_pixel0_clk>;
211            clock-names = "core_iface",
212                          "core_aux",
213                          "ctrl_link",
214                          "ctrl_link_iface",
215                          "stream_pixel";
216
217            assigned-clocks = <&dispcc_disp_cc_mdss_dptx0_link_clk_src>,
218                              <&dispcc_disp_cc_mdss_dptx0_pixel0_clk_src>;
219            assigned-clock-parents = <&usb_dp_qmpphy_QMP_USB43DP_DP_LINK_CLK>,
220                                     <&usb_dp_qmpphy_QMP_USB43DP_DP_VCO_DIV_CLK>;
221
222            phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
223            phy-names = "dp";
224
225            #sound-dai-cells = <0>;
226
227            operating-points-v2 = <&dp_opp_table>;
228            power-domains = <&rpmhpd RPMHPD_MMCX>;
229
230            ports {
231                #address-cells = <1>;
232                #size-cells = <0>;
233
234                port@0 {
235                    reg = <0>;
236                    mdss_dp0_in: endpoint {
237                        remote-endpoint = <&dpu_intf0_out>;
238                    };
239                };
240
241                port@1 {
242                    reg = <1>;
243                    mdss_dp0_out: endpoint {
244                        remote-endpoint = <&usb_dp_qmpphy_dp_in>;
245                    };
246                };
247        };
248
249        dp_opp_table: opp-table {
250                compatible = "operating-points-v2";
251
252                opp-162000000 {
253                    opp-hz = /bits/ 64 <162000000>;
254                    required-opps = <&rpmhpd_opp_low_svs_d1>;
255                };
256
257                opp-270000000 {
258                    opp-hz = /bits/ 64 <270000000>;
259                    required-opps = <&rpmhpd_opp_low_svs>;
260                };
261
262                opp-540000000 {
263                    opp-hz = /bits/ 64 <540000000>;
264                    required-opps = <&rpmhpd_opp_svs_l1>;
265                };
266
267                opp-810000000 {
268                    opp-hz = /bits/ 64 <810000000>;
269                    required-opps = <&rpmhpd_opp_nom>;
270                };
271            };
272        };
273
274        dsi@ae94000 {
275            compatible = "qcom,sar2130p-dsi-ctrl",
276                         "qcom,mdss-dsi-ctrl";
277            reg = <0x0ae94000 0x400>;
278            reg-names = "dsi_ctrl";
279
280            interrupt-parent = <&mdss>;
281            interrupts = <4>;
282
283            clocks = <&dispcc_disp_cc_mdss_byte0_clk>,
284                     <&dispcc_disp_cc_mdss_byte0_intf_clk>,
285                     <&dispcc_disp_cc_mdss_pclk0_clk>,
286                     <&dispcc_disp_cc_mdss_esc0_clk>,
287                     <&dispcc_disp_cc_mdss_ahb_clk>,
288                     <&gcc_gcc_disp_hf_axi_clk>;
289            clock-names = "byte",
290                          "byte_intf",
291                          "pixel",
292                          "core",
293                          "iface",
294                          "bus";
295
296            assigned-clocks = <&dispcc_disp_cc_mdss_byte0_clk_src>,
297                              <&dispcc_disp_cc_mdss_pclk0_clk_src>;
298            assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
299
300            operating-points-v2 = <&dsi_opp_table>;
301            power-domains = <&rpmhpd RPMHPD_MMCX>;
302
303            phys = <&mdss_dsi0_phy>;
304            phy-names = "dsi";
305
306            #address-cells = <1>;
307            #size-cells = <0>;
308
309            ports {
310                #address-cells = <1>;
311                #size-cells = <0>;
312
313                port@0 {
314                    reg = <0>;
315
316                    mdss_dsi0_in: endpoint {
317                        remote-endpoint = <&dpu_intf1_out>;
318                    };
319                };
320
321                port@1 {
322                    reg = <1>;
323
324                    mdss_dsi0_out: endpoint {
325                    };
326                };
327            };
328
329            dsi_opp_table: opp-table {
330                compatible = "operating-points-v2";
331
332                opp-187500000 {
333                    opp-hz = /bits/ 64 <187500000>;
334                    required-opps = <&rpmhpd_opp_low_svs>;
335                };
336
337                opp-300000000 {
338                    opp-hz = /bits/ 64 <300000000>;
339                    required-opps = <&rpmhpd_opp_svs>;
340                };
341
342                opp-358000000 {
343                    opp-hz = /bits/ 64 <358000000>;
344                    required-opps = <&rpmhpd_opp_svs_l1>;
345                };
346            };
347        };
348
349        mdss_dsi0_phy: phy@ae94400 {
350            compatible = "qcom,sar2130p-dsi-phy-5nm";
351            reg = <0x0ae95000 0x200>,
352                  <0x0ae95200 0x280>,
353                  <0x0ae95500 0x400>;
354            reg-names = "dsi_phy",
355                        "dsi_phy_lane",
356                        "dsi_pll";
357
358            #clock-cells = <1>;
359            #phy-cells = <0>;
360
361            clocks = <&dispcc_disp_cc_mdss_ahb_clk>,
362                     <&rpmhcc_rpmh_cxo_clk>;
363            clock-names = "iface", "ref";
364        };
365
366        dsi@ae96000 {
367            compatible = "qcom,sar2130p-dsi-ctrl",
368                         "qcom,mdss-dsi-ctrl";
369            reg = <0x0ae96000 0x400>;
370            reg-names = "dsi_ctrl";
371
372            interrupt-parent = <&mdss>;
373            interrupts = <5>;
374
375            clocks = <&dispcc_disp_cc_mdss_byte1_clk>,
376                     <&dispcc_disp_cc_mdss_byte1_intf_clk>,
377                     <&dispcc_disp_cc_mdss_pclk1_clk>,
378                     <&dispcc_disp_cc_mdss_esc1_clk>,
379                     <&dispcc_disp_cc_mdss_ahb_clk>,
380                     <&gcc_gcc_disp_hf_axi_clk>;
381            clock-names = "byte",
382                          "byte_intf",
383                          "pixel",
384                          "core",
385                          "iface",
386                          "bus";
387
388            assigned-clocks = <&dispcc_disp_cc_mdss_byte1_clk_src>,
389                              <&dispcc_disp_cc_mdss_pclk1_clk_src>;
390            assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
391
392            operating-points-v2 = <&dsi_opp_table>;
393            power-domains = <&rpmhpd RPMHPD_MMCX>;
394
395            phys = <&mdss_dsi1_phy>;
396            phy-names = "dsi";
397
398            #address-cells = <1>;
399            #size-cells = <0>;
400
401            ports {
402                #address-cells = <1>;
403                #size-cells = <0>;
404
405                port@0 {
406                    reg = <0>;
407
408                    mdss_dsi1_in: endpoint {
409                        remote-endpoint = <&dpu_intf2_out>;
410                    };
411                };
412
413                port@1 {
414                    reg = <1>;
415
416                    mdss_dsi1_out: endpoint {
417                    };
418                };
419            };
420        };
421
422        mdss_dsi1_phy: phy@ae97000 {
423            compatible = "qcom,sar2130p-dsi-phy-5nm";
424            reg = <0x0ae97000 0x200>,
425                  <0x0ae97200 0x280>,
426                  <0x0ae97500 0x400>;
427            reg-names = "dsi_phy",
428                        "dsi_phy_lane",
429                        "dsi_pll";
430
431            #clock-cells = <1>;
432            #phy-cells = <0>;
433
434            clocks = <&dispcc_disp_cc_mdss_ahb_clk>,
435                     <&rpmhcc_rpmh_cxo_clk>;
436            clock-names = "iface", "ref";
437        };
438    };
439...
440