| /linux-6.15/Documentation/devicetree/bindings/clock/ |
| D | qcom,ipq9574-nsscc.yaml | 77 <&uniphy 0>,
78 <&uniphy 1>,
79 <&uniphy 2>,
80 <&uniphy 3>,
81 <&uniphy 4>,
82 <&uniphy 5>,
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| D | qcom,ipq5018-gcc.yaml | 33 - description: UNIPHY RX clock source
34 - description: UNIPHY TX clk source
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| /linux-6.15/Documentation/devicetree/bindings/phy/ |
| D | qcom,ipq5332-uniphy-pcie-phy.yaml | 4 $id: http://devicetree.org/schemas/phy/qcom,ipq5332-uniphy-pcie-phy.yaml#
7 title: Qualcomm UNIPHY PCIe 28LP PHY
19 - qcom,ipq5332-uniphy-pcie-phy
61 compatible = "qcom,ipq5332-uniphy-pcie-phy";
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/bios/ |
| D | command_table_helper.c | 121 * // =00: Digital Transmitter1 ( UNIPHY linkAB )
122 * // =01: Digital Transmitter2 ( UNIPHY linkCD )
123 * // =02: Digital Transmitter3 ( UNIPHY linkEF )
179 * each, A+B, C+D, E+F, Uniphy A, C and E are enumerated as link 0 in in dal_cmd_table_helper_assign_control_parameter()
195 * =00: Digital Transmitter1 ( UNIPHY linkAB ) in dal_cmd_table_helper_assign_control_parameter()
196 * =01: Digital Transmitter2 ( UNIPHY linkCD ) in dal_cmd_table_helper_assign_control_parameter()
197 * =02: Digital Transmitter3 ( UNIPHY linkEF ) in dal_cmd_table_helper_assign_control_parameter()
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| D | command_table_helper2.c | 145 * // =00: Digital Transmitter1 ( UNIPHY linkAB )
146 * // =01: Digital Transmitter2 ( UNIPHY linkCD )
147 * // =02: Digital Transmitter3 ( UNIPHY linkEF )
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/dio/dcn301/ |
| D | dcn301_dio_link_encoder.c | 124 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. in dcn301_link_encoder_construct()
125 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY. in dcn301_link_encoder_construct()
126 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer in dcn301_link_encoder_construct()
127 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS. in dcn301_link_encoder_construct()
130 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. in dcn301_link_encoder_construct()
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/dcn201/ |
| D | dcn201_link_encoder.c | 156 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. in dcn201_link_encoder_construct()
157 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY. in dcn201_link_encoder_construct()
158 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer in dcn201_link_encoder_construct()
159 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS. in dcn201_link_encoder_construct()
162 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. in dcn201_link_encoder_construct()
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/dio/dcn30/ |
| D | dcn30_dio_link_encoder.c | 135 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. in dcn30_link_encoder_construct()
136 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY. in dcn30_link_encoder_construct()
137 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer in dcn30_link_encoder_construct()
138 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS. in dcn30_link_encoder_construct()
141 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. in dcn30_link_encoder_construct()
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_link_encoder.c | 376 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. in dcn21_link_encoder_construct()
377 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY. in dcn21_link_encoder_construct()
378 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer in dcn21_link_encoder_construct()
379 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS. in dcn21_link_encoder_construct()
382 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. in dcn21_link_encoder_construct()
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/dio/dcn20/ |
| D | dcn20_link_encoder.c | 435 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. in dcn20_link_encoder_construct()
436 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY. in dcn20_link_encoder_construct()
437 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer in dcn20_link_encoder_construct()
438 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS. in dcn20_link_encoder_construct()
441 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. in dcn20_link_encoder_construct()
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| D | dcn20_link_encoder.h | 204 SRI(CHANNEL_XBAR_CNTL, UNIPHY, id)
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| /linux-6.15/drivers/phy/qualcomm/ |
| D | phy-qcom-uniphy-pcie-28lp.c | 215 .compatible = "qcom,ipq5332-uniphy-pcie-phy",
278 .name = "qcom-uniphy-pcie",
285 MODULE_DESCRIPTION("PCIE QCOM UNIPHY driver");
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| D | Kconfig | 158 bool "PCIE UNIPHY 28LP PHY driver"
165 Enable this to support the PCIe UNIPHY 28LP phy transceiver that
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| D | Makefile | 20 obj-$(CONFIG_PHY_QCOM_UNIPHY_PCIE_28LP) += phy-qcom-uniphy-pcie-28lp.o
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/dio/dcn31/ |
| D | dcn31_dio_link_encoder.c | 327 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. in dcn31_link_encoder_construct()
328 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY. in dcn31_link_encoder_construct()
329 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer in dcn31_link_encoder_construct()
330 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS. in dcn31_link_encoder_construct()
333 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. in dcn31_link_encoder_construct()
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_link_encoder.c | 850 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. in dce110_link_encoder_construct()
851 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY. in dce110_link_encoder_construct()
852 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer in dce110_link_encoder_construct()
853 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS. in dce110_link_encoder_construct()
856 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. in dce110_link_encoder_construct()
1752 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. in dce60_link_encoder_construct()
1753 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY. in dce60_link_encoder_construct()
1754 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer in dce60_link_encoder_construct()
1755 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS. in dce60_link_encoder_construct()
1758 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. in dce60_link_encoder_construct()
|
| /linux-6.15/drivers/gpu/drm/radeon/ |
| D | atombios_crtc.c | 1842 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
1844 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1851 * - PPLL0 is available to all UNIPHY (DP only)
1852 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1855 * - DCPLL is available to all UNIPHY (DP only)
1856 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1859 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1918 /* UNIPHY A uses PPLL2 */ in radeon_atom_pick_pll()
1921 /* UNIPHY B/C/D/E/F */ in radeon_atom_pick_pll()
1937 /* UNIPHY B/C/D/E/F */ in radeon_atom_pick_pll()
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| D | atombios.h | 699 // =0: UNIPHY or PCIEPHY
953 …USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid…
1025 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1026 // =1 Dig Transmitter 2 ( Uniphy CD )
1027 // =2 Dig Transmitter 3 ( Uniphy EF )
1031 …UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when…
1032 …// =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means ma…
1039 …UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when…
1040 …// =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means ma…
1044 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
[all …]
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| D | atombios_encoders.c | 780 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
783 * DIG1 can drive UNIPHY link A or link B
784 * DIG2 can drive UNIPHY link B or LVTMA
815 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/dio/dcn10/ |
| D | dcn10_link_encoder.c | 712 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. in dcn10_link_encoder_construct()
713 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY. in dcn10_link_encoder_construct()
714 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer in dcn10_link_encoder_construct()
715 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS. in dcn10_link_encoder_construct()
718 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. in dcn10_link_encoder_construct()
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| D | dcn10_link_encoder.h | 114 /* UNIPHY */
|
| /linux-6.15/drivers/gpu/drm/amd/include/ |
| D | atombios.h | 835 // =0: UNIPHY or PCIEPHY
1159 …USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in ob…
1231 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1232 // =1 Dig Transmitter 2 ( Uniphy CD )
1233 // =2 Dig Transmitter 3 ( Uniphy EF )
1237 …UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when…
1238 …// =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means ma…
1245 …UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when…
1246 …// =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means ma…
1250 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
[all …]
|
| /linux-6.15/drivers/gpu/drm/msm/dsi/phy/ |
| D | dsi_phy_28nm.c | 324 /* DSI Uniphy lock detect setting */ in _dsi_pll_28nm_vco_prepare_hpm()
427 /* DSI Uniphy lock detect setting */ in dsi_pll_28nm_vco_prepare_8226()
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/ |
| D | dc_types.h | 667 /* Pcie or Uniphy */
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/link/protocols/ |
| D | link_edp_panel_control.c | 770 /* Hardcoded for now. Can be Pcie or Uniphy (or Unknown)*/ in edp_setup_psr()
|